Copyrighted Material

MM and MTM for Mobility

One main purpose of this chapter is to introduce the hardware technology that delivers mobility. Before introducing the hardware technology, however, it is important to elaborate on the content and extent of mobility. Of course, mobility is not possible without communication networks, wired or the otherwise. Here we review the convergence of communications (wired with wireless, switched circuits with packeted circuits, voice with data, GERAN with UTRAN, wireless WAN with wireless LAN) first. The convergence of communications begins with a consolidation of circuit‐ and packet‐switched networks at low‐level physical layers (wired networks, including copper twisted pairs and optical fiber cables), then air interfaces with the wireless‐WAN (commonly known as 2G, 3G, and 4G) and wireless‐LAN (commony known as wifi). The tasks are done through 3GPP releases up to Rel 7 for 3G. Currently, 5G is under development, thus, 5G goals and key technologies to achieve the goals are discussed. Since mobility is actually achieved by combination of wired and wireless networks, we then review the key products employed in both networks. We found the communication products encompass different industries; for example, optical fiber industry where silica glass is the main material used for optical links, cabling industry where copper and plastics are heavily used to form connectors and cables, and semiconductor and PCB (printed circuit board) industries where silicon and organic materials are employed for devices and components miniaturization. After reviewing the products employed in wired and wireless networks, it is time to take a look at hardware fabrication and integration technologies, from which communication products are constructed. In this chapter, we discuss state‐of‐the‐art MM (more Moore approach) and MTM (more than Moore approach) processes. Both are planar processing technologies, and suitable for mass production, with MM employing semiconductors COPYRIGHTEDand MTM PCB (LTCC, too). MM MATERIAL takes place in wafer foundries and MTM in OSAT (outsourced semiconductor assembly and test) sites. MM and MTM are traditionally known as IC fabrication and packaging specialities. In Section 1.3, we review briefly the state of the art MM and MTM hardware technologies in realizing transistors and a combo consisting of A‐series AP and its mobile memory, the most critical device and component in handheld mobiles. Transistor engineering is the most important achievement in MM in recent years, which can be represented by HKMG (high‐k metal gate) and TriGate developments. Figure 1.1 below shows device construction with HKMG. The combination of the high‐k

3D IC and RF SiPs: Advanced Stacking and Planar Solutions for 5G Mobility, First Edition. Lih-Tyng Hwang and Tzyy-Sheng Jason Horng. © 2018 John Wiley & Sons Singapore Pte. Ltd. Published 2018 by John Wiley & Sons Singapore Pte. Ltd. Companion website: www.wiley.com/go/hwangic

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High-k Metal gate Figure 1.1 HKMG, three sides are high‐k dielectric, and the gate is metalized at the top surface.

S Oxide

Silicon

TriGate Figure 1.2 A FinFET constructing from multiple TriGates; each ridge in a TriGate is covered on D three sides.

Oxide S

Silicon

material (the darker layer) and metal gate gives the transistor much better performance (reduced leakage and enhanced transistor stability, respectively) than would be possible with a traditional silicon dioxide (dielectric) and polysilicon (non‐metal) gate. Figure 1.2 shows a 3D FinFET transistor constructed with multiple TriGates (triple- gates). It is named because each ridge in a TriGate is covered on three sides. The technology, along with Intel’s gate last approach, extended Moore’s Law into 32 nm (technology node) and below; therefore, is considered an important MM contribution. In September of each year, the world, especially the electronics industry and business, are all watching the birth of a new iPhone, in which A‐series AP and its main mobile memory LPDDR are focused. It is because A‐series AP and its mobile memory are the heart, literally, of many Apple iPhones, and mass production of them (the A‐series AP device or the PoP combo of AP and the LPDDR memory) represents a yearly crowning achievement. A‐series AP (A4, A5, …) and its mobile memory, LPDDR, are packaged in an advanced package, the so‐called “PoP (packaged on a package),” shown in Figure 1.3. Note that the dual‐die memory in Figure 1.3 is not symmetrically placed with respect to the AP below. Wirebonding may be one of the factors. The dual‐LPDDR set is on the top, whereas the application processor is on the bottom. The configuration may enhance greatly the processor’s performance; however, heat dissipation by the AP is a concern. In later AP(A7)/ LPDDR3 PoP for iPhone 5S, there are three rows of TMVs (through molding vias, see Figures 3.24 and 3.25 in Chapter 3), whereas there are only two rows, as shown in Figure 1.3. The added row may be designed to assist heat removal.

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Figure 1.3 A cross‐sectional view of AP(A4)/LPDDR combo in PoP for iPhone 4. Two rows of TMVs are conspicuous on each side. Source: Image courtesy of Chipworks Inc.

A9 employs 14 nm and/or 16 nm, depending on the manufacturer Samsumg (14 nm) or TSMC (16 nm). Various sources have indicated A10, used by iPhone 7 and available in September 2016, may be still fabricated using TSMC’s 16 nm technology; neverthe- less, the most advanced 10 nm technology is likely to be used to produce Qualcom’s AP, Snapdragon 835 by Samsung.[1] Because both MM and MTM hardware are introduced in this chapter, it is important to understand the difference between them. Let’s use the following table to illustrate the differences (Table 1.1). Figures 1.50 and 1.51 (shown later in this chapter) are an important summary to this chapter. Figure 1.50 illustrates the state of the art packages empolyed; x‐axis indicates the level of integration, and y‐axis the level of monolithicity (versus hybrid approach). Figure 1.51 illustrates the business division between MM and MTM. MTM hardware technology will be important in meeting the demands of the future 5G mobility. The topic is discussed briefly at the end of the chapter; but, in Chapter 9 more details on future hardware technologies for 5G mobility are offered.

Table 1.1 MM and MTM comparison.

MM (Wafer foundry) MTM (OSAT)

Processing Photo‐lithography, ion Molding, underfill, screen printing, electrolytic techniques implantation, CVD, sputtering, plating, electro‐less plating, wirebonding, etching flip‐chip bumping, reflow, SMT Substrates Silicon and GaAs (III‐V) MLO, MLC, Hi‐res silicon and glass Metallization W, Al, and Cu in Si; Au in III‐V Ti, Cr, W, Ni, Pd, Cu, Pb, Sn, Ag, etc..

1.1 Convergence in Communications and the Future, 5G

Here, we discuss the convergence of communications, which occurred during the development of 3G around 2000 to 2003, followed by later refinements (termed 3.5G, 3.9G, and B4G). Lastly, future wireless communications, 5G, for example, as well as its goals and the technologies needed to achieve the goals, will be discussed.

1.1.1 From 1980 (1G) to 2010 (4G)

In the 1980s, the first cellular phones by Motorola were all analog ones. These analog phones used the AMPS (advanced mobile phone system) cellular system developed by

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AT&T; they consumed more power, had shorter utility hours, and thus, they could not compete with the later digital GSM phones developed by the European community, represented by Nokia. The GSM phones, being digital, consumed less power, and quickly dominated the market. Motorola had to alter their courses of phone development, and thus ditched analog phones, and soon after adopted GSM and UMTS standards, later termed 2G and 3G, respectively. Motorola’s analog phones are considered as 1G, retrospectively. Key features of 1G include 1) being analog in nature, 2) having a bandwidth (BW) of 30 kHz; note that human voices have a highest pitch of 20 KHz; and 3) carrying voice only. The 2G development span lasted over the entire 1990s: first it added GPRS (2.5G) and then EDGE (2.75G) capability along the way. 2G is digital in nature, and it carries voice and data (e.g., short message service, SMS). It had a BW of 200 kHz (124 channels share 25 MHz); for example, GSM900 (band 8) downlink band is between 935 MHz and 960 MHz. The original 2G carries only voices over the circuit‐switched (CS) networks (e.g., PSTN and POTS). GPRS added packet capability, extending the circuit switched only 2G to 2.5G, which includes packet switched (PS) networks (e.g., ethernet). 2.5G had a digital data rate of 144 kbps. IMT‐2000 under ITU‐R began in 1999. It set out to integrate GSM and UTRA (UMTS terrestrial radio access) into one global standard, UMTS (Universal Mobile Telecommunications System). The tasks were accomplished by 3GPP (the Third Generation Partnership Project) in releases: Rel 99 and Rels 4, 5, 6, and 7 roughly cor- respond to the calendar years (e.g., Release 4 in 2004). Thus, Rel 99 on W‐CDMA (wideband CDMA, which employs 5 MHz bandwidth), development Release 4 on TDD, Release 5 on HSDPA, Release 6 on HSUPA, and Release 7 on HSPA+. After Release 7, the releases started to lag behind the progress of the calendar years. Figure 1.4 shows GERAN (GSM‐EDGE radio access networks) and UTRAN (UMTS terrestrial radio access networks) are connected the core network (CN). CN is a converged physical layer, which includes circuit‐switched PSTN/ISDN and POTS and packet‐switched ethernet, as shown in Figure P.5. Physically, the CN employs both

Um Abis BSS I DL u PSTN/ISDN A U BTS BSC POTS Landline E IuCS DSL, ADSL GPRS CS GERAN (GSM-EDGE)

Sectors UL DL RNS Gb UE Iub PS Node B RNC Ethernet WWW/PDN IuPS CN UTRAN

Figure 1.4 In IMT 2000 development by 3GPP, GERAN (2.75G) and UTRAN (WCDMA) merged to form UMTS (3G).

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IMT-2000 IMT-ADV LTE-R8 LTE-R13 (2007) INTRODUCTION OF LTE CONSIDERATIONS Peak: 1 Gbps (Goal for 4G) DL = 300Mbps UNLICENSED BANDS LTE-R11 UL = 75 Mbps 1GHz BANDWIDTH LTE-A LAUNCH 20 MHz LTE-M2M IoT 4×4 MIMO DL 1990 1999 2000-20082009 2010 2011 2012 2013 2014 2015 2020

GERAN R99 R4, 5, 6, 7 R8, R9 LTE-R10 LTE-R12 5G 2.75G UTRAN UTRAN CDMA2000 LTE-ADVANCED INTRODUCTION ENHANCEMENTS: E-UTRAN FDD TDD/TD-CDMA DL = 3Gbps (B4G) CARRIER AGGREGATION TD-SCDMA UL = 1.5Gbps ACTIVE ANTENNA SYSTEMS CA = 100MHz SPATIAL MULTIPLEXING (Mass. MIMO, Beamform) W-CDMA3G, CDMA2000, 8×8 MIMO DL

and TD-SCDMA SPECTRAL EFFICIENCY

R8: DL = 15 bits/sec/Hz, UL = 3.75 bits/sec/Hz R12: DL = 30 bits/sec/Hz, UL = 15 bits/sec/Hz

Figure 1.5 B4G (Beyond 4G) and 5G.

twisted pairs category cables (copper based) and optical‐fiber cables. GSM network (GERAN) connects a mobile user to ISDN/PSTN (digital voice network) and PDN (Packet Data Network). So does UTRAN. While GSM (GERAN) uses strictly a FDD air‐interface; UTRA (UTRAN) has both TDD and FDD. UTRA‐FDD employs 2,110 to 2,170 MHz as its downlink band, and 1,920 to 1,980 MHz band as its uplink band. There are 12 channels in each link (either downlink or uplink), 5 MHz bandwidth for each channel (thus, WCDMA). In UMTS developed by 3GPP, there were two CDMA‐TDD air interfaces: UTRA‐TDD and TD‐ SCDMA. UTRA‐TDD has a 1900 to 1920 MHz band, and 5 MHz bandwidth for each channel. TD‐SCDMA has 1.6 MHz bandwidth. In Rels 8 and 9, evolved universal terrestrial radio access (E‐UTRA) and CDMA2000 (3GPP2, 1.25 Mz bandwidth) were developed. WCDMA: 2.4 Mbps on one pair of 5 MHz, chip rate 3.84 Mcps; CDMA2000 chip rate 1.22 Mcps; CDMA2000 1xEV‐DO Release 0: 2.4 Mbps, Release A: 3.1 Mbps, and Release B: 9.3 Mbps on one or several pairs of 1.25 MHz bands. BTS and Node B perform similar logical and network functions for GERAN and UTRAN, respectively. However, they are some differences between BTS (base transceiver station) and Node B. Whether BTS is a cell or not depends on the type of the antenna; if the antenna is omni‐directional, one BTS constitutes one cell; if the antenna is directional, one BTS can cover different cells. Under Node B, there are sectors; and a sector is similar to a cell. Under UTRAN, a UE can be controlled by multiple Node Bs; making soft handover a reality. TDD is half‐duplexing; FDD is full‐duplexing. FDD doubles the data rate because of full‐duplexing. However, FDD uses lots of frequency spectrum, though, generally at least twice the spectrum needed by TDD. Plus, the so‐called guard bands are not usea- ble, either. Given the scarcity and expense of spectrum, these are real disadvantages. Another disadvantage with FDD is the difficulty of using special antenna techniques like multiple‐input multiple‐output (MIMO) and beamforming. The downside is that successful implementation of TDD needs a very precise timing and synchronization system at both the transmitter and receiver to make sure time slots do not overlap or otherwise interfere with one another. Timing is often synched to precise GPS‐derived atomic clock standards.

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TDD can be realized using a SPDT switch; FDD can be realized using duplexers, which can be constructed using diodes, circulators, or cavities. As a note, diplexer is a device that separates or combine frequencies of two bands, for example, 2.45 GHz and 5 GHz wifi signals, or GSM900 and DCS1800. Because of self‐interference, FDD is not exactly full‐duplexing; for example, in GSM FDD, the DL and UL are off by three bursts (577 µs x 3 = 1.73 ms); thus, simplifying the complexity of electronics. The self‐interference can cause damage to the near‐by receiver when the transmitter is transmitting simultaneously. By a three‐burst offset, the damage from self‐interference can be greatly reduced. In Chapter 6, filters, switches, and duplexer using FBAR are discussed. In 2007, IMT‐advanced was organized, with a goal of achieving data rate of 1 Gbps around 2010 to 2013. Peak data rates must be up to 100 Mbps in high‐mobility situa- tions and up to 1 Gbps for low‐mobility/stationary applications. This is considered as a standard definition of 4G: employing a BW of 5, 20, 40, up to 80 MHz, to achieve peak throughput rates that exceed 1 gigabit per second (gbps, spectral efficiency of 15 bit/s/Hz). Spectral efficiency[2] can be obtained by the dividing data rates by the physical bandwidth (bit/s/Hz). Spectral efficiency can be obtained from MCS table, which relates the data rate (Mbps, Gbps, etc.) to the physical bandwidths (80 MHz, 160 MHz, etc.), in terms of modulation techniques (CDMA and OFDM), coding schemes, and data streams through MIMO mechanism. The table can be found in references [3–5]. For MCS index 15 (64‐QAM, coding 5/6, 2 data stream), the spectral efficiency is 7.5 bit/s/ Hz (300 Mbps/40 MHz), when the guard interval (GI) is 400 ns. In 5G, the spectal efficiency can be as high as 30. Around 2009 (3GPP‐Rel 8), LTE was introduced, with a physical bandwidth of 20 MHz, a goal of 300 Mbps data rate was targeted (4x4 MIMO DL, a spectral efficiency of 16 bit/s/Hz max.).

1.1.2 LTE‐A and Rel 10 in 2010s

In 2011, LTE‐advanced (3GPP Rel 10), was introduced. LTE‐advanced (or the true LTE) proposed to employ channel aggregation and high data streams of 8x8 MIMO (DL). From an aggregation of five 20 MHz bands, it is able to provide a physical bandwidth of 100 MHz. Along with the 8x8 MIMO and and 128 QAM (quadrature amplitude modulation) modulation technique, the 100 MHz bandwidth of LTE‐advanced is able to obtain a peak data rate of 3.0 Gbps (spectral efficiency of 30 bit/s/Hz). Nokia Siemens Networks (NSN) used commercial products to demonstrate LTE‐advanced running at a data rate of 1.44 Gbps.[6] The demo aggregated five 20 MHz carriers to achieve 100 MHz bandwidth, the theoretical maximum for LTE‐advanced. Sprint and NSN achieved 2.6 Gbps speed on the TD‐LTE network as of February 5, 2014. In a test using NSN’s Flexi Multiradio 10 Base Station at the company’s Mountain View, California, facility, 120 MHz of Sprint’s 2.5 GHz TDD spectrum was aggregated to achieve what the companies claim is a TD‐LTE speed record.[7] On June 11, 2014, Nokia and SK Telecom achieved a throughput speed of 3.78 Gbps on the converged TDD and FDD LTE spectrum.[8] The trial used a combined ten spectrum frequencies allocated for both LTE variants for 200 MHz of bandwidth.

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Multi-band 29 19 23 24 26 27 28 21 22 33 35 36 37 38 7101112 2356489118 25 20 34 39 40 41 42 43 13 14 17 44

2G 4G 3G GERAN UMTS LTE TDD GSM/EDGE WCDMA

CDMA 1× EV-DO TD-SCDMA LTE FDD CDMA2000 CDMA2000

Multi-mode

Figure 1.6 Multi‐mode multi‐band, or MMMB.

The throughput speed of 3.78 Gbps enabled mobile broadband users to download a full‐length 5 GB high‐definition (HD) movie in 11 seconds. Mulitple modes and multiple bands (MMMB) are necessary to realize the 4G (IMT‐ advanced, LTE, and LTE‐advanced) capability. Figure 1.6 shows the modes and bands allocation for 2G, 3G, and 4G. There are 39 bands ranging from 700 MHz to 2.6 GHz (for North American). To realize MMMB function for 4G‐LTE, multiple antennas, power amplifiers, switches, filters, duplexers, and antennas are needed. Figure 1.7 shows a logic board of the North American iPhone 5S. The RF front end (RF FE) is located at the right‐hand side, consisting of a power amplifier (PA) modules, switches and filter modules, power amplifier‐duplexer modules, and antenna tuning modules. Refer to [9] for a modualization of RF FE, including how duplexers can be represented by two FBAR (thin‐film bulk acoustic resonator) filters. The FE performs through‐air access functionalities for wireless WAN (wide area network). PA manufacturers include Skyworks (SWKS), Avago (Broadcom), RF Micro Devices (RFMD), and TriQuint (TriQuint and RFMD are now Qorvo). Included on the logic board is an RF module that performs through‐air access functionalites for wireless LAN (wireless local area network). As a matter of fact, the RF module is a wifi/BT/radio combo marketed by Murata (Part # 339S0205).

BCM5976 RF modules for trackpad screen WAN in RF FE controller

Murata module 339S0205

Figure 1.7 A logic board of North American iPhone 5S. Source: Image courtesy of Chipworks Inc.

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Given that it takes 10 years per generation development for mobile phones, data speed from analog (voice only) 2G to digital (voice and data in 3G and 4G), to 5G (2020) (see Figure 1.5), one of the 5G goals is 10 Gbps. 5G and Internet of Things (IoT) are discussed in the next section.

1.1.3 The Future: 5G and IoT (Targeting 2020)

Goals of 5G and IoT communications as well as radio access techniques to achieve the goals are discussed. Later in this chapter, MM and MTM hardware technologies to meet the future 5G mobility demands are discussed, and in Chapter 9, more details of hardware technologies are offered. Note 5G mobility, not IoT, demands the most advanced hardware technologies. Therefore, it is focused. Users experienced data rates 0.1 to 1 Gbps;[10] peak data rates: 10 Gbps (100× of 4G data speed in high mobility conditions, i.e., 0.1 Gbps), and 1000× of 2010 data capacity (bps/Hz/area). 1000× can be obtained from the following improvements: physical bandwidth (expanded spectrum to 1,800 MHz), spectral efficiency, and small cells (spatial multiplexing, or traffic offloading densification).[11] Number of connections, 50 billion (=5 billion people × 10 connections) for IoT. By 2030, the number of global IoT connections will reach 100 billion (see Figure 1.8).[10] Note that the data rates for IoT would be much less demanding than those for mobile devices or mobile users. Most likely the IoT connections would be done through low power bluetooth, Zigbee, or 6LoWPAN. The data rates for bluetooth and Zigbee are 1 Mbps and 0.25 Mbps, respectively. They are much smaller than the gigabit per second (Gbps) requirements for mobile WAN. These took place in Ishigaki City of Okinawa Prefecture, Japan on December 11, 2012. NTT DOCOMO, INC., Tokyo Institute of Technology, succeeded in the world’s first packet transmission uplink rate of approximately 10 Gbps. In the experiment, a 400 MHz bandwidth in the 11 GHz spectrum was transmitted from a mobile station moving at approximately 9 km/h. Multiple‐input multiple‐output (MIMO) technology was used to spatially multiplex different data streams using 8 transmitting antennas and 16 receiving antennas on the same frequency. In Kista, Sweden, Ericsson using 400 MHz BW in the 15 GHz band, achieved 5 Gbps, employing a new radio interface concept and advanced MIMO technology, in July 2014.

100 Figure 1.8 IoT connection growth from 2010 to 2030.

[Unit: billion] 25

0 2010 2020 2030

Global population Global IoT connection

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Samsung used 500 MHz BW, 28 GHz band, and delivered 7.5 Gbps record using QPSK and 16 QAM, 64 element adaptive array transceiver technology. So, why is peak data rate of 10 Gbps for 5G mobility? Using data rates from wired networks as a reference, 40 Gbps (10 Gbps × 4), 100 Gbps (25 Gbps × 4, terabit ethernet, TbE is defined as >100 Gbps), are commercially available in 2016 for ethernet systems, and 200 Gbps and 400 Gbps are being developed. In 5G systems, wireless WAN and LAN are the “leaf” for the wired networks, 10 Gbps appears to be reasonable, with the core networks (ethernet based) being operated at multiple hundereds of gigabits per second (×100 Gbps). The first question is what is the physical bandwidth and at what band for the 5G systems (the stations and the mobiles)? In wifi wireless systems, 802.11 ac (<6 GHz) employs 80 MHz, 160 MHz BWs to achieve 6.77 Gbps using MU‐MIMO; 802.11ad (operating at 60 GHz), uses a BW of 7 GHz (57 to 64 GHz) to achieve 7 Gbps. From the above examples in 5G research, the bandwidth can be as wide as 400 to 600 MHz. 5G, whose bandwidth from a single allocation of 40 MHz to an aggregated band of 1,800 MHz, will be theoretically capable of peak through‐put rates that exceed 10 Gigabit per second (Gbps). The needed 1,800+ MHz bandwidth for 5G communications, is an agreed estimate by ITU and GSMA Research.[12] If indeed a BW of 1,800 MHz (still in searching and research) is required to deliver a top data speed of 10 Gbps peak, the spectral efficiency (data rate/BW, bits/second/Hz is the unit) is about 5, which is not hard to achieve. Spectral efficiency can be as high as 15 to 30 bits/sec/Hz. Spectral efficiency[2] of LTE‐Advanced is 30 bit/second/Hz, and the spectral efficiency for 5G is 10 bit/second/Hz (IMT‐2020‐5G). BWs are expensive and hard to locate. If the spectral efficiency is boosted, the required BW can be reduced; thus, the costs to the networks are lowered. The spectral efficiency in 5G can be increased by 1) Modulation techniques in PHY, such as BPSK, QPSK, and QAMs, CDMA (multi‐code), OFDM (multi‐carrier), and so on; and 2) MIMO (# of data streams). In advanced modulation, 1,024 QAM and a multi‐stream of 8 can be used in massive MIMO radio access. From the above discussions, along with narrow‐band electronics discussion in Chapter 6, many strategies can be employed to pick the most suitable bandwidth (from 20 MHz to 1,800 MHz). However, a wide bulk (i.e., in one continuous block) bandwidth is often difficult to obtain, carrier aggregation (CA) is used to reduce the need of one bulk bandwidth. For example, if 400 MHz cannot be found in a single block, two blocks of 200 MHz can be as efficient in achieving data transmission. 5G relies on dense radio networks and efficient radio delivery techniques to achieve higher data capacity. Small cells (SC) is one of the techniques to manage dense networks. Efficient delivery coincidently agrees with the refinement taken in LTE Rel 12 to improve 4G communication data speed through active antenna system (AAS) technique. AAS is to bring the active control components as close to the antenna elements as possible; thus, to obtain dynamically the necessary antenna patterns (either beamforming, or multi‐orthogonal). AAS, employed to enhance the radiation efficiency, is considered a must‐have companion technique for denser cells (i.e., small cells). In the following paragraphs, carrier aggregration (CA, grouping together separate bandwidths, a LTE‐A technique for 5G), small cells (spatial multiplexing), and active

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antenna system (AAS, through multi‐element antenna and digital beamforming) are discussed. Along with multi‐stream and advanced PHY techniques, active antenna is an effective technique to boost spectral efficiency (measured in bit/s/Hz). CA relies on aggregated bandwidth (BW in Hz) to get more digital data rate (bit/s) through the spectral effiency. Small cells increase data capacity through more off‐loading sites (measured in bit/s/Hz/km2).

1.1.3.1 Carrier Aggregation (CA) Digital data rate is equal to the raw physical BW multiplied by spectral efficiency, which is a function of theoretical PHY modulation M‐PSK and QAM, coding, and number of streams in MIMO operation. From Figure 6.2 in Chapter 6, the raw physical bandwidth determines the rise or fall times of the digital pulses; thus, the data rate: a broader bandwidth would result in a higher data rate. MIMO 4×4 and 8×8 have number of streams four, and eight, respectively. Isolation among the receiving ports impacts directly the performance of MIMO. Let’s focus here on raw physical bandwidths (BWs). From the above discussion, data rates are directly related to the raw physical bandwidths. A wider BW can be used to boost the data rate. However, a wide BW is, sometimes, just not available. Carrier aggregation can be used to relief the needs of a large bulk BW. 1.25 MHz is used in CDMA, 5 MHz in WCDMA, and 20 MHz in OFDM. In OFDM, a 64 multi‐carrier was defined thus—20 MHz/64 = 312.5 KHz—as the base tone for the carriers. LTE 3GPP Release 10 outlined use of an aggregrated BW of 100 MHz (from five of 20 MHz). In a newer transceiver (e.g., A8 by Apple), WTR1625L (a transceiver) needs WFR1620 to achieve carrier aggregation function, see Figure 5.2 in Chapter 5. Indeed, CA has been practiced. In the future, CA can be an important radio access tool to meet the 5G goals. It is estimated an agregrated 1,600 to 1,800 MHz band, according to ITU and GSMA Research,[12] but how is this huge block of BW to be allocated? According to CA, the huge block can be divided into several smaller blocks (BWs), and each smaller BW is then carried by millimeter wave CWs (continuous waves in GHz). Narrow‐band electronics would essentially decide the size of these smaller BWs. For example, assuming a narrow band process of 3% to 5%, 80 MHz can be carried using 2.44 GHz CWs, and using the same percentage, 160 MHz would require 5 GHz band (refer to Narrow Band Process and CW Carrier for Digital Signals in Chapter 6 for more details). CA can be used to relief the need of a wide bulk BW, which is useful in the 5G system design. Other issues include: 1) How long can the licensed band, if employed, can be temporarily used? 2) Antenna design to receive signals from multiple bands, and 3) Signals from different bands may be unequal; thus, require more signal processing. Small cells and AAS are discussed.

1.1.3.2 Small Cells Recognizing there is a gap between the wired (multiple 100 Gbps) and the wireless (10 gbps), more offloading sites are required. Small cells are one of designs for more efficient offloading. In 5G, small cells perform similar functions as Node B, low‐powered and yet capable, multi‐function radio access nodes that operate in licensed and unlicensed[13] spectrum and having a range of 10 meters to 1 or 2 kilometers. They are

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“small” compared to a mobile macro‐cell, which may have a range of a few tens of kilometers (from 100 meters to 35 km). With mobile operators struggling to support the growth in mobile data traffic, many are using mobile data offloading as a more efficient use of radio spectrum. It is estimated that by 2017 a total of 5 million small cells will ship annually (from research firm ARCchart; see Figure 1.9). Let there be 1,000 small cells in 1 square kilometer, each small cell will be about a square with 25 m to 35 m on one side, or a circle with a radius of 18 m. The small cell is about size between a pico‐cell and a femto‐cell.[14] 5G key characteristics: From the data shown in Figure 1.10, let’s assume 0.1 Gbps × 0.5 million (50% duty) = 50 Tbps/km2. From [10] the traffic volume density planned for 5G is tens of Tbps/km2.

Public hot spots Enterprise Residential

Small cell • Micro/metro cell (~a few 100 meters) • Pico (large building), or • Femto solution • Pico (~200 meter), or • Femto (small building, ~10 meter)

• Improve coverage and capacity • Improve in-building coverage • Improve indoor coverage Motivation • Offload users from macro-cells • Target high value business users • Increase data consumption • Manage network efficiency and QoS • Provide high quality and secured services

• M-advertising • High quality voice and video call • Surveillance Services • M-wallet • Company ID pass • Eldercare • Location based services • VPN • Multi-device sharing

Figure 1.9 Small cell solution for enterprise, public hotspot, and residential home.[14] Definitions of cells: macro‐cell: rural areas, highway; micro‐cell: a densely populated urban area; pico‐cell: a large office, a mall, or a train station; femto‐cell: home, or a small office.

4 2 Users’ data rate (Gbps) Connection density (10 /km ) 2 (0.1 to 1 Gbps) 1 (1 million connections/km ) 100

0.1 10

0.01 1

0.001 0.1 Traffic volume density End to end latency (ms) (Tbps/km2) 100 10 1 0.1 1000 100 10 1 (ms range) (Tens of Tbps/km2) 1 0.1 10 1

10 100 Peak data rates (Gbps) Mobility (km/h) (Tens of Gbps) (500+ km/h) 100 1000

Figure 1.10 5G key capabilities shown in solid line: User experienced data rate (0.1 to 1 Gbps), connection density (1 million users/km2), traffic volume density (tens of Tbps/km2), peak data rate (tens of Gbps), and end to end latency in ~1 ms;[10] for comparison, 4G capabilities are shown using the dashed line.

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Large area covered Coverage area consisting by a single cell of multiple cells

Higher-order modulation is possible High bandwidth density achieved due to since there is no interference from frequency reuse, even though average spectral neighboring areas efficiency is lower due to interference.

Figure 1.11 Data capacity improvement through denser cells.

According to METIS 2020 project, 1,000× improvement in data capacity (unit: bps/km2) can be achieved using denser cell technology. Let the physical bandwidth be 1,800 MHz for 5G, explain how it can be done. Assuming spectral efficiency of 30 bps/Hz for a macro cell, which spans 1 square kilometer. Therefore, the data capacity is 30 bps/Hz/km2. Further assuming that 1,800 MHz bandwidth small cells are used in 5G; thus, it is 18 times improvement (in 3GPP Rel 10, an aggregate of 100 MHz bandwidth was picked for 4G). It was mentioned that a macro cell is between 100 meters to 35 kilometers in size. Using a linear dimen- sion of 100 meters, there are 100 macro cells in one square kilometer. Picking 30 meters as the size for a small cell; there are 1,000 small cells in a square kilometer, which represents an improvement of approximately 10 times (Figure 1.11). Further, applying the concept of frequency reuse (possible for denser cells), there is seven times in saving in spectrum. Thus, the total improvement is 18 × 10 × 7 = 1,260 times in improvement in the per area data capacity (bps/km2). In this example, 30 bps/Hz/km2 has applied MIMO 8×8 multi‐stream technique. From this example, massive multi‐stream (massive MIMO) and dense cells (small cells) would definitely be needed for tens of Tbps/km2. That is, in the effort to increase data capacity by 1000×, small cell densification is a crucial step. Small cells have other required functionalities, discussed below. Small cells may support heterogeneous (different wireless media, such as data and voice; licensed and unlicensed bands) and coordinated networks in the future. There are many functions that small cells have to perform: TDD, FDD, and backhaul. In 3G, Node B is used between UE and RNC (radio network controller). Node B has TDD and FDD capabilities. Node B also provides mobile backhaul to core network (CN) for 3G UTRAN. CN is the backbone network (Figure 1.12). The reality is that we live in a multi‐protocol world and networks must be able to carry a wide array of ethernet, TDM, and SONET services, in other words a “fusion” of different end user services. A Node B can serve several cells, also called sectors, depending on the configuration and type of antenna. The utilization of WCDMA technology allows cells belonging to the same or different Node Bs and even controlled by different RNC to overlap and still use the same

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Figure 1.12 Node B in 3G UTRAN.

Sectors

UE Node B

Node B RNC CN

Front-haul/backhaul

frequency (in fact, the whole network can be implemented with just one frequency pair). The effect is utilized in soft handovers. TDD and FDD are important functions for small cells, because small cells will be deployed in LTE TDD and LTD FDD networks. Backhaul is needed to connect the small cells to the core network (CN), internet and other services,[15] like it occurred in Node B. Mobile operators consider this more challenging than macro‐cell backhaul because 1) small cells are typically in hard‐to‐reach near street level rather than in the clear above rooftops and 2) carrier grade connectivity must be provided at much lower cost per bit. A small‐cell backhaul solution must offer low latency of 2 ms or better. It also must support accurate frequency and (in the future) phase synchronization. In order to support TDD, FDD, and mobile backhaul, it is important to address critical network and physical synchronization issues in frequency and phase (time) domains.[16] The subject is beyond the scopes of this book.

1.1.3.3 AAS (Active Antenna System) Techniques for 5G and IoT As discussed, improved spectral efficiency (bits/sec/Hz), spatial multiplexing (multi‐ stream MIMO), and small cell off‐loading densification are crucial steps in the effort to increase data capacity by 1000×, as compared to that in 2010. AAS (active antenna system) proposed by maxim[17] is employed to enhance the radiation efficiency. They include multi‐antenna techniques, such as ABF and massive‐element MIMO, to achieve efficient power operations. Active‐integrated antennas using Ab‐IPD‐SiP (active bear- ing IPD‐SiP) and A‐IPD (antenna IPD) are discussed in Active‐Integrated Antennas in Chapter 6. DU (digital unit) consists of a large number of low power RUs through front haul. A RU is a radio unit with a multi‐element antenna, which is used to improve the efficiency of radio resources. The multi‐element antenna enables spatial multiplexing techniques: as a beamformer, or a massive MIMO, see the following figures.[18] As a beam‐former, CA and loading balancing (licensed and unlicensed) are

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Sectors Sectors

Figure 1.13 Beamformer focuses on a small cell (sector).[18]

Omni-antenna Massive-element antennna

UE#1

UE#1 UE#4 UE#2 UE#4 UE#3 UE#2 UE#3

Figure 1.14 Massive‐element antenna (right) is able to focus on individual UEs.[18]

performed (Figure 1.13). As a massive MIMO, interference coordination is performed (Figure 1.14). A low‐power RU is like a Node B, which connects wirelessly to UEs.[18] Intra‐cell capacity enhancement on MU (multi‐user)‐MIMO with massive‐element antenna. Using four orthogonal beams in spatial domain, the cell capacity is increased to a maximum of four times compared to the conventional omni‐antenna. More discussions on multi‐antenna technology can be found in Chapter 6.

1.2 Review of Key Products in Communication Networks

1.2.1 Wired Communications

Unprecedented human endeavors have made cloud computing a step closer towards the reality. A wired version of cloud computing, where gigabit ethernet (GbE)[19] is the core technology (Figure 1.15).

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Cloud computing

COAXIAL CABLE

TWISTED PAIR OR Extended life by design SHIELDED TWISTED PAIR Cat. cables/connectors Optical fiber

dc 0.001 0.01 0.1 1 10 100 1,000 Gbps

Figure 1.15 Extended copper to 10 Gbps and hand off to optical fiber thereafter. Cloud computing uses Ethernet 802.3 employing GbE [19].

At the users’ end, DSL/ADSL (asynchronized digital subscriber line)[20] is used to connect the ethernet network to the household customers. DSL/ADSL applies digital modulation technique over the traditional, twisted pair phone line, POTS (plain old telephone service).[21] POTS has been used by telephone companies to transmit voices at 56,000 bits per second (56 Kbps). However, using the innovative modulation technique, ADSL modulate frequencies from 4,000 Hz to as high as 4 MHz. This enables ADSL service and traditional POTS voice service to coexist over the same copper lines. This wired ethernet, which utilizes both copper and optical fiber technologies, is a realization of the IEEE 802.3 standards.[22] The 802.3 standards define LAN (local area network) access method using CSMA/CD (carrier sense multiple access with collision detection) media access control (MAC) protocols. The speed of the network is the highest in the backbone, in tens of gigabits/s (Gbps) up to 100 Gbps, and it gradually reduces to tens of megabits/s (Mbps) toward the client ends. In the wired network, depending on the distance, two types of cabling are used: one uses copper as the media; the other employs optic fibers. Categories 5, 5e, 6, and 6a cables,[23] which also employing twisted paired copper wires, have been used in the ethernet industry to carry the electrical signals up to 10 Gbps. In optical links, optical fibers use single mode or multimode to transmit optical signals.[24] Usually, optical fibers are the preferred cable for the long hauls. Because the high‐performance processors only employ electrical signals, the fiber optic cable has to convert its optical signals to electrical ones before they can be processed. Optical to electrical conversion modules, for example, quad small form‐factor pluggable (QSFP), become indispensable devices for the GbE backbone. It is capable of delivering 40 Gbps and 100 Gbps. Either in the core of the backbone, or at the client ends, there exist the high‐performance, high‐powered stationary computing devices, in the forms of servers (backbone areas), desktops, or notebooks (homes). They are the workforce of the wired communications network. The work force is most likely an Intel or AMD CISC‐based CPU (central processing unit). The CPU and its necessary memory and control units are usually

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packaged in the chipset format, with a powerful peripheral interface port that supports high‐performance communication protocols as the I/Os. The chipset is implemented on the motherboard of an SoB (system on a board). In the following section, we will review the key components in wired GbE networks that are identified: 1) cables (copper and optical fiber based) and OE modules, and 2) the chipset.

1.2.1.1 Cables and Connectors (RJ and Optical‐Electrical Modules) IEEE 802.3 working group has published over the years several standards relating to 10GbE, the various interconnection technologies that transmitting the ethernet frames at a digital rate of 10 gigabit per second (10 billion bits per second). Two main physical media are twisted pair copper and optical fiber. To improve the frequency performance, connectors (registered jacks for the copper twisted pairs and optical‐electrical modules for optical links) become the bottleneck. Research has been focused on the design of better connectors in both media.

1.2.1.1.1 Copper Twisted Pair Cables and RJ Connectors As discussed, twisted pair copper wires, such as DSL/ADSL, have been embedded in POTS telephone lines. Twisted pairs are a form of differential pair. In Chapter 5, it is further explained why a differential pair is twisted. In 10GbE copper cables, the same technology is applied, but a much higher speed is achieved, and better designed connectors, RJ45, is used. For example, the standard related to 1GbE over copper twisted pair cable is 802.3ab, and the physical cable is designated as 1000Base‐T; the standard related to 10GbE over copper twisted pair cable is 802.3an, and the physical cable is designated as 10GBase‐T. The popular physical media under this category are categories 5e, 6a, and 7, designated as Cat5e, Cat6a, and Cat7, respectively. Cat5e and Cat6 can be used in distances up to 55 meters, and Cat6a or Cat7, 100 meters. The physical bandwidths for each twisted pair in Category 5, Cat6, Cat6a, and Cat7 are 100 MHz, 250 MHz, 500 MHz, and 600 MHz, respectively. The data rates for Cat5, Cat6, and Cat7 are 100 Mbps, 1 Gbps, and 10 Gbps. Cat5, Cat5e, Cat6, and Cat6a all use UTP (unshielded twisted pair), Cat7 uses STP (braided/foil shielded twisted pair), the shielding material can be a foil or braided. CAT 6a cable has a larger diameter, designed to alleviate internal and external cross talk noise issues. The larger diameter cable increases the isolation of the internal twisted‐pairs as well as the neighboring, bundled external cables. The 0.35 in maximum cable diameter is 40% larger than CAT 6 (0.25 in).[25] Per the IEEE 802.3an standard, the usable bandwidth required to achieve 10 Gb/s data rates is beyond 400 MHz. Active equipment vendors achieved this high bandwidth level in part by the use of digital signaling processing (DSP) technology in active semiconductor chips to suppress internal cable channel noise, such as near end cross talk (NEXT), far end cross Talk (FEXT), and return loss, through compensation techniques. Of course, attenuation is another key design parameter. However, if the characteristic impedance is fixed, there is not much can be done, since the attenuation (or the inser- tion loss) is strictly dependent on the conductivity property of the copper, through the skin effect phenomena. At higher frequencies, the skin depth is thinner, and the loss is getting higher, so is the attenuation.

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PVC jacket Filler UTP material

PWR SDP

SDP GND

Figure 1.16 Cross section of twisted pairs and RJ45 connector for data (Cat 6), left and middle; a proprietary connector, right.

Figure 1.16 shows a registered jack connector RJ45 for data, middle, and a cross section of category cable consisting of one unshield twisted pair (UTP) and two shielded differential pair (SDP) for telephone, along with power and ground, left. Please note that all 10GBase‐T “category” cables have four un‐shielded or shielded twisted pairs (8P8C). Registered jack RJ11, used for telephone, is a 6P2C (6‐position 2‐contact) connector. Of the two contacts, one is used for transmitting, the other for receiving. RJ11 has been used in the POTS lines (Cat‐1) for many years. RJ45 is the common name for an 8P8C modu- lar connector using eight conductors, although “RJ45” was not originally specified as a registered jack with popular ethernet standards. However, the physical dimensions of the RJ45 have been standardized, and RJ45 has considered as 10GBase‐T “category” connector. Many proprietary design features are hidden in the connector for the cable, Figure 1.16, right.[26] Advanced compensation on PCB inside the connector provides improved bal- ance and crosstalk performance. The flex technology provides noise cancellation. Ethernet controller has been used to implement the network protocols and traffic controlling between two communication nodes. They can be desktops, work stations, or servers. Frequently, the controllers are fabricated in the format of a networking card. The left of Figure 1.20 shown is a receptacle for GbE ethernet through a single port network card. The networking IC, usually an FPGA or an ASIC, uses a fan to dissipate the heat. A single port 10GBase‐T adaptor can dissipate heat of as much as 10 to 20 W, depending on an FPGA[27] IC or an ASIC IC.[28]

1.2.1.1.2 Fiber Optic Cables and the Optical‐Electrical Modules The cross talk in multi‐twisted pair cables becomes a limiting factor for the copper based technology to further improve its bandwidth performance. Also, the conductor loss, for example, the skin effect due to high frequency components, limits the twisted pairs from being operated at long distances (greater than km). Optical links offer the advantages of low cross talk between the fibers and, they can be operated at long distances. Likewise, the IEEE standard related to 10GbE over optical fiber for LAN and WAN is 802.3ae, and the physical link for optical LAN is designated 10GBASE‐SR

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(short reach), –LR (long reach), and –ER (extended reach), and for optical WAN, it is designated as 10GBASE‐SW, LW, and EW. Fiber optic cabling is a technology where electrical signals are converted into optical signals, transmitted through a thin glass fiber, and re‐converted into electrical signals. Fiber optic cabling is constructed of three concentric layers: 1) the core: it is in the central region of an optical fiber, through which light is transmitted, 2) the cladding: the material in the middle layer, and 3) the protective layer: it serves to protect the core and cladding from damages. In multi‐mode fiber (MMF), many “modes” of light are allowed to propagate down the fiber optic path. The multi‐mode fiber typically has a core diameter of 50 to 100 microns. The most popular fiber for networking is the 62.5/125 (core diameter and cladding) micron multi‐mode fiber. The primary advantage of multi‐mode fiber over twisted pair cabling is that it supports longer segment lengths. Multi‐mode fiber can support segment lengths as long as 2,000 meters for 10 and 100 Mbps ethernet, and 550 meters for 1 Gbps ethernet. In single‐mode fiber (SMF), the fiber has a core diameter that is so small (9 µm) that only a single mode of light is propagated. This eliminates the critical limitation to bandwidth, modal dispersion. The critical limitation to the bandwidth of a single‐mode fiber is due to the material dispersion. Single‐mode fiber is capable of supporting much longer segment lengths than multi‐mode fiber. Using 1,310 nm light sources, segment lengths from 5,000 meters to several 10,000 meters are supported at ethernet data rates of 1 Gbps, but up to 10,000 meters only for 10 Gbps. The small form‐factor pluggable (SFP) fiber optic transceiver module supports data rates up to 10 Gbit/s. SFP+ is an enhanced version. It is a popular industry format supported by many network component vendors and manufacturers. Google and Facebook expressed interests in terabit ethernet (TbE). TbE is defined as ethernet with data rates higher than 100 Gigabit per second. The TbE technology that draws wide‐spread interests from industry is 400 Gbps, which is deliverable using the current technology.[29] Altera demonstrated a specially modified Stratix IV FPGA that handled bidirectional 100Gbps ethernet (100GbE) traffic over a pair of IC‐package‐mounted Avago MicroPOD multi‐lane optical transceivers. The optical transceivers are mounted directly to the FPGA package using a 3D package‐on‐package assembly technique, which results in an incredibly small package, as optical assemblies go. Figure 1.17 shows an optical‐electrical (OE) modules (Laser and Photo diode) in QSFP cages, capable of delivering data at 40 Gbps. QSFP is connected to 38 CKT IPASS

Serializer Optical fibers De- RX Drive amp serializer

Laser Photo QSFP diode QSFP

Figure 1.17 A core technology for GbE, the quad small form‐factor pluggable (QSFP), serializer and de‐serializer (Serdes) operations, photo‐diode (PD) converts optical signals to electrical ones.[31]

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Figure 1.18 A QSFP module, the upper figure; and the laser transmitter module.[34,35]

connector (75586) inside a QSFP cage. The 38 CKT IPASS connector is used in PCI Express ×4. Pluggable dual light pipe and heat sink are part of the QSFP cage. Optical fibers can be used for long haul communications. The signals are serialized before the EO interface.[30] The signals are carried in a serialized optic form, and at the receiver end, it is de‐serialized, Figure 1.17, the bottom illustration. During the long‐haul transmission, the cross‐talk coupling is eliminated due to the single line serialization operation. The connection of SFP+ or QFSP to a PCIe of a desktop or a server is facilitated through a network adaptor.[32] Inside the QSFP, a Vcsel module and a PD module are located on the PCB. Vcsel module is used to convert electrical signals to optical ones, and transmit them; whereas PD is used to receive optical signals, and convert them back to electrical ones.[33] A QSFP module, with the case removed (the upper photo in Figure 1.18); inside the mod‐demod modules are present, and electrical and optical signals are converted; the lower photo shows the laser transmitter module with eight optical fibers, four in and four out.

1.2.1.2 X86 Chipsets: High‐Performance, High‐Powered, Stationary Users According to von Neumann computing architecture,[36] the key components of a computing machine consists of the ALU (arithmetic logic unit), the memory, the control unit, and the I/Os. An Intel chipset is shown in Figure 1.19.[37] The chipset is

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Figure 1.19 An Intel chipset, which is implemented on a motherboard (SoB),[37] which consists of a CPU (with the heat sink removed), north bridge, and south bridge.

implemented on motherboard, about the size of a letter. The “brain” of the chipset is the Pentium 4 CPU (central processing unit). There are different memory types: cache memory, which is hidden inside the CPU, and RAM memory, which resides on the motherboard. Front side bus (FSB), between the cache and DRAM, is an internal bus. The internal bus is managed by a memory controller hub (MCH), Figure 1.20. The CPU shown is with the metal lid on, but without the heat skink. The metal lid is also called Integrated heat sink (IHS), see Figure 3.9 in Chapter 3. The socket and the CPU are shown in Figure 1.40. There are two types of graphic processors: one is internal, the other external. The internal one is called integrated graphic processor. The external one, AGP, can be added through the AGP connector. The communication between the AGP and CPU is controlled by MCH (memory controller hub, i.e., the north bridge). So, the AGP has a direct line to the computer’s system memory (DRAM), so the 3D graphic elements can be stored in DRAM, instead of the video memory. There are several external buses. IDE for hard drive (serial ATA, or sATA), USB for external flash memory, PCI or PCIe (PCI express) for external communication.[38–40] They are managed by I/O controller hub (ICH, the south bridge). Other local peripheral ports include audio channel and optical drive (for DVD), see Figure 1.19. One thing worthy of noting is that PCI/PCIe plays an important role in communicating with external devices, such as GbEs (1GbE, 10GbE). Figure 1.20 shows an additional device that is used by ICH2 to connect to GbE. This shows how a desktop computer can access GbE through PCIe (PCI express). Likewise, similar switches are designed and have been used to connect PCIe of servers or workstations to either 10GBASE –T, ‐SR –LR, and –ER. Main memory is made of volatile DRAMs packaged on both sides of a DIMM (dual in‐line memory module) strip, see Figure 1.46 (later in the chapter). GPU is where

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Figure 1.20 A desktop computer (x86 based) connects to GbE using CPU PCIe; MCH is the north bridge, ICH2 is the south bridge shown in Figure 1.19. GPU MCH Main memory

USB 3.0 sATA ICH2 Local Mobile I/Os docking

Switch GbE PCI

PCI Add express ins PCI/PCIe

Figure 1.21 A GPU card, where a huge heat sink is attated to the GPU die.

intensive computing takes place; thus, it generates a lot of heat. The GPU IC, like the CPU, the north bridge, or the south bridge, is packaged with a heat sink. The difference is the GPU card is insertable board, whereas CPU, the north bridge, or the south bridge are located on the motherboard (see Figure 1.21). The peripheral I/Os are one of key features in a von Neumann computing machine. The locations of the I/O ports define the border of the computing machine. So, it is safe to say the chipset is defined by the mother board, since all the I/Os are mechanically attached to the board. Other wired communication interfaces, such as sATA and USB can be consulted in.[41][42]

1.2.2 Wireless Communications

There are basically two fundamental wireless services: one being based on wireless LAN technology (WLAN or wifi); the other based on cellular technology (wireless WAN). In the first service, the wireless users, mobile or not, use access points (or called

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VLR CN

PSTN GERAN MSC GMSC Landline (POTS) (WAN)

AuC BRI EIR HLR GR

GG (WAN) SGSN SN PDN WWW UTRAN

Figure 1.22 Routers provide connection between CS (landline for voices) and PS (WWW for data).

“hot spots”) to transmit and receive data. Hot spot in a household (home office) is usually provided by DSL or ADSL on POTS. As mentioned, the DSL/ ADSL service and traditional voice service to coexist over the same POTS twisted pair copper lines. Through the access points, the wireless internet (or wifi, wireless LAN) services (data and voice) are delivered. One of the services may be voice over IP (VoIP) that provides telephone talks through the internet. Wifi realizes IEEE 802.11 standards, where CSMA/ CA (collision avoidance) protocols are exercised. Public hot spots (airports, schools, libraries, or small business) may go through different avenues: cables, or directly from ethernet.[43] In Figure 1.22, a merger of circuit switched and packet switched networks is illustrated. GERAN and UTRAN are explained in Figure 1.4. POTS (plain old telephone Service) is the old telephone lines using copper. Originally designed for carrying only voice signals, POTS has been upgraded to carry voice and data using modern modem technology (i.e., analog voice and digital data by DSL/ADSL co‐exist). Ideally, ADSL is able to provide uploading speed of 3.5 Mbps and downloading speed of 24 Mbps. PSTN (public switched telephone network), is the telecomm carrier, and consists of telephone lines (POTS), fiber‐optic cables, microwave transmission links, cellular networks, communications satellites, and undersea cables. PSTN is almost entirely digital in its core. Integrated services digital network (ISDN) is a set of communications protocols for simultaneous digital transmission of voice, video, data, and other network service over the traditional circuits of PSTN. Since the ethernet is packet switched and ISDN/PSTN over POTS is circuit switched.[44] In between, it is necessary to have interfaces that buffers the data and directs the traffic, such as, basic rate interface (BRI) and primary rate interface (PRI).[45] In the second service, cellular technology, that is, base stations, are installed to deliver voice service. The hand‐off between the cellular domains is handled seamlessly, thus, providing the true user mobility. Recently, commercial smartphone makers have started to offer data and cloud storage services in their mobile devices (2.5G, 3G, and 4G). In [46], it was explained that cellular‐based 3G phone voice and data can be transported through the fixed media such as ISDN/PSTN, and eventually through GbE to reach a remotely located server. Gateway mobile switch center (GMSC) provides gateway to

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ISDN/PSTN. That is, voices from GSM mobile users can be delivered through a wired (fixed) network, Figure 1.4. Note that in the future UMTS development, the GSM EDGE radio access network GERAN is replaced by UTRAN (universal terrestrial radio access network), where Node B is the cell unit.[47] This virtually extends the GbE cloud computing into wireless domains, thus forming a huge connected world web consisting of mobile users (Internet of People, IoP). In the near future, the cloud computing network would add wireless sensing nodes at its leaf ends, forming the so‐called IoT.

1.2.2.1 ARM Architecture ARM is the abbreviation of “advanced RISC machine.” ARM7 uses von Neumann architecture, ARM9 uses Harvard architecture.[48] It is low power and tiny. ARM has 8, 16, 32, and 64‐bit systems. Using a RISC‐based approach to computer design, ARM processors require significantly fewer transistors than ×86 CISC processors, which are typically found in a traditional desktop computers or servers. The benefits of this approach are lower costs, less heat, and less power usage, traits that are desirable for use in light, portable, battery‐powered devices such as smartphones and tablet computers. ARM‐based processors include Snapdragon from Qualcomm, Exynos from Samasung, Tegra from nVidia, Xscale from Intel/Marvell, OMAP from Texas Instruments, as well as ARM’s Cortex series and AppleApple’s A-series (e.g., A7, A8) processors used in its iPhone and iPad products. Recently, Intel joins the mobility market by adding AtomTM business.[49] ARM‐based processor is usually fabricated with its peripheral I/Os on a single chip, called system on a chip, or SoC. The architecture of an ARM processor is shown in Figure 1.23. AMBA (advanced microcontroller bus architecture) used in ARM is an open standard bus. It has two varieties: AMBA high‐performance bus (AHB) and AMBA peripherals

Figure 1.23 ARM architecture: ARM core ARM processor, buses, and the peripheral I/Os on an ARM single chip. processor AHB Mem. controller Perip. bridge PIO System controller APB Ethern CAN MAC USB USART PWM PIO PIO SPI Sys. ser. 2-wire ctrl interf..

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bus (APB). AHB is communicating with memories through memory controller; APB is connecting to “simple” peripheral I/Os (PIO in Figure 1.23) after the peripheral bridge. The bus structure shown in Figure 1.23 is much simpler than the north and south bridges shown in Figures 1.19 and 1.20. Note that the multitude of peripheral I/Os on the architectural functional blocks of an ARM single chip. On TI OMAP4530, also an ARM‐based single chip, there are many peripheral I/Os: USART, GPIP, I2C/SPI.[50] These I/Os are used to connected many peripheral devices, such as, the transceiver IC, the base band IC, the wifi/bluetooth connectivity RF modules, Gyro and accelerometer, touch screen, and the controller. Another feature that is quite different from ×86, Figure 1.20 is that GPU in ARM architecture is located inside the processor. That is, it is a form of integrated graphics solution. Other important common feature is that the ARM‐based single chips are mostly for mobile users, due to their lower power consumption, either standard, or customized. The power consumption of an ARM‐based single chip is usually rated at less than 1 W. However, in a smartphone (an iPhone or an Android phone), the most power‐hungry device may not be the ARM‐based application processor; rather, it could be the PA module for 4G RF transceiver (Qualcomm’s RTR8600), or the display processor. Each one may exceed 2 watts (33 dBm) on average.[51]

1.2.2.2 Wireless WAN Let’s now turn our attention to the main devices that achieve personal mobility: the mobile devices, or cellular phones. In the following sections, we will introduce the architecture of a cellular phone, which breaks up the main functions into a few blocks. And, we will discuss the components used in each block. Recently, 4G LTE becomes available in the United States. LTE is a standard for wireless communication of high‐speed data for mobile phones and data terminals. It is based on the GSM/EDGE and UMTS/HSPA network technologies. It employs a different radio interface along with core network improvements to increase the capacity and speed. LTE is the natural upgrade path for both carriers with GSM/UMTS networks and for CDMA. Ideally, 4G networks can achieve 100 Mbits/s (Mbps) for downlink, 50Mbps for uplink. Using the tear‐down data,[52] architecture functional block for iPhone 5 as a 4G mobile device, can be illustrated in Figure P.3, in the preface. Teardown photo of a newer iPhone can be found in Figure 5.2 in Chapter 5. There are main blocks: the main processor and its memories, RF front end for cellular communications, the connectivity RF (wifi/ Bluetooth/radio), and user‐interface ICs. The single largest component, the battery, is not shown. The importance of battery is probably proportional to its size, since it provides the power for roaming, and its capacity is directly related to the talk time.

1.2.2.2.1 Application Processor (AP) and its Main Mobile Memory Apple’s A‐Series AP Using Apple’s iPhone 5 as an example, the application is A6 (shown in Figure 1.41), which was fabricated with dual ARM core and triple‐core GPU, in a SoC realization. Layers of memories to support these processors include cache, main memory, and

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external NAND flash memory. The cache memories, L1 and L2, are on chip, the main memory (1 GB LPDDR) is integrated with A6 application processor using stacked package on package, or PoP technology. On iPhone 5’s main logic board, choices of 16 GB or 32 GB NAND flash memory are provided and are integrated on the other side of the board. It is interesting to note that in an ×86 CPU, the graphic processor was originally integrated with the CPU, but, later when GPU becomes dominant (because of the demands in graphical presentations on mobiles), it is provided externally to the ×86 CPU through an individual GPU insertable board. The GPU is managed by MCH on ×86 boards.

Mobile Memory LPDDR JEDEC defines standards on LPDDR and wide I/O, such as LPDDR2 (JESD209‐2), LPDDR3 (JESD209‐3C), LPDDR4 (JESD209‐4), and wide I/O (JESD229), and wide I/O 2 (JESD229‐2) memory. Cadence has published models for LPDDR5. As illustrated in von Neumann architecture Figure P.7, (see the preface), memory, which works closely with the ARM processor, is an important unit in mobile devices. Because of different power sources used in ×86 and ARM SoC processors, memories have to be designed differently, too. That is, low power series, such as LPDDR (low power DDR, i.e., mobile DDR) are used for mobile devices. As mentioned, the application processor (e.g., A7, A8) and its main mobile memory are packaged in PoP format. One GB LPDDR3 has been used in iPhone 5S (A7) and iPhone 6 (A8). Two GB LPDDR4 made by Samsung were used in iPhones 6S (dual core, A9) and iPhone SE. JEDEC defines standards for LPDDR and wide I/O mobile memories.[53] Refer to Chapters 3 and 5 for more discussions on mobile memories.

1.2.2.2.2 RF Front End (FE) An RF front‐end consists of a main transceiver, other RF‐passives systems that perform functionalities such as power amplification, switching, filtering, or duplexing, and antennas. Refer to Chapter 6 for the design of RF functional components (see Figure 1.24).

Figure 1.24 2G/3G modem and the front Antenna end (transceiver, switches, filters, and switching PAs).[9][54] module (ASM) Dual-band GSM

UMTS TR UMTS (GSM-FDD) duplexer

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MMMB MMMB TR MMMB modem PA/switch

AD Mod- demod DA

Figure 1.25 MSM, left, and RF FE, right, consisting of a transceiver/UE category 3 modem and RF circuits.

Inside an iPhone 5, the main transceiver, a Qualcomm RTR8600 multi‐band/mode RF transceiver, is paired with the base band (BB) processor, a Qualcomm MDM9615M LTE mode to fulfill the critical RF front‐end and modem functions. On the iPhone 5’s logic board, these two devices are paired next to each other. The RTR8600 has the following two models: one is GSM model consisting of UMTS/ HSPA+/DC‐HSDPA (850, 900, 1,900, 2,100 MHz); GSM/EDGE (850, 900, 1,800, 1,900 MHz); LTE (Bands 1, 3, 5); the other is CDMA model consisting of CDMA EV‐DO Rev. A and Rev. B (800, 1,900, 2,100 MHz); UMTS/HSPA+/DC‐HSDPA (850, 900, 1,900, 2,100 MHz); GSM/EDGE (850, 900, 1,800, 1,900 MHz); LTE (Bands 1, 3, 5, 13, 25). The receiver sensitivity for 4G LTE downlink requires at least ‐106 dBm. In Qualcomm’s RF360TM, UE category 4 MDM9625 modem is connected to the ARM processor (MSM in Figure 1.25). Also connected to the ARM processor is the RF front end (FE), which consists of a transceiver WTR1625L, UE category 3 WFR1620 modem, and RF circuits, such as PA, switch, antenna matching tuner, and envelop power tracker. The transceiver, RFIC WTR1625L from Qualcomm was packaged in WL‐CSP. According to [55] Qualcomm’s transceivers have gradually increased the number of raido access modes and frequency bands over the years, represented by RTR 8600, WTR 1605 L, and WTR 1625 L. RTR8600 represents a 3G/4G transceiver, where it packed UMTS/GSM/CDMA/LTE and GPS and GLONASS in global navigation satel- lite system (GNSS) support. It was fabricated using 65 nm RF CMOS technology, and was packaged in a 48 mm2 plastic (symbolized by the letter “R” in RTR) BGA package. Meantime, WTR1605L and WTR1625L are other 4G/5G Qualcomm transceivers (“L” represents LTE, or LTE‐A); it added TD‐SCDMA in radio access and Beidou in GNSS support. They are realized using 65 nm RF CMOS, and are packaged in a 25 mm2 WL‐ CSP using a WLP technology (“W” in WTR represents WLP). 3GPP Release 8 defines five LTE User Equipment (UE) categories, shown in Table 1.2,[56] depending on maximum peak data rate and MIMO capabilities support.[57] Physical bandwidths of 20 MHz, or combination of multiple of 20 MHz (e.g., CA, 60 MHz = 20 MHz +20 MHz +20 MHz) are used. In March 2008, the International Telecommunications Union‐Radio communications sector (ITU‐R) specified a set of requirements for 4G standards, named the International Mobile Telecommunications Advanced (IMT‐Advanced) specification. Continuing 3G efforts, the working body

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Table 1.2 UE category for mobile modem.[56]

UE category Maximum L1 DL (Mbps) Maximum L1 UL (Mbps) #of MIMO streams

Category 1 10.296 5.16 1 Category 2 51.024 25.456 2 Category 3 102.048 51.024 2 Category 4 150.752 51.024 2 Category 5 299.552 75.376 4

3GPP released development results on LTE (evolved‐UTRA), referred to as 4G. With 3GPP Release 10, which is referred to as LTE‐advanced, three new categories (Categories, 6, 7, and 8) have been introduced, and two more (Categories 9 and 10) with 3GPP Release 11. With 3GPP Release 12, six more UE categories (Categories 0, 11‐15) have been introduced. As a reference, UE Category 9 and 10 have 452.2 Mbit/s downlink (DL) speed. In November 2014, Qualcomm announced its fifth‐generation LTE modem, a UE Category 10 chip with global carrier aggregation, and second‐generation RF360TM[58] envelope tracker (ET).[59] The Gobi 9×45 modem is based on 20‐nm technology. The main new features, as compared to 9×35, is downlink increased from 300 to 450 Mbit/s, and uplink is the first major upload increase to 100 Mbit/s. This is the first chip that can fully utilize all 60 MHz in aggregated bandwidth in downlink and 40 MHz in uplink. RF FE RF360TM is Qualcomm’s solution to RF FE. In RF360TM,[58] transceiver RFIC and global MMMB (multi‐mode, multi‐band) management chip are packaged in a PoP, PA, and switch are packaged in a QFE 23×× module, antenna matching tuner is packaged in a QFE15×× module, Envelop power tracker is an IC. It appears that ASE’s SiP module shown in Figure 9.11 in Chapter 9 is an ideal packaging format for RF‐passives systems such as PA, switches/filters, baluns, duplexers, and antenna‐ tuning circuits. In summary, RF modules are used for these RF‐passives integrated systems. RF modules can be represented in Figure 4.20 and Figure 4.22 in Chapter 4, and Figure 9.7 in Chapter 9 as well as Figure 1.7 and Figure 1.48, Figures 4.20 and 4.22 in Chapter 4, and Figure 9.11 in Chapter 9. Features of these RF modules include one organic board (MLOs) and two discrete components are surface mounted on the organic boards. In the future, RF SiP (RF modules that include IPDs and glass panels) represented by Ga Tech’s conceptual drawings of IPAC shown in Figures 9.12 and 9.13 in Chapter 9 are to be used to improve the performance of RF FEs at manageable costs.

1.2.2.2.3 Antennas Let’s now describe the important hardware for wireless communications and mobility. Obviously, the first component that comes to our mind is antenna. For example, antennas at the base station for the cellular phone technology, antenna for a hot spot, and many hidden antennas on a phone. The antennas for base station and hot spot are rather easy to identify. For example, shown in Figures 1.26a and 1.26b are antenna for a cellular base station and an indoor router for wifi.

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Base-station antennas Router antennas

Base station tower

Figure 1.26 Antennas at a base‐station (a), left and antennas of an indoor wifi router (b), right.

The total RF power that can be transmitted from each antenna at a cell depends on the number of radio channels that have been authorized. Typically, a maximum of 16 or 19 channels is used. For a typical cell, each sector has three transmitting antennas, and each could be connected to 16 or up to 19 transmitters. All the sector antennas should have a directional radiation pattern for energy efficiency. Although the FCC permits an effective radiated power (ERP) of up to 500 watts per channel, the majority of cellular base stations in urban areas operate an ERP of 100 watts per channel or less. An ERP of 100 watts corresponds to an actual radiated power of 5 to 10 watts, depending on the type of antenna (i.e., the efficiency) used.[60] Given the sensitivity of the receiving cellular phone, the ERP determines the allowed size of a cell, or vice versa. Sometimes, multi‐antenna is used in a communication system, such as the one shown in Figure 1.27. The multi‐antenna is used for diversity. The purpose of antenna diversity is to pick the signal from the antenna with better reception, or to combine the both signals to obtain signal of a better signal to noise ratio Secondary cellular antenna (SNR). The diversity is employed to reduce the ill effects from multipath signal propagation, and it is popular in 802.11 wireless LAN access points. WiFi/BT In the old day, antenna protrusion on a phone can antenna clearly be seen, and identified. The antennas on a modern mobile device are integrated inside or on the case, and they are cannot be identified from the outside. Figure 1.27 shows the antennas for iPhone 4S. There are primary (bottom) and secondary (top) antennas for cellular wireless communications.[61] The primary one is on the bottom, and the second- Primary cellular antenna ary is on the top. The primary one is made of a metal • = Antenna feed point band and flexible printed circuit (FPC). The second- Figure 1.27 iPhone 4S ary one is made of only metal band. The operating primary, secondary, and wifi frequency bands are 850 and 1900 MHz. The second- /bluetooth antennas. ary cellular antenna was added for Rx diversity.

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Also shown in Figure 1.27 is the location of the feed point for the wifi/bluetooth antenna. This antenna is operating at 2.44 GHz.

1.2.2.3 Connectivity RF Bluetooth is a wireless technology standard for exchanging data over short distances (using short‐wavelength radio transmissions in the ISM band from 2,400 to 2,480 MHz) from fixed and mobile devices, creating personal area networks (PANs) with high levels of security. Created by telecom vendor Ericsson in 1994, it was originally con- ceived as a wireless alternative to RS‐232 data cables. But, later, it became an IEEE standard, i.e., IEEE 802.15.1. Overcoming problems of synchronization, it is able to connect several devices. The receiving sensitivity for Bluetooth is ‐70 dBm, or better.[62] Wifi is a popular technology that allows an electronic device to connect wirelessly to ethernet network that provide internet service. The term “wifi” is used in general English as a synonym for “WLAN,” or wireless LAN, which is based on IEEE 802.11 standards. In a household, the internet service is available through the access points (or hot spots) of DSL/ADSL. Such an access point has a range of about 10 to 20 meters indoors. The receiving sensitivity for wifi is ‐76 dBm (802.11 g), and ‐66 dBm (802.11n). Both wiFi and bluetooth are using 2.45 GHz ISM bands. The 802.11a wiFi uses an additional 5.7 GHz band. They are now often available on a PC, a video game console, a digital audio player a smartphone, or a tablet. Figure 1.28 shows a Skywork wifi transceiver next to its MAC/BB processor. Usually these two components, transceiver and MAC/BB are integrated on an RF module. Touch screen is the user interface method to replace a mouse’s point and click function. For a mobile user, it is inconvenient to carry a mouse and a pad. The functionality was first commercialized by Apple, and it has become so popular that the functionality is available in almost all the new phones and tablets. Apple went with a multi‐chip solution to handle touch screen function in their iPhone 5 and

Figure 1.28 A wifi transceiver next to MAC/BB. Dual front-end PA/switch module

2.4G Rx

WiFi/BT LNA 2.4G Tx

PA processor 5G Tx Single-chip MAC/BB PA 5G Rx LNA

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iPad products: one from Texas Instruments (TI27C245I), and the other from Broadcom (BCM5976). The accelerometer is used to sense the gravity of the earth, a sensor that has been present since the original iPhone by Apple. The accelerometer detects the device’s acceleration, shake, vibration shock, or a fall by detecting linear acceleration along one of three axes (X, Y, and Z). The accelerometer IC is able to automatically turn the graphical display accordingly when the user changes the orientation of the screen of a phone or a tablet. The change between the portrait and landscape depends on the contents of the display. For example, reading news or e‐book, it is customary to use portrait, and watching a movie, it is usually to use landscape. Inside an iPhone 5, an ultra low‐ power, high‐performance, three‐axis linear accelerometer, LIS331DLH (2233/DSH/ GFGHA) from STMicroelectronics, was used. The gyroscope is used to sense the planarity of a phone or a tablet. Apple’s iPhone 4 introduced a gyroscopic sensor that detects a three‐axis angular acceleration around the X, Y, and Z axes, enabling precise calculation of yaw, pitch, and roll. The gyroscope complements the accelerometer. The combined data from the accelerometer and the gyroscope provides detailed and precise information about the device’s six‐axis movement in space. The three axes of the gyroscope combined with the three axes of the accelerometer enable the device to recognize approximately how far, fast, and in which direction it has moved in space.[63] Inside the iPhone 5, a low‐power three‐axis gyroscope L3G4200D from STMicroelectronics, is installed.

1.2.2.4 Batteries Battery is probably the single largest item in the phone construction, and proportionally the single most important component in a mobile or portable device. For a mobile device, it provides the necessary power for all the devices inside the phone. The battery life after each full recharging determines the talk time or duration of usage when roaming. A battery’s capacity is usually specified in milli‐Ampere‐hour (or mAh). After each re‐charging, the battery in a mobile device is capable of delivering 1500 to 3000 mAh (in 2012, the Droid RAZR Maxx was equipped with a 3300 mAh battery). The battery delivers the power at a rating of 3.7 DC volts. Figure 1.29 shows a Li‐ion battery for Sony Xperia S with 1,700 mAh, equivalent to 6.3 Wh (watt‐hour) capacity. Lithium‐ion batteries are common in consumer electronics. They are one of the most Figure 1.29 Li‐ion battery (bound by popular types of rechargeable battery for porta- the white border, 1‐3/4” by 2‐1/2”) in a ble electronics, with one of the best energy den- smartphone (2‐1/4” by 4”) with 1,300 sities, no memory effect, and only a slow loss of mAh, 4.81 Whr capacity. charge when not in use. Memory effect of a

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battery refers to a phenomenon observed on NiCd batteries that gradually lose their maximum energy capacity if they are repeatedly recharged and being used only partially. All batteries are limited by a finite number of charging “cycles.” Recently, there is controversy related to the sealed batteries. Manufacturers argued that customers want to have a thinner phone, and one way to achieve that is to seal the phone. Aesthetics (ID, industrial design) are another obvious reason to go that route, with designers opting for a fluid, unibody motif, since sealed phone body is a beautifully crafted device “… created from a single piece of polycarbonate with precision machined details.”[64] This ID design philosophy is in a direct conflict with customers’ desire of extended use of their purchased phones; that is, when the sealed battery fails to function because of the limited charging cycles, and a replacement is needed. Battery deserves in‐depth design consideration and discussion;[65] however, it is not the main focus of this book.

1.3 MM and MTM, an Intro to Hardware Technology

1.3.1 Moore’s Law

It was observed that the number of transistors on integrated circuits for microproces- sors doubled approximately every two years (see Figure 1.30). The number of transistors is reaching 3 billion, and note that multi‐core architecture has been commonly applied since 2010. The observed rule is often referred to as Moore’s law, named after Intel co‐founder, Gordon E. Moore, who described the trend in his 1965 paper.[66] The trend has continued for almost half a century (paper was written in 1965). The observation has a powerful impact: the industry has a simple metric to drive the technology advancement. For a while, physical channel length becomes synonymous with semiconductor industry’s mission statement. In order to meet the Moore’s law, companies are delivering transistors with smaller gate oxide thickness and channel length that simultaneously reduce the voltage (thus, the power) required for reliable

Transistors per chip Delayed products 10B @ 45 nm/32 nm 2006 1B Moore’s law 2009 0.1B Transistors/chip doubled every 2 years 10M Pentium III Pentium II Pentium 1M 486 386 0.1M

10K

1971 1980 1990 2000 2010 2018

Figure 1.30 Moore’s law: the transistor counts double every two years.

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and fast logic operations. For relatively matured products, the reduced feature dimensions mean the die per wafer (DPW) is increased, the cost is lowered; thus, higher margins for the companies. Die shrink for a product has been a common practice in many semiconductor companies to drive up the profits. However, the 2010 update to the ITRS (International Technology Roadmap for Semiconductors) marked a slowing growth starting 2013 (note the mission of a roadmap is to predicts future technology trends). It stated that the transistor counts were to double only every three years after roughly 2013. There are several obstacles to the trend. Just to name a few: physical limitations and the cost of manufacturing smaller devices at the same yield level of the previous technology. When the shrinking dimensions are approaching molecular and atomic levels, the voltage reduction cannot be continued, because it causes dielectric breakdown and high current drain during the operation and standby. Photolithography has been used to drive down the physical channel length. Light waves are used in photolithography. They represent another obstacle to smaller feature dimensions.

1.3.1.1 Immersion Technique Since 2005, the light wavelength used in lithography has stopped at 193 nm. This light wavelength has been used to deliver channel lengths of 65 nm, 45 nm, and 32 nm using various light enhancing techniques. For example, immersion with fluids of higher index of refraction was used to deliver 45‐nm channel length (2011);[67] double patterning (DP) was used to deliver 32‐nm technology (2012) for MPU/ASIC and DRAM. A year earlier (2011), the same lithography technique has delivered 22‐nm half pitch (almost equivalent to Technology Node, defined later) for NAND Flash. The 22‐nm half pitch may be the first time the gate length (Lgate) is not necessarily smaller than the technology node designation. For example, a 30‐nm gate length would be typical for the 22‐nm node (see Table 1.3). As a matter of fact, gate length became less important as a metric to represent the progress of more Moore technology around 2011. Table 1.3 shows the lithography techniques that are currently used and planned for manufacturing MPU/ASIC‐DRAM and flash circuits.[67] Due to its relatively simple structure and high demand for higher capacity, flash memory (NAND, a non‐volatile) applies the most aggressively scaled lithography technology among electronic devices. Therefore, flash memory is usually first employed when there is a new advancement in photolithography. It is generally believed that EUV (extreme ultra‐violet, wavelength 13.5 nm) may be needed for the feature size going down to 22 nm for MPU/DRAM to 16 nm for NAND flash. EUV is a very expensive technology. At the same time, 193‐nm multiple patterning (MP) was being investigated. Other concern on EUV is that the throughput for the technology is too low. But, TSMC and ASML were able to improve the throughput significantly in 2014, about 500 wafers daily.[68] It was announced that TSMC would adopt EUV for their 5‐nm chip volume production, see Section 9.3.1 New from Wafer Foundries in Chapter 9. On March 23, 2012, with the release of the Ivy Bridge chip (22 nm), Intel’s Senior Fellow Mark Bohr stated that the company will be able to extend its current immersion process to the 14‐nm and even 10‐nm chips before EUV would be needed. He did not mention specific techniques that will be utilized. Intel move from its current 22‐nm

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Table 1.3 Lithography techniques used for MPU/ASIC and DRAM and flash.[67] DP: dual patterning.

MPU/ASIC and DRAM Flash

2011 45 nm 193 nm + Immersion 22 nm 193 nm + DP 2012 32 nm 193 nm + DP 2013 2014 16 nm EUV, 193 nm + MP, or Imprint 2015 22 nm EUV or 193 nm + MP 2016 2017 2018 16 nm 2019 11 nm MEB 2020 2021 11 nm

process to the 14‐nm process by the end of 2013, and hopes to use its manufacturing advantage in Atom low power products to stay ahead of ARM‐based chip makers. ARM‐based chips are for smartphones and tablets, the so‐called SoC for mobile applications. In 2014, MEB (multiple E‐beam) lithography was investigated for 10‐nm feature size. E‐beam is a technology that uses focused beam of electrons to “scribe” (i.e., direct write) on an electron‐sensitive film called a resist. The resist can later be developed, so the features (or circuitry) can be obtained. Depending on the power of the electron beams, the mask‐less, direct‐write technology can deliver resolution of sub‐10 nm. Due to the direct write approach, MEB is a very slow process.

1.3.1.2 HKMG, Gate Last, and TriGate (FinFET) IBM and Intel had different approaches to more Moore (MM). Gate first was employed by IBM who felt the end of Moore’s Law was at somewhere around the 65‐nm node using plain 193‐nm photolithography. Intel knew the adoption of gate first would stop scaling progress at 32 nm. Intel secretly worked on gate last,[69] and brought the technology to manufacturing. In May 2011, Intel announced that the 22‐nm node would not only be a shrink, but also that it would be the first implementation of TriGate high‐k metal‐gate (HKMG) transistors.[70] Metal gate choices include Ta/Mo, TiN, and Mo.[71] The process of making HKMG TriGate transistors is shown in Figures 1.1 and 1.2. TriGate can be built on SOI silicon substrate. SOI enhances the device performance by de‐coupling the lossy silicon substrate from the device. HKMG (high k metal gate, k refers to the dielectric constant) technology is employed to achieve better device performance, for example, transistor stability (during the subsequent high temperature processes) and reduced device leakages than those would be possible with a traditional silicon dioxide/polysilicon gate.

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Table 1.4 Intel advanced transistor configurations at reducing feature sizes; *HKMG: high K metal gate.

Year 2003 2005 2007 2009 2011

Tech [nm] 90 65 45 32 22 Transistors Invented SiGe 2nd Gen. SiGe Gate Last, 2nd Gen. Gate TriGate Strained Silicon Strained Silicon HKMG* Last, HKMG

Advanced device structures and materials were developed when the feature sizes are shrinking. Table 1.4 shows Intel’s advanced transistor designs at reduced feature sizes.[72][73] High‐K metal gate was used in 45 nm and for subsequently smaller features. At 22 nm, the 3D transistors (multigate, such as trigate) are used. Different TriGates by Intel are shown in Table 1.5 and Figure 1.31. Table 1.5 shows different transistor types: high speed logic, low power logic, and high voltage. Each type has its unique design features. In Figure 1.31, it is noticeable that transistors for high voltage have thicker high‐k dielectric layer, and the gates are much wider.[73] One important point of Table 1.5 is that the gate length for 22‐nm technology node was 30 nm and greater. As mentioned, gate length is obviously losing its status in representing the progress made in MM technology around 2011. Note that in Figure 1.31, the gate of the gate last covers the left, top, and right sides of the drain‐source channel. Because of the fin structure of the drain‐source channel, it is also called FinFET (the term was coined by Professor Chenming Hu of UC–Berkeley and CTO of TSMC). Figure 1.32 shows a conventional transistor structure. Using this structure, the gate length (or the width, as appeared in many textbooks), which is the smallest feature of the transistor device, was adequate to represent the progress of Moore’s Law. However, approaching the millennium, a more representative metric, half pitch, emerged as the technology node, which, by intent, is closely associated with the progress of Moore’s Law, shown in Table 1.6. Gate length is defined in Figure 1.32, pitch and half pitch are defined in Figures 1.32 and 1.33. In [67], the half pitch of M1 for MPU/ASIC, half pitch of contacted M1 for DRAM, and half pitch of uncontacted poly for flash are used for equivalent scaling (may be interpreted as technology node) (see Figure 1.33). Using half pitch as the technology node seemed to hold the water until 2004. ITRS abandoned the use of the term, technology node, in 2005, but its use continued by some. In 2009, ITRS discontinued the practice of refraining from using the term “technology node.”[75] Please note the double negative of ITRS’s action. At the time, industry feels it is necessary to have a specific term to closely be associated with the progress of Moore’s Law. Taking into consideration the effects of process techniques, such as, gate strain in the channel, high‐K metal gate, and multi‐gate (TriGate or FinFET), the simple metric (channel length) has to be replaced by “equivalent scaling.”[67] The term is technology node, thanks to Intel and ITRS. Indeed, the term technology node comes back, and it is defined be a set of parameters. Intel changed the world in 2011 (technology node 22 nm) by introducing HKMG and gate last approaches; as a consequence, TriGate (or FinFET) became their products.

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Table 1.5 Transistor types for 22 nm technology node.[73]

Transistor type High speed logic Low power logic High voltage

Options High Performance Standard Perf./ Low Power (LP) Ultra Low Power 1.8 V 3.3 V (HP) Power (SP) (ULP) Vdd (Volt) 0.75 / 1 0.75 / 1 0.75 / 1 0.75/1.2 1.5/1.8/3.3 3.3 / >5 Gate Pitch (nm) 90 90 90 108 min. 180 min. 450 Lgate (nm) 30 34 34 40 min. 80 min. 280 N/PMOS Idsat/loff 1.08/0.91 @0.75 V, 0.71 / 0.59 @0.75 V, 0.41 / 0.37 @0.75 V, 0.35 / 0.33 @0.75 V, 0.92 / 0.8 @1.8V, 1.0 / 0.85 @3.3 V, (mA/um) 100 nA/um 1 nA/um 30 pA/um 15 pA/um 10 pA/um 10 pA/um 3/12/2018 6:48:05 PM 36 3D IC and RF SiPs: Advanced Stacking and Planar Solutions for 5G Mobility

Gate Gates

Logic -High speed (HP/SP) -Low power (LP/ULP)

High voltage

Figure 1.31 TriGate configurations by Intel; the ridges hugged by the gate are drain‐source: (into the paper).[73]

Pitch (S-D) Source S Gate contact G contact

Lgate Drain D contact Viewing angle

Source Lgate contact

Figure 1.32 A planar bulk Si MOSFET[74] and definition of pitch (S‐D) and gate length.

Table 1.6 Gate length can be used adequately related to the progress in MM, until millennium.[75]

Pitch in [nm]

Year Node ½ pitch Gate length

2009 32 52 29 2007 45 68 38 2005 65 90 32 2004 90 90 37 2003 100 100 45 2001 130 150 65 1999 180 230 140 1997 250 250 200 1995 350 350 350 1992 500 500 500

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Figure 1.33 Metal 1 pitch (source Pitch (S-D) drain) and half pitch definitions, the figure is obtained from Figure 1.32 by the viewing angle.[75] Half pitch Drain Source contact contact

Gate

Drain Source Channel

In addition to the original gate length (now called channel length), other features associated with the TriGate construction, are shown in Figure 1.34: the pitch, the fin pitch, (Pfin) the fin width, and so on. Thus, to describe the evolution of device making from technology to technology, it is necessary to have a new term that is acceptable to everyone, and also backward compatible to the past history of Moore’s law. Intel, being the first major player who implemented the gate last,[69] TriGate structure, had a strict and disciplined timeline, for example, Table 1.4. It was a two‐year technology roadmap, where technology nodes of 90 nm (2003), 65 nm (2005), 45 nm (2007), 32 nm (2009), and 22 nm (2011) are shown. Note that the 0.7 multiplier between two consecutive nodes; meaning half of the size of the key feature of the transistor in four years, much longer than the two‐year scale shown in Figure 1.30. They appeared as the “official” technology node definition. As mentioned technology node is defined from a set of parameters (features). Figure 1.35 show examples of technology node definition for 22 nm and 14 nm (for high‐speed logic) transistors. For technology node 22 nm (2011): the fin pitch is 60 nm, fin width is 8 nm, the channel length (i.e., the gate length) is 30 nm, and gate pitch is 90 nm. Channel length and gate pitch are illustrated in Figure 1.34. They are consistent with high speed logic given in Table 1.5. For technology node 14 nm (2013): the fin pitch is 42 nm, fin width is 6 nm, the channel length is 20 nm, and gate pitch is 70 nm.

Pfin

Source S contact Gate G Pitch (G-G) contact Pitch (G-G)

Drain D contact

L Fin width Source channel Lchannel contact

Figure 1.34 A 3D FinFET, and definition of fin pitch, fin width, pitch (G‐G), and channel length.

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Pfin =42nm Pfin =60nm

42 nm 34 nm height height

Si substrate Si substrate

22 nm process 14 nm process

Figure 1.35 Technology nodes: 22 nm (2011) and 14 nm (2013).

Continuing on the two‐year technology roadmap by Intel, ORTC of ITRS[76] speculates the following timeline: 10 nm in 2015, 7 nm in 2017, and 5 nm in 2019, see Table 1.7. In each technology node (from 16/14 nm down to 5 nm), all the key characteristics of flash, MPU/ASIC, and DRAM are defined. From Table 1.7, 16/14 nm (2013) technology node has a half pitch of 40 nm (logic), from Intel’s 14‐nm technology node definition, the gate pitch is 70 nm. They are at least consistent from the very beginning. Note that the technology node roadmap defined by ITRS[76] lists the annual targets. The technology node roadmap by Intel and ITRS are results of R&D efforts, or best educated guesses by the industry experts. The technology node is backward compatible to the established Moore’s Law. In a sense, the “theoretical” Moore’s Law by using technology node is still valid. However, there are different delays in volume productions for different

Table 1.7 Technology roadmap by ITRS.[76] Unit: nm.

2013 2014 2015 2016 2017 2018 2019

TechNode “16/14” “10” “7” “5”

MPU/ASIC M1 1/2 pitch 40 31.8 31.8 28.3 25.3 22.5 20 FinFET Fin W 6.4 5.8 5.3 4.9 4.4 4.1 3.7

Flash 1/2 pitch [2D] 18 17 15 14.2 13 11.9 11.9

DRAM 1/2 pitch (contacted) 28 26 24 22 20 18 17

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categories of devices: flash, MPU/ASIC, and DRAM. In the subsequent paragraphs, actual volume production timelines for devices in these categories are reviewed.

1.3.1.3 High Density and Logic Products: Flash, MPU/ASIC, and DRAM Technology node is a tool to manage future needs in R&D, engineering, tools, and equipment. It represents the collective consensus from many major research organiza- tions and industry companies. However, there is variability, among them, in prototyp- ing and volume production schedules.

1.3.1.3.1 NAND Flash Due to its relatively simple structure and high demand for higher capacity, NAND (non‐ volatile flash memory) memory applies the most aggressively scaled technology among electronic devices (Figure 1.36). Hynix has been able to fabricate sub‐20 nm NAND since 2011. In November 2012, Samsung announced that it had started production of 10‐nm scale chips. The aggressive trend of the shrinking process design rule in NAND flash memory technology effectively accelerates Moore’s law (Table 1.8). Table 1.8 shows the history of flash memory volume productions. At least up to 2013, flash memory products have had exactly the same schedule as the reference roadmap, if not advanced. MI Flash Technologies is a joint venture of Intel and Micron Technology, formed to manufacture NAND flash memory for use in consumer electronics, removable storage, and handheld communication devices.

1.3.1.3.2 MPU/ASIC and DRAM The major manufacturers for MPU/ASIC and DRAM include Intel, TSMC, Samsung, and GlobalFoundries. Intel is the only company that has the high performance (×86) and low power (Atom) IC manufacturing capabilities under one roof (Table 1.9).

100 Samsung Toshiba 50 Hynix 40

30 D.R. [nm]

20 50% design rule in two years

10 2007 2008 2009 2010 2011 2012

Figure 1.36 Trend of NAND flash memory (most aggressive silicon technology); design rule (DR) versus year.

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Table 1.8 Flash memory volume production history, compared to the Intel roadmap, in bold. MLC: multi‐level cell, TLC: triple‐level cell.

Yr Intel roadmap, ITRS, and companies

2011 22 nm 2012 20 nm ITRS Flash Roadmap Samsung 21 nm (MLC, TLC) MI 20 nm (MLC + HKMG) Toshiba 19 nm (MLC, TLC) SK Hynix 20 nm (MLC)

2013 16/14 nm 2014 16 nm ITRS Flash Roadmap Samsung 19‐16 nm V‐NAND (24 Layers) MI 16 nm Toshiba 15 nm SK Hynix 16 nm 2015 10 nm

Table 1.9 Volume production history for Intel products (x86 and Atom).

Yr TechNode & Intel products (x86 and Atom)

2007 45 nm 2008 Core 2 DUO, 2.4 GHz, 45 nm 2008 Bonnel (Atom) 1.86 GHz, 45 nm

2009 32 nm 2010 2ND Gen, Core, 3.8 GHz, 32 nm 2011‐2012 Saltwell (Atom), 32 nm

2011 22 nm 2012 3RD Gen. Core, 2.9 GHz, 22 nm 2013 Silvermont (Atom), 22 nm 2013 16/14 nm

Bold‐faced in Table 1.9 indicates the Intel’s two‐year roadmap reference. The Intel products follow immediately after their roadmap. Atom products fall behind a bit more. But, from the following figure, Figure 1.37, the Atom products are on the same footing as that for ×86 processors in 2014. In Figure 1.37, the roadmap of the technology used in two different areas (×86 and Atom) is shown. Saltwell and Silvermount (both Atom) was about one year behind their respective ×86 processors (Westmere and Ivy Bridge) in employing the same technology. By 2014, 14‐nm technology was applied by ×86 and Atom processors at the same time.

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Performance 32 nm 22 nm by ×86 14 nm

Low-power 45 nm 32 nm 22 nm 14 nm by atom 2011-2012 2013 2014

Figure 1.37 The process technology employed for x86 and Atom within Intel.

Table 1.10 Intel roadmap and volume production history for Apple’s A-series SoCs (volume production by either TSMC or Samsung). Bold indicates the Intel roadmap.

Yr Intel roadmap & volume production technology

2009 32 nm

2011 22 nm 12‐Sep‐12 A6 (3G), 32‐bit SoC, 1.3 GHz, 32 nm

2013 16/14 nm 10‐Sep‐13 A7 (4G LTE), 64‐bit SoC, 1.3‐1.4 GHz, 28 nm 9‐Sep‐14 A8 (4G LTE), 64‐bit SoC, 1.4 GHz, 20 nm

2015 10 nm 9‐Sep‐15 A9 (4G LTE), 64‐bit, (1.85 GHz), 16/14 nm 7‐Sep‐16 A10 (4G LTE), 64‐bit, (2.34 GHz), 16 nm (TSMC)

For Apple’s ARM SoC (A‐series application processor) volume production, (see Table 1.10), it falls behind the reference roadmap by two to three years. In 2015, Samsung was assumed to be the major volume producer for Apple’s A9, which uses 14‐nm technology. TSMC focused on 10‐nm technology development, and had to be ready for A10 in 2016. However, Intel got the shot at manufacturing Apple’s A‐series chip, A10,[77] using its 10‐nm technology; on the other side, it was mentioned that A10 might not use 10‐nm technology, as announced by TSMC. According to TSMC, Apple’s A10 might have been manufactured by TSMC using their 16‐nm technology. According to TSMC technology,[78] TSMC has advanced 12‐inch wafer fabrication for 0.13 µm, 90 nm (70% shrink), 65 nm (70% shrink), and 55 nm (90% shrink) devices. In their more advanced technology, 40 nm, 28 nm (70% shrink), 20 nm (70% shrink), and 16 nm (80% shrink) are used for mobile applications. The company started making chips for devices such as smartphones and tablets using the 20‐nm process in early 2013. TSMC’s 20‐nm technology was developed for the Apple application processor, A8. The Apple A8 is a 64‐bit SoC designed for iPhone 6, which became available on September 9, 2014. In April 2013,[79] it was disclosed that a very aggressive SoC design for ARM’s Cortex‐A57 used TSMC FinFET 16‐nm technology. Volume production began around the end of 2013. Qualcomm and Broadcom were likely to be TSMC’s FinFET customers. In early 2013, however, TSMC acknowledged that it lost the Altera contract to Intel, who used a more advanced 14‐nm technology.

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Figure 1.38 A7 (left) and A8 (right), where CPU and GPU cores along with PLLs are shown. Source: Images courtesy of Chipworks Inc.

TSMC demonstrated the 2.5D silicon interposer technology (CoWoS) for Xilinx and Altera in FPGA, and SK Hynix, Cadence, mentor graphic in wide I/O. Samsung manufactured the Apple application processor, A6 using Samsung’s 32‐nm technology. The Apple A6 is a 32‐bit SoC designed for Apple’s iPhone 5, which became available on September 12, 2012. Apple’s application processor, A7, was fabricated using Samsung’s 28‐nm technology. The Apple A7 is a 64‐bit SoC designed for Apple’s iPhone 5S available on September 10, 2013. A7 is the first Apple’s ARM SoC that uses 64‐bit system. On a mobile device, ARM SoCs, such as the A‐series Application processors, A6, A7, and so on, are the key IC. ICs are fabricated in wafer foundries using MM (more Moore) technologies. On APs A7 and A8, there are CPU and GPU cores along with PLL circuits, Figure 1.38.[80] A7 has a size of 102 mm2 (9.83 mm × 10.45 mm), and A8 89 mm2 (8.47 mm × 10.50 mm). A9 had two different sizes, 96 mm2 and 104.5 mm2, by Samsung (14 nm) and TSMC (16 nm), respectively. GlobalFoundries, which moved to the 14‐nm process in 2014, makes chips based on ×86 and ARM processor designs, and also graphics processors. According to Bloomberg news, Apple used production capacities of Samsung and GlobalFoundaries for I9 chips. It was unclear whether TSMC would be involved in production of the A9 processor for Apple. Samsung foundry was already making commercial chips using 14 nm FinFET (14LPE, low‐power early) manufacturing technology. GlobalFoundries intended to start production using Samsung’s 14LPE tech in the first half of the year 2015, even though it is unclear how many wafers GlobalFoundries can produce using the 14LPE. By contrast, TSMC said it would only start production of semiconductors using its 16 nm FinFET (16FF) fabrication process only in the third quarter of 2015, which is later than expected. Figure 1.39 shows the silicon technology (in nano‐meter, nm) used in ×86 CPU IC and A‐series chip (ARM SoC) by Intel and Apple, respectively. Both are logics ICs.

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10,000

Pentium 386

1,000 286 486

100 iPhone 5S

Pentium4 Technology [nm] 10 iPhone 6

1 1980 1990 2000 2010 2020

Figure 1.39 Combined x86 and A‐series ARM SoC products by Intel and Apple, respectively.

The 1993 Pentium used 0.8‐mm technology, and the clock speed was 66 MHz. In 2000, the Pentium 4 used .18 mm technology, and it has clock speed of 1.5 GHz. A7 was used in iPhone 5S (64‐bit system), which has clock speed of 1.3 to 1.4 GHz, 28 nm technology was used; A8 was used in iPhone 6 (also 64‐bit system), which has a clock speed of 1.4 GHz, and 20‐nm technology was used. There are about two years of delay between the red (smartphone using A‐series chip) and blue lines (×86 IC production). The delays could easily be explained by the longer preparation for the massive volumes required in smartphone production (that is, it is not just ×86 ICs, but the entire iPhone product line). The sales volume for smartphones in 2014 was 1,245 million,[81] and that for desktop and laptop combined in the same year was 300 million.[82] LPDDRs are used as volatile memory for the ARM SoC on a mobile, whereas DRAMs are employed as volatile memory for CPU on an ×86. One GB LPDDR3 has been used in iPhone 5S (A7) and iPhone 6 (A8). Shown in Figure 1.38, are two chip layouts for A7 and A8, where it is obvious that A8 has upgraded to a dual‐core CPU, whereas both have quad‐core GPUs. Two GB LPDDR4 made by Samsung were used in iPhones 6S and SE (both use A9 with dual‐core CPU, using 16/14 nm technology, and 2 GB memory). LPDDR4 using 20 nm technology was in iPhone 6S. DRAMs are packaged in 2D memory modules, shown in Figure 1.46. Technology employed in volume production for both LPDDR and DRAMs is a bit behind that used for applications processors (see high‐density and logic discussions in Chapter 9). To further integrate IC with other IC(s), bare or packaged, and/or with other supporting passives, MTM is employed. MTM is now introduced.

1.3.2 More Than Moore

After the introduction of technologies related to MM, it naturally leads us to another focus of this book, more than Moore (MTM). MM has produced electronic products in IC forms. MTM is the next level of integration that uses ICs and passives as its building blocks (see Figure 5.4 in Chapter 5). Both MM and MTM are planar technologies that

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are capable of miniaturization in massive scales. Miniaturization results in portable devices (thin and light), whereas mass production results in affordable prices. RF modules are important products found in the RF FE section in wireless systems. Passives, in large number, are indispensible components to deiver RF functionalities, so “RF‐passives integrated system” is an appropriate name to describe a RF system. For the convenience of discussion, we divide the semiconductor packaging into two groups: the first one is “single‐chip packages,” or SCP, and the second group, “system in a package,” or SiP. The bulding block products in either group have to be tested “known‐ good.” In the first group, the building block is bare die. The bare die are normally packaged, and become “single‐chip packages,” and testing is performed at package level to weed out the bad single‐chip packages. However, some bare die, are tested at wafer level without a package, and they become “known good bare” die. Further integration is applied to either KGB ICs and/or packaged ICs, and sometimes, along with a multitude of passive components to produce SiPs. Single‐chip packages (SCPs) can be classified into organic interposer (OI) and lead frame (LF)‐based package, in addition to specially obtained KGB die. SiPs include MCM (or MCP) and modules, to be discussed later. In general SCPs are standardized products, whereas SiPs are customized. In the following paragraphs, SCP and SiPs are discussed, and associate each and every packaging format with a product we review in wired and wireless communications. In so doing, readers may be able to grasp and appreciate more the key features of MTM (SCPs and SiPs) technology. For example, where or when a KGB die is used? Is BGA used only for high I/O CPUs? What is the best package for a PA, or any other RF devices? What is the key characteristic of RF packaging? Why multi‐chip package is nowadays just a‐few‐chip package? Why the 2D multi‐chip packages are not practical? Moreover, we are interested in the packaging formats that are most suitable for Mobility, which requires portability, light weightedness, small‐ and thin‐form factors, battery that lasts, in addition, WAN radio accessibility and RF wifi connectivity.

1.3.2.1 Single‐Chip Packages: OI (LGA, BGA, and CSP), KGB, and LF (QFN)‐Based The single most important function of a packaging is to provide I/O extension from the chip, and, this function is sometimes called “re‐distribution.” The mechanical structures employed to fulfill the functionality include 1) lead frame (LF) based and 2) organic interposer (OI) based. Packages that employ a lead frame are TAB (tape automated bonding) and QFN (quad flat pack with no lead), for example, and that employ organic interposer are BGA (ball grid array), CSP (chip scale package), and LGA (land grid array), and so on. As a matter of fact, LGA is an interesting packaging format. It can also be made using a metal frame. It will be elaborated in Chapter 3. Of course, there is a third category, that is, a KGB die directly attached to a printed circuit board (PCB) motherboard. Though appearing exactly the same as a bare die just sawn off from a wafer, this directly attached die (DCA) has in fact gone through rigorous wafer level testing, and has been determined “known good,” so is called “known good bare,” or KGB. The materials and processing aspects of these packaged (lead and organic interposer based) or bare‐die formats are discussed in more details in Chapter 3.

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The following key packaging formats are reviewed: LGA (Pentium 4 CPU), BGA (A6 CPU and Qualcom’s transceiver RTR8600), and a KGB (Broadcom’s Touch screen IC). The device(s) in the parenthesis immediately following the package are the device(s) reviewed. Pentium 4 CPU is used in many desktop computers, which provide horse power for wired communications; A6 and Qualcom’s transceiver RTR8600 are the main devices the iPhone 5, the most popular wireless device. Broadcom’s touch screen IC is used in the iPhone 5 for user interface.

1.3.2.1.1 OI Based LGA The Pentium 4 CPU is packaged in land grid array (LGA) format, and then housed in a socket. In a pin grid array (PGA), the I/O format, instead of solder balls, is a long hard metal protrusion. In LGA package, the I/Os are a flat metal squares, and the pins are in the socket it mates to. Figure 1.40 shows the lid processor with a metal lid (left), the socket (LGA775) for the CPU (middle), and the bottom view of the CPU (right). Shown in Figure 1.40 is an Intel CoreTM2 Quad processor Q8300 (64‐bit, 45‐nm technology, and dissipated power 95‐watt): 2.5 GHz (processor base speed), 4 MB L2 cache, 1,333 MHz bus (FSB). It has a metal lid as the protection, which shields the CPU from being chipped or cracked by the socket. The lid also acts as a heat spreader (an integrated heat spreader, IHS, or simply a copper slug, see Figures 2.10, 2.11 in Chapter 2). When the socket is in the closed position, heat is dissipated through the air‐cooled heat sink device (not shown) on the top of the socket. Inside the lid, there two CPU configurations, see Figure 2.24 in Chapter 2: one, the CPU is flip‐chip attached to a PCB with HDI (high density interconnect); the other, CPU sits in the cavity of a PCB. Between the heat spreader and the back of the processor there is TIM (thermal interface material), which helps to remove the heat from the back of the CPU. It is likely the HDI has a pitch of 0.33 mm to accommodate the flip chip bumps. LGA is related to BGA (ball grid array), which will be introduced and discussed in more details in Chapter 3. On the motherboard of a desktop or a server, the DRAMs are installed. DRAM memory of sizes of 2 and 4 GB are popular in a desktop, and are as large as 16 and 32 GB in a serve.

Round LGA pads

Figure 1.40 The left-most figure shows Intel CoreTM2 quad processor (Q8300) with metal lid sitting on the socket shown in the middle (a LGA 775 with a bed of spring connectors, see Figure 3.10 in Chapter 3); the right figure shows the bottom LGA pads of the processor. Note that the spring connectors and the round LGAs are one‐to‐one in match.

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External I/Os, for example, IDE for hard drive (serial ATA, or sATA), USB for external flash memory, and PCI or PCIe (PCI express) for external ethernet communications, are placed on the peripheral of the motherboard.

BGA, CSP, and WL-CSP BGA has been popularly applied in packging RF transceivers. As an example, Fujitsu’s transceiver MB86L11A is packaged in BGA.[83] Implemented in submicron CMOS (i.e., RF CMOS single‐chip solution), Fujitsu’s integrated MB86L11A transceiver module in IC package eliminates external low‐noise amplifier (LNA) and inter‐stage SAW filters from the transmitting and receiving paths of both 3G and LTE lineups. It is encased in a compact BGA package measuring 6.6‐mm × 6.6‐mm. Qualcomm’s RTR8600 is a radio device for iPhone 5 (A6 is used) packaged in plastic BGA. A more advanced version of RTR8600, WTR1625L, also by Qualcomm, is shown in Figure 3.1 in Chapter 3. “R” in RTR refers to “plastic,” that is, the molding material in BGA. “W” in WTR indicates wafer level CSP (WL‐CSP). In a WL‐CSP (or WCSP), the redisctribution layers are replaced simply by BCB or PI blank layers at Wafer foundry. WL‐CSPs are used when the number of I/Os is low. The newer transceiver (for A8), WTR1625L needs WFR1620 to achieve carrier aggregation function (see Figure 5.2 in Chapter 5). On the figure, WTR1625L and its modem MDM9625M are located on the different sides of the logic board. BGA is also used as the first level package for A‐series application processors. A de‐ processed application processor is shown in Figure 1.41. Clearly from the figure, there are no square I/O pads on the application processor. Flip chip bumps are the only obvious I/O structures. The dots shown in Figure 1.41 are the under bump metallurgy (UBM) for the bumps. The gold color in Figure 1.41 is actual the color for Cu/low‐k. There are 39 bumps on a row. The processor IC itself is 97 mm2 in size, and the CPU is likely fabricated using the 32‐nm technology by Samsung.

Figure 1.41 A de‐processed application processor for A6. Source: Image courtesy of Chipworks Inc.

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Figure 1.42 A ball grid array (BGA) external views: top (left), bottom (right).

It is estimated that the pitch of the HDI top of the organic interposer would likely be 0.25 mm. Cache memories, L1 (32/32/kB) and L2 (1 MB) are fabricated along with GPU cores on chip,[84] and I/Os for the peripheral devices on the iPhone 5 are fabricated on the CPU, too. The A6 CPU is flip chip attached to an organic board (the interposer). The bottom of the interposer is an array of solder balls. After the molding material is applied on the CPU, an A6 in a BGA (ball grid array) package is created, as shown in Figure 1.42. Inside the BGA, the chip can be flip chip attached to the organic interposer, or can be wirebond connected to the interposer. For more internal views of a BGA, please refer to Chapter 3. In Figures 1.3 and 1.47, the A‐series AP in BGA format is further integrated into PoP in the next‐level packaging. From the examples of A6 CPU and RTR8600, we found BGA have been applied in both digital and RF transceiver domains. But, one important characteristic is that BGAs are for devices with relative high I/Os. It is the most popular package configuration for high‐end products (CPU, FPGA, which are all system on a chip, SoC). Sometimes, it is the package for SoCs. There is, however, a low I/O version of BGA, that is, CSP (chip‐ scale package), such as iPhone transceiver WTR1625L. In sumary, the OI (organic interposer, defined in Figure 3.15 in Chapter 3) is used for re‐distribution (RDL). BGA has full OI as its RDL, WL‐CSP has reduced OI using only a blank layer of BCB or PI[85] for RDL, and since the layer can be applied in a wafer foundry, so it is named. LGA and BGA represent two very different markets: one for high‐power desktop and server market, the other low‐power and mobile market. We see many differences between an ARM‐based CPU (e.g., application processor A6 of iPhone 5) and a CISC‐ based CPU (e.g., ×86 Pentium 4). The size of an ARM‐based CPU is less than 100 mm2. That is, the entire functional system is fabricated on a single chip, thus, the ARM CPU is called, “system on a chip,” or SoC. The Pentium chipset as a functioning system has a size of a motherboard. As mentioned, the levels of the power dissipated are different; CPU on a chipset is rated at 90 to 100 W, whereas an ARM‐based CPU consumes less than 1 W. Figure 1.43 show the power consumption for different CPUs. The power consumption for NB is about 50 to 60 W, and for Atom SoC, so it consumes only a few watts, Figure 1.43.[86] As a matter of fact, in a desktop computer, Pentium 4 has a size of 217 mm2, and dissipates heat of 80 to 90 W. The heat density is as high as 45‐50 W/cm2. No wonder extensive heat sinking apparatus is needed for such a high‐power CPU.

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Figure 1.43 Power consumption for x86 Desktop CPU in the chipset and Atom (SoC). 60 W NB 40 W

20 W New NB 10 W

5W SoC <1 W

Multi-processor capab. Protocoled communication Favorable

Power High-end consumption game (least the better)

Price (least the Portability better)

Figure 1.44 Radar chart for a CPU in a chipset and a single chip (SoC).

The prices are drastically different, too. A Pentium is about $350 to $400 (a motherboard is about $700 to $900). According to a recent report, A6 BGA costs about $28, the 1GB SDRAM (S for synchronized), $4,[87] 16 GB NAND, $9. The I/O capabilities are different: ×86 CPU works with the bridge ICs and then connected to PCI/PCIe with high‐end communication protocols. The ARM CPU only works with lower speed I/Os. And, these I/Os have only a few pins (two to four pins), and no communication protocols are used. The user experience drew from the CPUs are drastically different. An ×86 CPU is able to open many processors, and some can even co‐exist. For example, a user is able to listen to music, while working on Word editing. On an iPhone, or an iPad, only one processor can be run at a time. The font choices are limited, too for iPhone or iPad users. From Figure 1.44, we see that these two processor CPUs are diagonally different.

1.3.2.1.2 Known Good Bare (KGB) IC(s) In an iPhone 5, Texas Instruments’ TI27C245I touch screen SoC and Broadcom’s BCM5976 touch screen controller are bundled together to produce Apple’s unique, impressive users’ touch screen experience (see Figure 1.45). The Broadcome controller is made in a KGB die format, and seems to be the only bare IC on the Apple logic board.

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Figure 1.45 Broadcom’s bare die, BCM5976, is next to TI’s SoC shown in Figure 1.7. Source: Image courtesy of Chipworks Inc.

As exemplified by BCM5976, the DCA (direct chip attachment) board assembly technique that directly attaches a known good die on the printed circuit board (PCB) has design considerations. The die attachment has added another manufacturing step. Solder reflow is the most frequently used, regular assembly technique for all the surface mount devices (SMDs, such as passives and BGA SoCs). DCA would require another process called “underfill,” which is not conveniently available for regular board assembly. Other discussions on known good bare die or DCA can be seen in Chapter 3. Please note that OI’s foremost role is to provide the RDL (re‐distribution layer) function.

1.3.2.1.3 QFNs (Lead Frame Based) We have so far touched upon only the single packages that utilize an OI (LGA, BGA), reduced OI (CSP, or WL‐CSP), or without any OI (i.e., known good bare die). QFN is another single‐chip package; yet it utilizes a lead frame, instead of an OI. QFNs are one of packaging platforms suitable for RF and high‐frequency devices, because of the short I/O paths, and the signal transition that can be further improved. One important characteristic for QFN is that it is used in low I/Os RF products (power amplifier, low noise amplifier). However, this has changed somewhat. Some companies have added rows of I/Os. Moreover, some companies have more than one die on a QFN, making it a QFN MCP. We will study more about QFNs in later Chapter 3 on IC packages.

1.3.2.2 MCM/MCP (WB) MCM and MCP represent multi‐chip modules or packages, in which KGB die are used as the building blocks. There are wirebond MCM/MCP and other MCM/MCPs that employ advanced interconnections schemes, such as TSVs and micro‐bumps, and Cu‐ Cu bonding techniques, introduced later. In this chapter, a MCM/MCP based on wirebonds is shown. Refer to Chapter 9 for MCM/MCPs based on advanced interconnection schemes. Since it is risky to integrate many bare die (cost is too high if one of the die fails), a multi‐chip package nowadays is actually “a‐few‐chip package.” Two‐chip MCPs, CPU and memory, transceiver and MAC/BB, appear to be the most popular. In Chapter 3, these packages will be discussed in more details.

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1.3.2.2.1 3D Wirebond Stacked MCPs In the iPhone 5, the wireless WAN RF FE section consists of two key devices: one is Qualcom’s RF transceiver, RTR8600, and the other Qualcom’s baseband device, MDM9615M. The baseband device is responsible for physical layer modem functions, and is fabricated using Samsung 28 nm LP CMOS technology. Multi‐chip package (two‐chip MCP) is employed to integrate the baseband device with its 1 GB DRAM memory, also by Samsung. In the MCP, wirebonds were used to connect I/Os between the modem IC and the memory. The 3D wirebonding technology has been around for about 10 to 15 years.

1.3.2.2.2 Other 2D and 3D Wirebond MCPs Other 2D and 3D wirebond MCPs are discussed in Chapter 3, Figures 3.22 and 3.23. In the following sections, modules are introduced: 2D memory module (a Kingston memory, 3D PoP (A6 CPU and its main memory), and RF module (Murata’s wifi module). Module is a very broad term used to describe customized packages, digital or RF. In general, RF module involves bare or packaged IC(s) and/or multitude of passives (discrete components mainly) integrated in ceramic, or organic platform. RF modules and SiP modules can be used inter‐changeably, see or SiP modules (see Figure 9.7 in Chapter 9, a term used by ASE). RF module, or SiP module, integrates devices and components from different technologies and sources; thus, is considered a heterogeneous technology.

1.3.2.3 Modules 1.3.2.3.1 2D Memory Module (Using Packaged ICs) DRAM memories are often inserted to the motherboard of a desktop or a notebook computer. It is usually the first memory external to the CPUs. The memory is BGA packaged, and an array of memories is placed on a module. The sizes of the DRAM memory include 1 GB, 2GB, and 16 GB. The size of the DRAM impacts significantly the speed of an application on a desktop or a notebook (see Figure 1.46).

Figure 1.46 Kinston’s memory module made from BGA packaged memory ICs.

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1.3.2.3.2 PoP—A 3D Module (With Packaged ICs) Now, we use teardown analyses of iPhone 4 (inside, application processor, A4) to illustrate the various forms of package configuration. 3D PoP (stacked packaged on a package) technology has been employed to package A4 and its mobile memory LPDDR (see Figure 1.3). Inside the PoP, there are actually two types of ICs: one is the application processor (bottom), and the other LPDDR (top). Note the two rows of TMVs (L1.5) are present in the PoP (Figure 1.3). The same PoP technology has been applied for an optical FPGA by Altera. Constructually, an AP/LPDDR PoP can be prepared in two steps: 1) preparing an A4 SoC in a BGA and LPDDR memory in another BGA, and 2) joining them one (LPDDR) on top of the other (SoC), (see Figure 1.47 below). The only requirement is that the top BGA balls have to be larger than the height of the flip chipped (shown in Figure 1.47) or wirebonded IC. The two‐step PoP is improved by eWLB (embedded wafer level BGA) and TMVs, (see Figures 3.24 and 3.25 in Chapter 3). Fan‐out (FO) or Fan‐in (FI) eWLB processes were invented by Infineon for WL‐BGA and WL‐CSP packages. The FO process is then applied in fabricating the bottom AP BGA with eMC (epoxy molding compound). This process is called FO‐WLP. Through Level 1.5 TMVs in eMC (not BGAs), new FO‐PoPs are born. Later, TSMC announced their InFO‐WLP, and consequently InFO‐PoP (see Figure 9.2 in Chapter 9). Other example of integrating a SoC in a PoP includes Motorola’s processor in a Droid RAZR.[88] Dual‐die is the most popular product combination, taking advantage of the computing efficiency of a processor and its memory, a general purpose CPU and an ASIC, and so on. Dual‐die in 3D PoP is used for performance reason, and it is essential to make it as thin as possible. The thickness of a mobile LPDDR BGA is between 0.8 to 1.4 mm. Currently, 2.5D IC MCP technology is being developed. In 2.5D IC, a silicon inter poser (SI) is used as a RDL between the ICs it accommodates. On silicon interposer, the redistribution layer structures are fabricated, and inside the silicon interposer, there are many through silicon vias (TSVs) used to connect the ICs. Examples include Xilinx’s and Altera FPGAs,[89] where TSMC’s CoWoS may be used. Moreover, 3D IC MCP technology, which employs microbumps and TSVs, are important development. 2.5D IC and 3D IC multi‐chip technologies will be the main topics in Chapters 2 and 3. Please note that the term “multi‐chip packages” is reserved for the packages that integrate known good bare (KGB) die only. 3D PoP, therefore, is not a MCP, but a module, according to our terminology.

L1 Border of Subst two BGAs L1.5 connections using larger BGAs Subst L1 L2 BGA PCB

Figure 1.47 Early and concept drawing of packaged on a package (PoP) packaging form.

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1.3.2.3.3 RF Modules (With Bare or Packaged ICs and Passives) Inside the iPhone 5, a Murata wifi RF module 339S0171 was installed. As a matter of fact, the RF module consists of Broadcom’s BCM4334 single‐chip dual‐band combo device supporting 802.11n, Bluetooth 4.0 + HS, and FM Receiver.[90] The IC was fabricated using a low‐power 40 nm RF‐CMOS process from TSMC and it measures 4.07 mm × 4.48 mm (see Figure 1.48). The reason a bare die was used was meant to meet the low‐profile requirement. Note in Figure 1.48, a bandpass filter (BPF) is used in Murata’s wifi module. A bandpass filter, which is made of passives only, is used to selectively pick up signals in certain band, and filter out the un‐wanted signals. Popular RF SiP technologies, IPD (integrated passive device) and EP (embedded passive), are often employed to integrate or embedded the passives on the top of or inside a PCB and to perform certain RF functions, such as, filtering, balun, and impedance matching. One of key characteristics in RF packaging is that there are many passives (on an RF module, or on a printed circuit board), and to effectively manage them has become the focus of many researchers and technologists. Antenna is a passive component, and a very important one, since it is used to communi- cates wirelessly with other devices. An antenna may be integrated on an IPD along with an accompanying PA or LNA, thus, turning an IPD into an antenna IPD (or Ant‐IPD). In Murata’s RF module (actually, Broadcom’s BCM 4334 was packaged inside the module), a bare IC is used if thinness is demanded. In a Kingston memory module, thickness is not the most demanded characteristic, so an array of BAG packaged memory ICs is installed on a PCB to form a memory module. Usually, a known good IC is more expensive than the BAG packaged IC. If the product thickness is not actively sought, using BGA package ICs leads to cost saving (Figure 1.49).

Figure 1.48 A bare die BCM4334 on Murata’s wifi RF module 339S0205.[90] Source: Image courtesy of Chipworks Inc.

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Figure 1.49 A bare IC, BCM4334. Source: Images courtesy of Chipworks Inc.

In this section, we reviewed several key packaging configurations that have been used currently. Basically, there are single‐chip packages and system in a package. In single‐ chip package, we found LGA and BGA serve very different CPU markets; LAG for ×86 CPU in a chipset, BGA for ARM‐based CPU; BGA is typically used for high I/O devices, and it can be used for digital and RF ICs. BGA is almost synonymous to SoC (system on a chip), since it is always used the package high‐end SoCs. It is known that good bare IC has a certain inconvenience when attached to the main PCB. We mentioned that QFN is mainly for low I/O RF and high frequency devices. In system in a package arena, we are dealing with multi‐chip packages, modules, and RF components. We reviewed 3D stacked MCP and 3D PoP module. These technologies, employing wirebonds and flop chip bumps, have been available for many years. 2.5D IC, which uses silicon interposer with advanced TSVs, and 3D IC, which uses TSVs and microbumps, are being developed currently. The passives are needed in RF circuits to fulfill filtering, balun, impedance matching, and so on. RF functions. The passives, including antenna, have become key characteristics for RF packaging. Thus, it is important to effectively manage them. IPD and EP are important RF SiP technologies. The choices of KGB die or packaged ICs, wirebonded or bumped, depend on the product outline requirements. If the product demands absolute thinness, KGB die and flip chip bumps are usually used, if the cost is not an issue.

1.3.3 MTM Packaging Map and MM‐MTM Business Model 1.3.3.1 MTM Packaging Map, State of the Art MTM Map (PKG) summarizes various types of packages mentioned in the previous section, organized in a XY plot. X‐axis represents the level of integration (from amorphous form to 2D, 2.5D, and 3D), and Y‐axis the degree of monolithicity (from hybrids

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to monolithic‐based). Silicon represents high degree of monoliticity (active devices can only be built on silicon); passives represents low degree of monolithicity. For x‐axis, the amorphous state at the left end represents components physically embedded in substrates. Moving toward the right in x‐axis, the level of integration for packages increases, from two‐ to three‐dimensional. For y‐axis, monolithicity, at the top, means silicon‐based and metallizations that are compatible with silicon, such as aluminum (earlier in FEOL) and copper (later in BEOL), whereas hybrids means passives, for example, ceramics, or organic based, with many choices of metallization, such as, Au, Pb, Sn, Nickel, Cr, and Cu (electrolytic or electro‐less plated). From y‐axis, ICs and passives are two building blocks of MTM hardware (see Figure 5.4 in Chapter 5). There are many electronic assemblies in the communication market. In Chapter 1, we have seen many electronic assemblies, such as QFN, BGA, LGA, and modules (2D memory, 3D PoP, and RF modules), and so on. As shown in Figure 1.50, MTM Map (PKG) organized the electronic assemblies in a XY map. The x‐axis denotes the level of integrations: embedded (amorphous, or no form), 2‐D (e.g., single‐chip package, or SCP, standard components), and 3‐D (stacked, customized assemblies). The Y‐axis denotes the degree of monolithicity. Passives are usually not constructed using silicon. From Figure 50, MTM contains basically two categories of packages: single‐chip package (SCP) and system in a package (SiP). SCPs are standard components, and are highly monolithic, whereas SiPs are customized components, including multi‐chip package (MCP) or multi‐chip module (MCM), modules (2D memory modules, 3D PoP, and RF modules). Features of a SiP include, first, low in monolithicity (i.e., many or more passives); second, a higher level of integration is usually needed (to form a

SCP

Monolithic/ MCP/MCM: active KG Bare 2D, 2.5D (SI), & 3D (3D IC)

BGA/ Modules (2D) QFN CSP & PoP (3D)

PGA/LGA RF modules (Bare, Pkgd) RF modules (Bare, Pkgd) Y: Degree of monolithicity IPD Passives/ EPs SiPs hybrids EPS SMD/IPD Embedded, Standard Customized amorphous -> 2D assemblies ≥ 2D X: Level of integration

Figure 1.50 MTM‐PKG map: X‐axis being the level of integration (from amorphous to 2D, to ≥2D), y‐axis being the degree of monolithicity (from hybrids to monolithic‐based).

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combination of ICs and passives); and third, they are more customized components, unlike SCPs, which are JEDEC standards. Heterogeneous RF‐passives integrated systems (RF SiPs), introduced in Chapter 9, are expanded technology/concept from RF modules. RF SiPs may be a new breed of packaging format. It is that contains active devices and passives on high‐performance substrates (hi‐ res silicon and glass) using large area processing techniques (wafer‐level or large panel planar). Hi‐resistivity silicon or glass are low considered as low loss substrates; the low loss property can be used to boost the performance of passives. Wafer level techniques include IPDs, CSP, and InFO, and currently, the wafer size is 300 mm. The 450‐mm wafer processing is in planning stage. Large panel for glass are at least 500 mm in diameter. Wafer level and large panel employed for cost saving purposes. Heterogeneous RF SiPs often used EPs and IPDs as their build blocks. EPs and IPDs consist of a collection of passives performing RF functions, such as filtering, balun, duplexing, tuning and matching, and so on. Hidden in the more than Moore (MTM) packaging map are substrates and processing technologies. In Chapter 3, the Y‐axis of the MTM map can be changed to “Substrates,” in Chapter 4, the y‐axis of MTM map can be changed to “passives,” (see Figure 4.2). That is, Figure 1.50, Figure 3.17, and Figure 4.2 represent the state of the art packages, substrates, and passives technologies. In Chapter 9, a modified MTM map is used to represent the solutions for 5G mobility. For performance and cost‐effective reasons, advanced stacking and large‐area plannar technologies are pursued as solutions for future 5G mobility. Advanced interconnection techniques are discussed in Chapter 9 to fulfill 3D (bare) stacking; large panel processing, either wafer level (450 mm) or glass (>500 mm), are pursued for cost‐saving strategies (refer to Figure 9.27 in Chapter 9 for more detailed discussions). Figure 1.51 below shows relationship between MM and MTM. MM and MTM are referred as technologies used to build two different levels of electronic systems; one at wafer level (in wafer foundries, monolithic‐based), the other at SiP level (in OSAT, hybrids and many passives). MM refers to technology used to manufacture ICs. In MM, two popular computing architectures are produced: one is ×86, the other ARM. X86 is applied in high‐performance desktops (sometimes notebooks too) and servers; ARM, or SoC, is employed for low‐power mobile products, such as smartphones (iPhones) or tablets (iPad or Surface). MM also produces RF CMOS transceivers for homogeneous RF-passives systems.

Figure 1.51 Classification of MM and MTM; two different business models; MM (WF) one with high margins (MM), the {X86 CPU other with less margins (MTM). (on an SoB), ARM (SoC), and RF CMOS}

SCP

MTM (OSAT) Supply chain

SiPs

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MTM refers to package choices for ICs fabriced from MM platforms. MTM includes SCP (KG bare ICs, BGA, LGA, and CSP) and SiPs (MCP, modules, and RF‐ passives integrated systems), see Figure 1.50 for the MTM packaging Map. SCPs are standard components, whereas SiPs are customized components. MTM factory is an OSAT. Before wafers are shipped to an OSAT site (or a back‐end facility), they (the wafers) are passivated. The first thing OSAT do is to create openings on the wafers, for interconnection (wirebonds or flip‐chip bumps) and packaging. The opposite of SoC (an ARM, or other microcontrollers) is SoB (system on a board, which can be ×86 mother board), not SiP. From the above discussion, the opposite of SiP is monolithic‐centric single‐chip package (SCP). Since SoC is always realized in SCP, people equate SCP (physical unit) with SoC (computing platform, or architecture), which may not be proper.

1.3.3.2 Hardware Technologies for 5G Mobility According to International Data Corporation’s (IDC) Worldwide Quarterly Mobile Phone Tracker, it was predicted that mobile phone vendors would ship more than 1.7 billion mobile phones in 2012. In the first quarter of 2013, according to Gartner, the mobile phone sales volume was 426 million.[91] IDC forecasts 2.2 billion mobile phones will be shipped[92] in 2016. The prediction may be a bit too optimistic. According to [93] by IDC, worldwide smartphone sales surpass 1.4 billion for the year of 2015. Although the sales of handsets show a sign of slowing down, the demands for future 5G and IoT hardware are not wavering. The demands are further fueled by global efforts toward realizing the huge cloud computing, which includes the development of modern communication theories, algorithm realization, and even more fierce hardware miniaturization. In convergence of communications, wired networks with data rates in hundreds of Gbps and wireless WANs from 2G to 4G are introduced. OE (optical‐electrical) module[94] (a QSFP by Altera and Avago) are important in realizing GbE (gigabit ethernet), or even TbE (terabit ethernet). 5G’s goals of peak mobile user data rate 10 Gbps and IoT 100 billion connections are targeted to become fruition in 2020. Communication and radio access techniques to meet the demands are discussed. MEMS modules that contains sensing devices (accelerometer, temperature, stress‐strain, chemical sensing, etc.) can be in huge IoT demands. Using the tear‐down reports, we have reviewed state of the art packaging technologies for the highly popular, highly miniaturized handheld devices, the smartphones. First, we saw 3D PoP technology (see Chapter 3) had been applied to integrated SoC with mobile memory into a 3D SiP. As of a few years ago (September 2015, iPhone 6S using A9 was just available on the market), ARM Processor (A9 SoC) and mobile memory (LPDDR4) were fabricated using 16‐nm/14‐nm and 20‐nm technologies, respectively, in volume production. AP and its main mobile memory belong to high‐density & logic (HD&L) product line, and this product line appeared to demand the most advanced packaging (MTM) and CMOS (MM) and technologies in the recent years. Another important logic‐centric ICs, but did not employ the most advanced CMOS technology, are the base‐band processors (BB, i.e., the modem), for example, UE category 4 MDM9625 and MDM9225 used in A8 to manage global multimode multiband

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(MMMB) functions. BGA packaging form is used for the BB, and for the baseband processors used in A8, 28 nm technology was applied for volume production. Another area of focus in smartphones is RF front end (RF FE). In a smarphone, RF FE consists of two major RF‐passives sections: one is homogeneous RF‐passives integrated system, RF CMOS (i.e., the wireless WAN transceiver), and the other heterogeneous RF‐passives systems to perform power amplification (PA), switching/filtering, duplexing, and antenna tuning functions. Currently, these heterogeneous RF‐passives systems are realized in RF module formats. Other RF connectivity systems, such as Bluetooth, wifi, Zigbee, GPS, and so on, also use RF modules as the main packaging (MTM) technology. Passives are a building block for electronic systems (see Figure 5.4 in Chapter 5), and are indispensible in RF systems. State of the art MM and MTM technologies reviewed are for current wired and wireless communications market. In MM category, lithography enhancement (for example, Immersion technique) and device engineering (HKMG and FinFET) are the most advanced development, whereas in MTM category, PoP stands out as the most advanced hardware technology. In Figure 1.50, a MTM PKG map, consisting of SCP and SiP two categories, is shown. 5G mobility has aggressive goals. Various communications and radio techniques employed to meet the 5G demands are reviewed. Of course, new hardware development in MM and MTM are engaged to satisfy the demands. Carbon nanatube (CNT) is the main research topic in device engineering. EUV is one of the main focuses for future IC volume production. Other MM development that is worth mentioning is 450 mm (18 in) development.[95] In MTM, there are numerous new developments in interconnection and planar processing technologies (see Table 9.2 in Chapter 9). Example of new interconnection technology include TSVs‐micro‐bumps and Cu‐Cu bonding (both considered as Level 5, discussed in Chapter 2), TMVs and TIVs (both considered as Level 1.5, discussed in Chapter 4), and TGVs (in Chapter 9). Planar technologies include wafer level planar (which handles round wafers in passive silicon and galss) and large panel planar (which handles rectangular glass panels). Advanced interconnections are used to fulfill 3D IC stacking, and planar technologies are used mainly in heterogeneous RF‐passives systems for performance improvement (low loss) and reduced costs purposes. In Figure 9.18 in Chapter 9, MTM technologies used in 5G mobility hardware are illustrated. InFO‐PoP and 3D IC (MCM/MCP) will be used for HD&L product line (including AP and mobile memory combo) (see Figures 9.2, 9.5, and 9.7 in Chapter 9). 2.5D and 3D IC integration become available, where known good bare die, instead of the packaged ICs, are being integrated. 2.5D silicon interposer (Figure 9.5) has been used in yield enhancement (FPGA divided into four, and connected by a silicon interposer), 3D IC (Figure 9.7) has been applied in “a‐few‐chip” or “dual‐chip” (processor and its main memory) to replace PoP. The same 3D IC can be used in “many‐chip” or “several‐chip” MCP (stack of memory and a control logic, as those to be used in enterprise) to vastly increase the memory data throughput. RF SiPs and MoM will be used for heterogeneously integrated RF‐passives systems (such as those inside RF front end) (see Figure 4.52 and Figure 4.55 in Chapter 4 and Figures 9.10, 9.12 (an IPAC), and 9.15). In state of the art technologies, MM takes place in wafer foundries (or wafer fabs), and MTM in OSAT (outsourced semiconductor assembly and testing) sites. The division is

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a rather clear cut (see Figures 1.50 and 1.51, and SiP modules in Figure 9.11). Owing to recent advances in interconnection technology, planar technologies, the division appears blurred. From Figure 9.27, a new entity has appeared in the MTM landscaping, wafer level (wafer foundries look‐alike) and large panel planar technologies. Fan‐in WLP (WL‐CSP, WL‐NSP), WL‐IPD, fan‐out WLP (eWLB), 2.5D‐SI, WL‐CSP + IPD, and PoP are all wafer level processing that can occur in a WL planar site. 2.5D GI, glass IPD, and MoM can take place in LP planar sites. The new entity can be part of a WF, or belongs to an OSAT, depending on the product line, either high‐end or commontity due to margins consideration. WL planar existing in WF is possible when the facility is used for products that commend high gross margins. Continuing the Moore’s law, MM is getting too expensive to be affordable; however, 5G is just a couple of years away (2020, the targeted year). From the future volume production technology landscaping shown in Figure 9.27 in Chapter 9, WF can con- tinue to be a vital player in 5G mobility hardware arena by providing many WL planar services. For example, MM can only add the production capability, by expanding to 18‐inch wafer. TSMC made the announcement in 2015, it would soon to start 18‐inch site in the middle part of Taiwan, Taichung.[95] The 18‐inch wafer capability, however, is mainly for BEOL (that is, WL planar). On the other hand, from Table 1.1 and Figure 1.16, there numerous important MTM developments in OSAT. Undoubtedly, MTM and OSAT will contribute significantly to 5G mobility hardware.

1.3.3.2.1 3D IC for HD&L and RF SiPs for Heterogeneous RF‐Passives Systems From the title of this book, MTM hardare technologies, 3D IC and RF SiPs, are used to implement hardware for 5G mobility. Indeed, MTM technologies are focused in this book. Figures 9.2, 9.5, and 9.7 in Chapter 9 illustrate MTM technologies for current and future AP and mobile memory combo. In Figure 9.2, PoP using InFO by TSMC is shown. In Figure 9.3, 2.5D solutions using TSV‐less and InFO are shown, and finally, in Figure 9.4, a 3D IC MCM/MCP solution for the dual‐die combo is shown. The RF front end (FE), which consists of transceiver, PA, switching/filtering, duplexing, antenna matching tuner, and antenna(s). Transceivers, considered as homogeneous RF‐passives integrated systems, are fabricated using RF CMOS technology, and are packaged in BGA, CSP (or WL‐CSP). The rest of the components in RF FE, i.e., PA, switching/filtering, duplexing, antenna matching tuner, and antenna(s), referred to as heterogenerous RF‐passives systems, are packaged using QFNs and RF modules (see Figure 9.11 in Chapter 9). In the future, the heterogenerous RF‐passives systems will be packaged using RF SiPs and IPAC, see discussions in Figure A.6 or Figure 9.12. Refering to Figure P.6 in the preface, RF SiPs are MTM hardware technology that is expanded from RF modules. IPD (thin‐film multilayer, TFM), WLP and LPP are main additions. STMicroelectronics has offered RF IPD, IPADTM for RF design,[96] from a wafer site. Wafer level processing, which includes fan‐in WLP (WL‐CSP), WL‐IPD, fan‐out WLP (eWLB), and so on, is gathering momentum for products for either HD&L or RF‐passives systems. LPP, in which glass panels are used, is another MTM technology for RF‐passives systems. WL planar uses round high‐resistivity passive silicon wafers or semiconductor glass wafers, SGW 300 mm; large panel planar uses rectangular glass.

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Performance of passives heavily depends on the loss properties of the substrates. High resistivity silicon (wafer level) and glass (large panel processing) both have the desired low loss properties. Refer to Chapter 9 for more discussion on RF SiP. ON Semiconductor may be the first commercial company that uses the term, RF system in a package (i.e., RF SiP).[97] AP and mobile memory are a part of HD&L product line, and RF FE are RF‐passives systems that are frequently applied in wireless WAN and connectivity LAN products. Indeed, from above discussions, 3D IC and RF SiPs are future hardware technologies for products used in 5G mobility: HD&L and RF‐passives systems. From Table 9.2 in Chapter 9, advanced interconnection, such as TSVs and micro‐bumps, Cu toCu bonding techniques, TMVs, TIVs, and TGVs, are applied in both arenas to achieve many 3D MTM structures. Refer to Chapters 2, 4, and 9 for discussions on advanced interconnection technologies.

References

1 “Qualcomm and Samsung Collaborate on 10 nm Process Technology For the Latest Snapdragon 835 Mobile Processor,” November 17, 2016, Qualcomm Press Releases. 2 https://en.wikipedia.org/wiki/Spectral_efficiency 3 http://mcsindex.com 4 https://en.wikipedia.org/wiki/IEEE_802.11n‐2009 5 MCS (Modulation and Coding Scheme) index is a number identifier, ranging from 0 to 31, used to represent theoretical data rates associated with the number of spatial streams (1‐ 4), modulation (BPSK, QPSK, etc.) and coding schemes, and combinations of frequency bandwidth and guard intervals (20 MHz and 40 MHz, with 800 ns and 400 ns GIs). For example, for MCS index = 5, spatial stream = 1, 64‐QAM modulation, coding scheme = 2/3, bandwidth = 20 MHz, GI = 800 ns, the data rate is 52 Mbps. Another example, for MCS index = 13, spatial stream = 2, 64‐QAM modulation, coding scheme = 2/3, bandwidth = 20 MHz, GI = 800 ns, the data rate is 104 Mbps. 6 Refer to Nokia website for 1.44 Gbps demonstration, March 8, 2012 http://networks. nokia.com/news‐events/insight‐newsletter/articles/14‐gbps‐demo‐shows‐route‐to‐lte‐ advanced 7 “NSN and Sprint hit 2.6 Gbps TD‐LTE throughput,” PRWeb, February 5, 2014. 8 Refer to Nokia website for 3.78 Gbps demonstration, June 11, 2014 http://networks. nokia.com/news‐events/press‐room/press‐releases/lte‐throughput‐leader‐nokia‐sets‐world‐ record‐with‐sk‐telecom‐of‐close‐to‐4‐gbps‐using‐tdd 9 “Working principles and Applications of SAW/FBAR Devices” Taiyo Yuden Navigator; http://www.t‐yuden.com/wireless/E‐SP2_101013.pdf 10 “5G vision and requirements,” IMT‐2020 (5G) Promotion Group, 2014. 11 “Radio access technologies for 5G,” a PPT presentation by Takehiro Nakamura of NTT DOCOMO, 2014. 12 Mobile spectrum requirements and target bands for WRC‐15, GSMA Public Policy Position, November 2015. 13 Feilu Liu et al., “Small cell traffic balancing over licensed and unlicensed bands,” IEEE International Conference on Communications, December 31, 2014. 14 “Small cells big opportunities,” a Huawei white paper, February 2014.

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15 Backhaul in telecommunications refers to the links between the backbone (i.e., the core network [CN], which consists of mostly wired networks) and the leaves at the edge. Technically, backhaul provides the roaming capability. A non‐technical, or business, definition of backhaul is the wholesale bandwidth provider who guarantees networks’ quality of service (QoS) to the retailers. 16 Stefano Ruffini, “Synchronization in the mobile standards,” Workshop on Synchronization in Telecommunication System (WSTS), San Jose, 2013. 17 Damian Anzaldo, “LTE‐advanced release‐12 shapes new enodeb transmitter architecture: part 1, technology evolution,” Maxim Application Note 6062, 2014. 18 “Massive‐Element Antenna for Small Cell Solutions in 5G,” a white paper by NEC Corporation, 2015. 19 Gigabit ethernet (GbE) is a term used to describe ethernet technologies employed to support Ethernet frames at a rate of gigabit per second. It is designated as 1000BASE‐ XX, and XX is used to differentiate technologies. 1000Base‐T employs copper twisted pairs (Cat‐5, Cat‐5e, Cat‐6, and Cat‐7) for 100‐meter data transmission. 1000BASE‐EX employs single‐mode 1,310 nm wavelength for long haul (~40 km) transmission. Other GbEs include 40 gigabit, 100 gigabit ethernets, which operate at 40 Gbps (gigabit per second) and 100 Gbps, respectively. 20 Asymmetric digital subscriber Line (ADSL) is a data communications technology, in which downlink data speed is greater than that of uplink (thus, the descriptor, asymmetric). The technology co‐exists with voice signals over the POTS (plain old telephone service, see below), as shown in the following figure:

04kHz 25.875 kHz 138 kHz 1104 kHz

PSTN Upstream Downstream

where the green and blue bands are allocated for ADSL, and the red band for voices, that is, public switched telephone network (PSTN). 21 Plain old telephone service is commonly known as the copper landlines, which have been used to deliver voice services since 1877, when Bell Telephone Company was established. 22 IEEE 802.3 is a very important IEEE ethernet standard that defines the physical (PHY) layer and media access control (MAC) of the data link layer of a data network. It supports packet transmissions in the data network that uses CSMA/CD (carrier sense multiple access and collision detection) access method. Standards can be found from the following IEEE website, http://www.ieee802.org/3/

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23 There are two category definitions: one is for ethernet cable (wired), the other for user equipment (wireless in 3GPP). Here in this chapter, category cables refer to twisted pairs used for data transmission. Cat5: 100 MHz bandwidth (BW), 100Base‐T; Cat5e (enhanced): 100 MHz bandwidth (BW), 1000Base‐T; Cat6: 250 MHz BW, 1000Base‐TX; Cat6a (augmented Cat6): 500 MHz BW, 1000Base‐T (or 10GBase‐T), Cat7: BW 700 MHz, 10GBase‐T. They all have a maximum link distance of 100 meters. 24 Multi‐mode optical fiber has a larger core diameter, typically between 50 and 100 µm. The larger core has higher light‐gathering capacity, and it simplifies connection adaptor design. The optical fibers are used in long haul data transmissions; for example, 100 Mbps for distances up to 2 km, 1 Gbps for distances up to 1 km, and 10 Gbps for distances up to 550 m. 25 “Just the Technical Facts, the Real Facts About Copper Twisted‐Pair at 10 Gb/s and Beyond,” LAN‐803‐EN, Corning, August 2007. 26 “Next‐Generation High‐Speed Transport Systems for Smart Data Center and Enterprise Networking,” WP‐06, December 2008 27 FPGA was invented by Xilinx’s founder, Ross Freeman, in 1985. FPGAs are programmable semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected through programmable interconnects. As opposed to application specific integrated circuits (ASICs), where the device is custom built for the particular design, FPGAs can be programmed to achieve a desired application or functionality requirements. 28 “10GBase‐T Power Budget Summary,” Tehuti Networks, March 2007. 29 Terabit ethernet or TbE refers to ethernet networks with data rates above 100 Gbit/s. As of 2015, 400 gigabit/s ethernet are targeted, using technology similar to 100 gigabit/s ethernet. They are often realized using optical fibers. 30 Andy Tiankuan Liu, “Dara communication for future experiments,” Joint CPAD and Instrumentation Frontier Community Meeting, Argonne National Laboratory, January 11, 2013. 31 “Molex QSFP+ Active Optical Cables,” from distributor Mouser’s website: http://www. mouser.tw/new/molex/molex‐qsfp‐plus/ 32 “Broadcom® 10 GbE high‐performance adapters for Dell® powerEdge® twelfth‐ generation servers,” white paper by Broadcom, July 2013. 33 Tien‐Ching Hsu, “High‐speed, low‐power consumption, 850 nm VCSEL and monolithic Integrated PD module for the application of optical interconnect,” unpublished master’s thesis, National Central University, Taiwan, 2009. 34 D. G. Underwood, G. Drake, W. S. Fernando, R. W. Stanek, “Modulator‐based, High Bandwidth optical links for HEP experiments,” IEEE Nuclear and Plasma Sciences Society, 60(5), 2013. 35 A. Paramonov, G. Drake, R. Stanek, D. Underwood, “A new high‐speed optcal transceiver for data transmission at the LHC experiments,” ACES, 2014. 36 von Neumann architecture describes organization for an electronic digital computer with parts consisting of 1) a processor unit containing an arithmetic logic unit (ALU) and processor registers, 2) a control unit containing an instruction register and program counter, 3) a memory to store both data and instructions, external mass storage, and 4) input and output mechanisms. There are on‐chip memory and off‐chip ones. For example, SRAM cache is on‐chip memory, DRAM and/or LPDDR are off chip.

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Figure P.7 Computer architecture by Memory John von Neumann.

Control unit ALU & & program program counters registers

I/Os

It was described in 1945 by the mathematician and physicist John von Neumann and others in the First Draft of a Report on the EDVAC, after involvement in ENIAC. Both system on a board (SoB) ×86 CPUs and system on a chip (SoC) ARM processors are based on von Neumann architecture. 37 Intel ×86 chipset is based on system on a (mother)‐board (SoB). Most ×86 chipsets have PCI or PCIExpress (PCIe) buses for high performance ethernet communications. On an Intel chipset, there are 1) CPU, 2) main memory (RAM), 3) controllers (memory controller hub and I/O controller hub), and 4) I/Os for external networking. 38 “PCI Express* Ethernet Networking,” Intel white paper, 2005. 39 Bob Sullivan, Michael Rose, and Jason Boh, “Simulating High‐Speed Serial Channels with IBIS‐AMI Models,” Application Note 5990‐9111EN, Keysight Technologies, 2011‐2014. 40 Jason Boh, “Signal Integrity Simulation of PCI Express Gen 2 Channel,” XrossTalk Magazine, January 2009, also Article Reprint 5990‐3889EN, Keysight Technologies, July 31, 2014. 41 “PHY Interface for the PCI Express, SATA, and USB 3.1 Architectures,” Version 4.3, Intel 2007–2014. 42 “Universal Serial Bus 3.0 Specification,” HP, Intel, Microsoft, NEC, ST‐NXP Wireless, and TI, November 12, 2008. 43 “Modem over ISDN BRI for Cisco 3640 router,” Cisco IOS Release 12.0(3)T. 44 Jean Walrand and Pravin Varaiya, “High‐Performance Communication Networks,” Second Edition, Morgan Kaufmann, San Francisco, 2000. 45 ISDN (Integrated services digital network) basic rate interface (BRI) is composed of two B channels and one D channel for circuit‐switched communication of voice, video, and data. ISDN primary rate interface (PRI) consists of one 64‐Kbps D channel plus 23 (T1) or 30 (E1) B channels for voice or data communication. 46 Jochen Schiller, “Mobile Communications,” 2nd edition, Pearson Education Limited, Edinburgh Gate, England, 2003. 47 The Universal Mobile Telecommunications System (UMTS) is 3G mobile cellular networks based on the GSM standard. Developed and maintained by the 3GPP (Third Generation Partnership Project), UMTS is a component of the International Telecommunications Union IMT‐2000 standard set. UMTS added wideband code division multiple access (W‐CDMA) radio access technology to offer greater spectral efficiency and bandwidth to mobile network operators. UMTS specifies a complete network system, which includes the radio access network UMTS Terrestrial Radio Access Network (UTRAN), the core network (CN), and the authentication of users via SIM (subscriber identity module) cards.

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48 “The ARM Architecture,” ARM stands for Acorn RISC Machine or Advanced RISC Machine. 49 In International Consumer Electronics Show, Las Vegas, January 10, 2012, Intel announced a new system on a chip (SoC) platform designed for smartphones and tablets, so called “Intel Inside Smartphones and Tablets.” The platform would use the AtomTM line of processor. It is a continuation of the partnership announced by Intel and Google on September 13, 2011 to provide support for the Android operating systems using Intel’s AtomTM processors. Motorola Mobility has been producing Android phones under Lenovo’s management. That is, it is likely that Intel’s logo may be inside Motorola Mobility’s smartphones. Intel’s AtomTM development has been seen as a strategy to boost mobility business, since Intel’s PC market, including desktops and notebooks, has been in decline. 50 “OMAPTM 5 mobile applications platform,” TI, 2011. 51 Datasheet for TQM7M5013, a TriQuint Quad‐band GSM PA module designed to be used with the Qualcomm transceiver (QTR), RTR8600. 52 https://www.ifixit.com/Teardown/iPhone+5+Teardown/10525 53 https://www.jedec.org/category/technology‐focus‐area/ mobile‐memory‐lpddr‐wide‐io‐memory‐mcp 54 David Vye, “The economics of handset RF front‐end integration,” Microwave Journal, September 2010. 55 Generations of Qualcomm’s transceivers: http://www.anandtech.com/show/6541/ the‐state‐of‐qualcomms‐modems‐wtr1605‐and‐mdm9×25/2 56 http://www.3gpp.org/keywords‐acronyms/1612‐ue‐category 57 UTRA (UMTS Terrestrial Radio Access) is a collection of radio access upgrades from 2G GSM. Evolved‐UTRA is a new air interface (i.e., radio access) added to UTRA for being upgraded to LTE (long‐term evolution, a 4G technology). 58 https://www.qualcomm.com/products/rf 59 “Qualcomm rides LTE to Cat 10,” November 20, 2014, EETimes. 60 “Information on human exposure to radiofrequency field from cellular radio transmitters,” Office of Engineering and Technology, Federal Communications Commission, December 1994. 61 https://sites.google.com/site/changch1011/my‐blog/iPhone‐4Ss‐Smart‐Antenna 62 “Bluetooth Measurement Fundamentals,” Application Note 5988‐3760EN, Keysight, 2001. 63 In iPhone 4, a gyroscopic sensor was introduced, which detects the angular acceleration around X, Y, and Z axes. The gyroscopic sensor complements the accelerometer sensor, which detects linear acceleration along X, Y, and Z axes. The combined data from the accelerometer and the gyroscope provides detailed and precise information about the device’s 6‐axis movement in space. As a result of the detection, the screen quickly adjusts the orientation relative to the smartphone user. 64 “It’s time to kiss that removable smartphone battery goodbye,” CNET Review, February 1, 2012. 65 “Understanding Lithium‐Ion and Smart Battery Technology,” HP® Customer Support. 66 “How computers got amazing: Moore’s Law at 50,” USA Today, April 19, 2015. [Note: the Moore’s law was first appeared in Electronics published on April 19, 1965. The traitorous eight are eight men who left Shockley Semiconductor Laboratory in 1957. Shockley described their leaving as a “betrayal.” The eight who left Shockley

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Semiconductor were Julius Blank, Victor Grinich, Jean Hoerni, Eugene Kleiner, Jay Last, Gordon Moore, Robert Noyce, and Sheldon Roberts. In August 1957, they reached an agreement with Sherman Fairchild and on September 18, 1957 they formed Fairchild Semiconductor. Moore co‐founded Intel in 1968 with Robert Noyce.] 67 International Technology Roadmap for Semiconductor, 2012 Update, Overview, 2012. 68 “A break‐through in TSMC’s EUV Technology,” Chinese‐language Commercial Times (Gong Shang Shi Bao), Taipei, Taiwan, February 25, 2015. 69 “Making of a Chip” Illustrations, Intel, January 2012. 70 “IBM and Intel: the end game for IBM semiconductor,” Seeking Alpha, September 17, 2014. 71 T. Matsukawa, S. O’uchi, K. Endo, Y. Ishikawa, H. Yamauchi, Y. X. Liu, J. Tsukada, K. Sakamoto, and M. Masahara, “Comprehensive Analysis of Variability Sources of FinFET Characteristics,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 6A‐5, pp. 118‐119. 72 “Intel’s revolutionary 22 nm transistor technology,” Intel, May 2011. 73 C.‐H. Jan et al., “A 22 nm SoC platform technology featuring 3‐D tri‐gate and high‐k/ metal gate, optimized for ultra low power, high performance and high density SoC applications,” IEDM, 2012. 74 Tsu‐Jae Liu and Nuo Xu, “FinFET versus UTBB for RF/Analog Applications,” ISSCC 2013 Forum F6: Mixed‐Signal/RF Design and Modeling in Next‐Generation CMOS. 75 Bill Arnold, “Shrinking Possibilities,” IEEE Spectrum, April 1, 2009. 76 “Table ORTC‐1 ORTC Technology Trend Targets‐2013‐2020,” International Technology Roadmap for Semiconductors (ITRS), 2013. ORTC: Overall Roadmap Technology Characteristics. 77 A10 is an application processor, 64‐bit ARM SoC by Apple; it is intended to be used in iPhone 7, available on market in September 2016. 78 The URL for TSMC’s technology is http://www.tsmc.com/english/dedicatedFoundry/ technology/index.htm 79 “Volume production of ARM’s new processor by the year end by TSMC,” Chinese‐ language Liberty Times (Zi You Shi Bao), April 3, 2013. 80 http://electroiq.com/insights‐from‐leading‐edge/2012/09/ 81 http://www.statista.com/statistics/263437/ global‐smartphone‐sales‐to‐end‐users‐since‐2007/ 82 http://www.statista.com/statistics/272595/ global‐shipments‐forecast‐for‐tablets‐laptops‐and‐desktop‐pcs/ 83 “CMOSRFTransceiver in IC package supports all 2G/3G/4G modes, bands,” RF/ Microwave Tracker, March 4, 2012. 84 A6 is an application processor, 32‐bit ARM SoC by Apple; it was used in iPhone 5, available on market in September 2012. 85 BCB (benzocyclobutene) and PI (polyimide) are two often used polymeric dielectric materials in WLP thin‐film technology. They are applied in re‐distribution layers, along with electro‐plated copper. They are used because of excellent mechanical properties, such as adhesion, shrinkage, rigidity, and manufacturability (spin‐coated, photo‐ sensitive). There have been papers that reported the advantages of BCB over PI, for example, a lower dielectric constant, a lower dissipation factor, reduced water absorption, a shorter cure time and a lower cure temperature. In addition to these

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improved dielectrics properties, the coating process with BCB has been found to produce a much more planarized layer as opposed to our standard PI process. 86 2011 Intel Investor Meeting, Intel Architecture Group, Santa Clara, CA, 2011. 87 “16 GB iPhone 5 bill of materials estimated at $168,” AppleInsider, September 14, 2012. 88 Motorola Droid RAZR Teardown can be found from the following website, http://www. ifixit.com/ 89 “Altera, Xilinx to switch from TSMC CoWoS process to PoP Packaging for next‐ generation chips, says paper,” Chinese‐language Economic Daily News (EDN) reports, March 4, 2013. Trial production of Altera’s and Xilinx’s next generation FPGAs using a 20‐nm technology node and CoWoS process at TSMC failed to meet expectations. The un‐successful trial has prompted Altera and Xilinx to seek alternative packaging solutions, such as, PoP (Packaged on Package), from AES, SPIL, and Amkor. 90 Teardown reports can be accessible from the following website, http://www. chipworks.com/ 91 “Gartner Says Asia/Pacific Led Worldwide Mobile Phone Sales to Growth in First Quarter of 2013,” Press Release, Newsroom, Gartner, May 14, 2013. 92 “Worldwide mobile phone growth expected to drop to 1.4% in 2012 despite continued growth of smartphones, according to IDC,” IDC Press release, December 4, 2012. 93 “Apple, Huawei, and Xiami finish with above average year‐over‐year growth, as worldwide smartphone shipments surpass 1.4 billion for the year, according to IDC,” IDC Press Releases, January 27, 2016. 94 “AFBR‐79Q4Z, AFBR‐79Q4Z‐D InfiniBand 4× QDR QSFP Pluggable, Parallel Fiber‐ Optics Module,” Data sheet from Avago, January 28, 2013. 95 “TSMC to invest NT$ 500 billion in Taichung industry park,” Chinese‐language Apple Daily (Pin Guo Ri Bao), Taipei, Taiwan, February 7, 2015. 96 Richard Renard, “STMicroelectronics offers full foundry services for its RF IPD process,” Technical article TA0348, STMicroelectronics, November 2013. 97 “Custom Design & Manufacturing Services,” ON Semiconductor, Rev. 4, September, 2014.

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