Wafer Level Packaging Interconnects: Russ Winslow Wafer Fabrication Vs

Volume 8, Number 2

QUARTER TWO 2004

A Publication of The MicroElectronics Packaging & Test Engineering Council

INDUSTRY NEWS WaferWafer LevelLevel

ENTEGRIS, INC. has announced that IC PackagingPackaging INTERCONNECT (ICI) has joined the Ente- gris Final Manufacturing Partner program. page 14 Interconnects: STATS CHIPPAC Interconnects: and have announced the signing of a definitive agreement for the companies to merge. page 17 WaferWafer FabricationFabrication vs.vs. PackagePackage AssemblyAssembly Industries Inc OneOne DayDay TechnicalTechnical SymposiumSymposium andand ExhibitsExhibits KULICKE & SOFFA and ASE GROUP announce a strategic relationship between ComingComing toto SantaSanta ClaraClara AugustAugust 19th19th ...... pagepage 55 K&S’s Test Products Group and ASE Test Limited. page 18 MEMBER COMPANY PROFILE TECHNOLOGY ong considered one of the best kept secrets in the Dr. Young Gon Kim of Tessera reviews subcon world, NS Electron- five infrastructure barriers to SiP development for achieving time-to-market goals, ics Bangkok has developed La strong reputation for high and possible solutions to overcoming those barriers in “Solving SiP Time-to-Market quality, short cycle times, and Challenges”. page 24 excellent customer service. These attributes are the core of an Robert Rowland of RadiSys Corpora- overall strategy by NSEB manage- tion discusses components from a process ment to create a superior subcon engineer’s perspective. page 28 experience for major semiconduc- Kelly Linden and some of his colleagues tor manufacturers worldwide. from Microvision discuss “Wafer Scale Vacuum Packaging of a MEMS Optical Born from the decision of National Semi- Semiconductor equipment bookings increase Scanner”. page 30 conductor to reduce its offshore factory 70% over March 2003 level. page 18 base in the early 90’s, NSEB was purchased by local Thai investors in 1993. It is now completely independent of National. Tak- Book-Book- ing advantage of the core competence in IC assembly and test, the new management to-Billto-Bill team has developed NSEB into what may North America's largest exposition devoted be the single best medium size IC assem- RatioRatio to semiconductor equipment, materials, bly/test house in the Far East. During the services, and technology returns to San last 4 or 5 years they have been ranked as Francisco and San Jose. page 40 one of the top 5 or 6 subcons. page 20 FORFOR MARCHMARCH 1.10 1.10 www.meptec.org 1 ■ ■ metals chemicals dielectrics ■ packaging ■ optoelectronics Putting the Pieces Together

Providing the Most Complete Solutions for Your Interconnect Packaging Challenges… Honeywell is established as a prime supplier in electrical and thermal interconnect products used in the manufacture of high performance BGA and flipchip packages. Our capabilities include design, prototyping, specialized fabrication, metal finishing and high volume manufacturing. Electrical Interconnect: Evaporation & Power Products Honeywell’s core competencies include manufacture of the high-purity evaporation charges and electroplating anode products that are used for back metallization, underbump metallization and wafer bumping of flipchip die. We offer a comprehensive material set for the manufacture of high power devices. Thermal Management: Spreaders, Lids & Stiffeners Honeywell provides a wide range of thermal heat spreaders, heat slugs and stiffeners used to overcome today’s thermal management challenges. We specialize in providing novel thermal solutions for applications requiring the highest performance and tightest tolerances. Thermal Management: Thermal Interface—Phase Change Materials Our packaging science expertise allows us to address thermal management concerns at various levels within both die-to-package and package-to-system assemblies. Honeywell’s PCM45 Series materials exhibit excellent surface wetting characteristics resulting in low contact resistance, but do not degrade with use. Putting Together Added Value— Combo-Spreader™ with Pre-attached Phase Change Material Available only from Honeywell, the Combo-Spreader is an innovative solution for today’s advanced thermal challenges. By combining the benchmark thermal performance of PCM45 with our industry leading thermal spreaders, we provide a lasting solution well ahead of the ITRS roadmap, with fewer production steps required. Our expertise in materials science, metallurgy and chemistry enables Honeywell to provide solutions to your interconnect packaging needs at a reduced cost of ownership…from layer one to package done.™

www.electronicmaterials.com © 2004 Honeywell International Inc. All rights reserved. Combo-Spreader 408-962-2055 and “From Layer One to Package Done” are trademarks of Honeywell International Inc. MEPTEC Council Update

Volume 8, Number 2 A Publication of The MicroElectronics Packaging & Test Engineering Council 801 W. El Camino Real, No. 258 Mountain View, CA 94040 Tel: (650) 988-7125 Fax: (650) 962-8684 Email: [email protected] Published By MEPCOM Editor Bette Cooper Design and Production Gary Brown Advertising Mica Jones Marketing –––––––––––––– MEPTEC Advisory Board Phil Marcoux MEPTEC Executive Director Seth Alavi Sunsil t’s that time again, SEMICON West, Our feature articles and even our edito- John Bubello when thousands converge on San rial this issue reflect some of the topics Advanced Packaging Magazine Joel Camarda Francisco and San Jose to see the from our events over the last year. Starting Kullike & Soffa latest and greatest technology in the chronologically, we have a contribution Gary Catlin semiconductor industry. In this col- from one of our presenters from our Aug- Mulichip Assembly Rob Cole Iumn last year the question arose about ust 2003 “Where the Components Meets FICO America how a big event like SEMICON West the Board” symposium, Robert Rowland John Crane would fare in face of the many challenges of RadiSys Corporation. Rob discusses J. H. Crane & Associates Jeffery C. Demmin our industry was facing such as the eco- components from a process engineer’s Tessera nomic downturn, continued travel restric- perspective. See his article on page 28. Mark DiOrio tions and concerns, and SARS. We’re Next we take a look at “Solving SiP MTBSolutions, Inc. Bruce Euzent pleased to see that in the year since then, Time-to-Market Challenges” (see page Altera Corporation things have improved dramatically. We 24) that grew out of our “SiPs or SoCs” Skip Fehr like to think that the worst is behind, and event, from Dr. Young Gon Kim of Tes- Chip Greely Qualcomm the best is yet to come. sera. Dr. Kim reviews five infrastructure Anna Gualtieri Also in this column last year we talked barriers to SiP development for achieving SPEL about MEPTEC’s success with our quar- time-to-market goals, and possible solu- Bance Hom Consultech International, Inc. terly technical symposiums, and we’re tions to overcoming those barriers. He Ron Jones pleased to report that the success is con- concludes by predicting “the SiP solution N-Able Group International tinuing. Since July of last year we held has a high potential and will impact the Pat Kennedy GEL-PAK an event in August 2003 on “Where the semiconductor significantly in the next Nick Leonardi Component Meets the Board: Package Dynaloy, Inc. Reliability Issues and Challenges”; in Abhay Maheshwari Issue Highlights Xilinx November we looked at “Packaging Mary Olsson Industry Roadmaps: Overcoming Obsta- From The Director page 4 Dataquest cles and Navigating Solutions”; in Feb- Marc Papageorge ruary it was “SiPs or SoCs? The Multi MEPTEC Events Follow-up page 6 Doug Pecchenino Million Dollar Question”; and in May we Ray Petit University News page 11 Pacific Rim Technology covered “MEMS and Wafer Level Pack- Jerry Secrest aging: Converging Technologies”. Our Industry News page 14 Secrest Research next event will be on August 19, 2004 on Jim Walker Member Company Profile page 20 Dataquest “Wafer Level Packaging Interconnects: Russ Winslow Wafer Fabrication vs. Package Assem- Feature Articles Six Sigma –––––––––––––– bly” (see page 5 for registration informa- • Solving SiP Time-to-Market Bob Hilton tion). In addition, we added a new event 1945 – 2003 Challenges page 24 –––––––––––––– – this time a non-technical, financial-ori- • Components: A Process MEPTEC Report Vol. 8, No. 2. Published quarterly by ented conference called “Interconnections MEPCOM, 801 W. El Camino Real, Mountain View, CA Engineer’s Perspective page 28 94040. Copyright 2004 by MEPTEC/MEPCOM. All rights Investors Conference”. The five MEPTEC reserved. Materials may not be reproduced in whole or in events since July of last year drew over • Wafer Scale Vacuum part without written permission. 1,000 attendees. We’re pleased to be able Packaging of a MEMS MEPTEC Report is sent without charge to members of page 30 MEPTEC. For non-members, yearly subscriptions are to continue to bring these excellent pro- Optical Scanner available for $75 in the United States, $80US in Canada and grams to the professional community. For Mexico, and $95US elsewhere. Calendar page 41 summaries and updates on a few of these For advertising rates and information contact Mica Jones, Advertising Sales at (925) 846-0115, Fax (925) 846-0266. events check out our MEPTEC Events Editorial page 42 Follow-up section starting on page 6. www.meptec.org 3 MEPTEC REPORT / QUARTER TWO 2004 From The Director continued from page 3 five years”. Our third contribution is from Kelly Linden and some of his col- The Interconnections leagues from Microvision from our “MEMS and Wafer Level Packag- ing” symposium on “Wafer Scale Investors Conference Vac-uum Packaging of a MEMS Optical Scanner” (see page 30). The was a success! packaging of MEMS (micro-elec- trome-chanical systems) is, in their words, “a critical challenge in creating a technically and commercially viable device”. Microvision’s work n May 12, eighty-five attendees conductor industry that will affect our on wafer scale vacuum packages and speakers gathered to dis- portion. shows it is definitely a feasible tech- cuss the financial outlook for the I’m very appreciative of Eric Gom- nology. semiconductor assembly and test berg’s time and presentation. Eric traveled Our editorial this issue is a contri- O bution from one of our session lead- services industry, or SATS companies. from NY, specifically Wall Street. Eric, The SATS Companies, also known as Senior Analyst with Thomas Weisel Part- ers at our “SiPs or SoCs” sympo- the “Backend Packagers and Testers”, cur- ners, is one of the first analysts to cover sium, and MEPTEC member, Mark rently are the fastest growing in the semi- our area, and he coined the term SATS. Hartung of Chip Supply, Inc. with conductor industry. Yet SATS companies Eric provided an historical perspective “Everybody’s talking ‘bout the new have very little investor visibility, much and its potential for growth. sound, funny, but it’s still rock and as the EMS companies had in the early Our keynote speaker, Satya Chillara, roll to me…” (see page 42). His 1990’s. Material, IP, and other semicon- is a former MEPTEC member and has reference to singer/songwriter Billy ductor interconnection companies are en- successfully made the jump from the tech- Joel’s hit from the 80s is a good joying equally strong growth and market nical to the financial. He recently joined analogy to explain the debate about demand. RBC Capital, an IIC sponsor and a large multi-die packaging. It’s an interest- MEPTEC’s Executive Level Members investment-banking firm that, along with ing take on what Mark calls “déjà vu and some key industry analysts want to the firms of our other analysts, were re- all over again”! help change this financial situation. As sponsible for a significant amount of the We’re pleased to highlight in our the SATS and other semiconductor inter- greater than ten fold market value increase Member Company Profile this issue connection companies are pressured to of the EMS companies. NS Electronics Bangkok, a longtime start expanding and looking for expansion Several event sponsors supported this Corporate member of MEPTEC. As money, they to want their financial picture conference. I would like to thank them for they state, they are “long considered to change. helping make this event successful and one of the best kept secrets in the The goal of this Conference was to pleasurable. Our 2004 IIC sponsors in- subcon world”. They point out that as-semble several informative speakers cluded Dow Chemical, RBC Capital Mar- a very important factor of their suc- and high market potential companies. Our kets, W R Hambrecht + Co, Gartner-Data- cess lies in one of their most impor- speakers were leading industry analysts, quest, KMZ Rosenman, and Advanced tant assets, their employees. Their publicly traded and late stage established Packaging and SMT Magazines. high quality in all facets of their SATS and Interconnection Companies. I I want to particularly thank several operations, from their people to their would like to extend a thank you to the people who put forth significant effort equipment to their customer service, Showcase Presenter Companies at this for this event. Thank you to Kim Barber, truly makes them a winner. See their inaugural event – ASAT, STATS, Chip- MEPTEC Executive Level Event Manag- story on page 20. Pac, PSI Technologies, Ultratera, UTAC, er; Marc Papageorge of SOS and Charles Our University News section Am-kor and ASE. I especially commend DiLisio of D-Side Advisors, members of this issue introduces the University them for their adherence to our challenge the IIC Advisory Board; Doug Molitor of Maryland and its Nanoelectron- of only ten minutes to present their corpo- and Steve Begley who helped prepare ics Research Group. They’re doing rate story. our Showcase Presenters; and Jim Walker some fascinating and ground-break- The financial analysts were topnotch. of Gartner-Dataquest who prompted the ing technology there with their Jim Walker, a VP of Gartner-Dataquest original concept. I also want to extend a research on semiconductor carbon and one of the inspirations for this event thank you to Hans Sevierns. Hans was nanotubes that have been found to provided an in-depth review of the market a very forceful supporter of this event have the highest mobility of any drivers for the SATS industry. Charles right up to his passing in February of this known material at room temperature. DiLisio of D-Side Advisors who discussed year. This re-search could effectively revo- the value opportunity for SATS followed ◆ lutionize the semiconductor materials him. in-dustry. See their story on page 11. Lucas Ward recently joined one of We’d like to thank all of our con- our IIC sponsors, WR Hambrecht + Co, tributors for making this a great is- leaving a comfortable family life in Italy. Phil Marcoux sue. If you’re reading our publication Lucas provided a broader view of some Executive Director for the first time at the SEMICON of the larger trends occurring in the semi- MEPTEC West show we hope you enjoy it. www.meptec.org 4 MEPTEC REPORT / QUARTER TWO 2004 MEPTECPresents MicroElectronics Packaging and Test Engineering Council

A ONE-DAY TECHNICAL SYMPOSIUM & EXHIBITS

August 19, 2004 • The Westin Santa Clara, Santa Clara, CA • 8:30 a.m. - 5:00 p.m. Table Top Exhibits 11:00 a.m. - 7:00 p.m. • Reception 5:00 p.m. - 7:00 p.m. Wafer Level Packaging Interconnects: Wafer Fabrication vs. Package Assembly

n the quest for smaller size, increased perfor- solutions-oriented event with session topics being mance and lower cost, the semiconductor indus- covered in brief presentations by experts, followed try is rapidly migrating towards a “packageless” by interactive question and an-swer panel sessions. package, commonly referred to as Wafer Level Invited speakers at this focused symposium will share IPack-aging (WLP). Markets that require small form their wealth of knowledge in various areas of WLP factor, such as hand held and portable devices, are technology. This symposium is a must for all the seen as the volume drivers for WLP, but WLP should executives, managers, engineers and other decision expand to other applications as the technologies are makers who wish to improve the cost / performance developed. By definition, WLP consists of intercon- of their products and have the opportunity to network nections made at the wafer level. With WLP typically within the industry. yielding the highest cost vs. performance advantage for interconnection of devices to substrate materials, Symposium Co-Chairs: the potential efficiencies gained in the WLP testing Nicholas Leonardi, President, TechDirect are seen as a bonus to utilization of these technolo- Rob Cole, Area Manager, North America gies. The question is not whether WLP will continue BE Semiconductor Industries to build upon its current momentum in the industry; that is a given. Rather, where will it be done? Is WLP Sessions will include: a part of wafer fabrication or a package assembly? REGISTER The answer de-pends on the specific WLP technology ■ Applications Driving Wafer Level Packaging NOW! chosen since some manufacturing processes can be Session Chair: Dr. Tom Di Stefano, President To register by phone, easily streamlined into the wafer fabrication process Centipede Systems oror forfor moremore informationinformation while others may be more effectively done as part of ■ Wafer Level Packaging Equipment and aboutabout thisthis andand otherother assembly. Processes MEPTEC events, contact During the two years since the previous MEPTEC Session Chair: Dr. Vivek Dutta, President Bette Cooper at conference on WLP, development and implementa- Advenient Technology 650-988-7125,650-988-7125, emailemail tion of WLP has continued and current industry growth is adding momentum to the area of WLP ■ Wafer Level Packaging Test and Burn-in [email protected]@meptec.org oror Session Chair: Leonette Stafford, Chapter visitvisit thethe MEPTECMEPTEC webweb-- manufacturing, making another symposium very timely. The objective of this conference is to address President, American Society of Test Engineers site.site. WLP technologies and convergence of wafer fabrica- ■ Wafer level Packaging: Strategies for Industry tion and package assembly. This will be a fast-moving, Collaboration Ask Us About Exhibiting at This Event! Pre-registration only, please. Space will be limited!

EVENT SPONSORS

® circuitnet International Wafer-Level Packaging Congress Join Us! Register online at www.meptec.org MEPTEC Events Follow-up

packaging by reminding people about how rather than relying on a single large market or the plastic lid with a hole in top of it increases customer. the value of a cup of coffee. Packaging needs As many speakers noted, obtaining known to add value to semiconductor devices while good die (KGD) remains an issue for SiPs. providing profit to the SATS industry. The Jan Vardaman (TechSearch International) key to success, according to DiLisio, is to mentioned the graveyard of defunct MCM focus on value and profit rather than volume companies and noted that many challenges and cost, and one opportunity for SATS com- are the same as they were ten years ago. Phil panies to add value to the supply chain may Marcoux (MEPTEC) asked panelists what be SiPs. DiLisio warned that packaging needs has changed in the past ten years to enable to “get out from under the wheel” of Moore’s SiP to succeed where MCM could not. Jim Law by moving from supplying a service to Rates (Chip Supply) said perhaps not much providing a product. If the IC vendor becomes has changed: “The good news is our mature a supplier to SATS companies instead of the die don’t require burn-in, the bad news is we other way around, SATS can prosper. DiLisio don’t have any mature die.” Intel does, how- also noted that SiP is an opportunity for EMS ever, provide legacy products that are fairly companies as well, who might take business close to being KGD. Larry Gilg (Bare Die Contributed by away from the SATS companies. Consortium) commented that test methods Julia Goldstein, Technical Editor Advanced Packaging Magazine Jim Walker (Gartner Dataquest) discussed have improved, and structural test may allow SiP versus SOC, and other speakers made use of die that have not been burned in. The “SiPs or SOCs? The Multi-Million Dol- similar observations throughout the day. Im- problem remains that semiconductor manu- lar Question” was an appropriate title for portant advantages of SiP are shorter time to facturers prefer to sell packaged die and will MEPTEC’s February 19 Symposium, be- market, lower cost and ease of combining only sell bare die at a price equal to or greater cause the answer depends on economics more mixed technologies, for example Si and GaAs than that of the packaged die. One solution is than technology. Symposium Chair George or analog and digital. SOC can provide higher to use CSPs within modules (stacked pack- Brathwaite (STATS) introduced the topic performance, smaller form factor and longer ages instead of stacked die). by explaining that the supply chain needs product lifecycles. Walker predicted that SiPs If SiPs can create value for the customer to address cost, convergence and shortened will make up 10 percent of all packages by independent of die cost, for example by product lifecycles and asking, “Is SiP here to the end of 2005. reducing footprint, they may still make money stay or is it a flash in the pan?” There was dis- Design cost is an important issue, par- for the SiP manufacturer. The question of cussion about the definition of SiP, with most ticularly for SOC solutions, requiring a $1B whether SiPs can be a money-making oppor- agreeing that stacked memory alone does not market to effectively amortize the cost. Morry tunity for SATS companies depends on their make a SiP, and that a SiP must include pas- Marshall (Semico Research) presented SiP business model, which may need to change sive components (embedded or discrete) as as a great opportunity for unit volume in the to be more like that of the EMS providers. well as semiconductor die. range of 100K to 10M, with SOC feasible ◆ Keynote speaker Charles DiLisio (D-Side only for very high volumes. DiLisio’s sug- Advisors) emphasized the importance of gestion was to go after multiple niche markets

grow-th rate of 25-30%. MEMS devices are When it comes to packaging MEMS, the being used today in high volume applications lines between the front-end and the back-end such as accelerometers, gyroscopes, digital of the industry become increasingly blurred. light processors (DLP), and printers. But this Many people believe that a partnership be- does not mean that all MEMS are yet con- tween the front-end and back-end is the most sidered mainstream or fully commercialized. successful route in merging MEMS and WLP. One reason for that may be the issues related Hom is one of those people. “With packaging to packaging MEMS devices. Many people in becoming one of the biggest challenges for the in-dustry believe that Wafer Level Pack- MEMS,” she says, “it becomes a natural mi- aging (WLP) is the ideal technology to deal gration in the US for packaging profession- with those packaging issues. als to find new challenges in this emerging To discuss the issues related to the con- MEMS field. In my own personal experience vergence of MEMS and WLP, MEPTEC and expertise, plating, which has traditionally brought some of the most prestigious names been a back-end operation in IC packaging, in the MEMS business together for a one-day has migrated into the IC front-end (Dama- technical symposium in May. Some of the scene Process) and is now fully integrated speakers from the conference offered their into the MEMS front-end fulfilling purposes Contributed by Jody Mahaffey, JDM Resources insights into the quickly changing world of as functional device designs, sacrificial lay- MEMS and WLP. ers, etch resist and eutectic gold/tin layers If you’ve been reading the trade-press these Long-time industry consultant Bance Hom for wafer bonding/lid seal operations. It also past couple months, you may think that acted as Symposium Chair for the MEPTEC be-came a priority for MEMS technologists to MEMS (MicroElectroMechnical Systems) is conference. She believes that there are so have a fundamental understanding of packag- one of the hottest topics in the industry today. many common skill sets and cross-linking ing technology to design and sync up their It’s been reported by varying sources that packaging technologies that are easily trans- devices to the outside world in a more cost ef- MEMS revenues are forecast to increase at lated bilaterally into both arenas, it seems fective and reliable mode. Wafer level pack- a compound annual growth rate of 15-20% obvious that tying the common links together aging becomes a key enabling technology as over the next few years, while units shipped will enhance the progression and agendas for packaging and fabs converge together.” are forecast to grow at a compound annual both technologies. Whether it is MEMS companies adding www.meptec.org 6 MEPTEC REPORT / QUARTER TWO 2004 MEPTEC Events Follow-up

packaging people, or through partnerships with model for most new companies. It is difficult for ized. Cost and a lack of standardization (which back-end companies, most experts agree that the new MEMS startup to tackle the packaging. affects cost) were common answers regarding packaging MEMS at the wafer level is a front- While it may be an enabling technology, investors non-technical issues. end responsibility. John Heck, Senior Engineer, no longer have the stomach to invest in the capital Joe Brown of SUSS MicroTec believes, “The MEMS & Packaging for Intel Corporation and infrastructure necessary to bring it up in-house. most significant non-technical issue is cost. This Session Chair for the Enabling Technologies The cost of development and implementation can in many ways relate to other issues such as Session of the conference, believes that merging must be amortized over the company’s specific standards but it usually comes back to cost. Most MEMS and WLP should fall to the front-end product line. In contrast, the foundries can lever- MEMS today are commodity products used in because there are critical steps which must be age their infrastructure and development costs cost sensitive markets such as automotive and done in a clean room, and because the handling over many customers and product lines. It just consumer electronics. In many ways cost adders of MEMS wafers should be minimized with the makes better financial sense.” to provide wafer level packaging must be targeted fragile devices exposed. Flannery adds, “It is also doubtful that wafer at pennies per die.” Joe Brown, MEMS Director at SUSS Micro- level integration will be successfully addressed at With respect to commercialization, Brown Tec, whose company presented in the Enabling the packaging level. The infrastructure does not adds, “Fully commercialized would infer the 800 Technologies Session, agrees with Heck saying, exist there. The level of precision and control lb. gorillas have accepted this path for technology. “For the most part MEMS have been front-end is greater than what they or their infrastructure Here standards and other key elements for cost process centered and for this reason have suffered is used to dealing with. And perhaps most impor- reduction are needed to fully realize the potential by lacking advanced packaging solutions. With tantly, many times the wafer level integration of MEMS and WLP.” packaging integrated by front-end processing step is not the last. Additional MEMS processing John Heck of Intel says, “I believe the lack (prior to CMOS) MEMS can take a big step must be done. That would mean it would have of standard, commoditized wafer level packag- toward meeting cost targets by utilizing novel to go back to the MEMS foundry which smacks ing materials is the biggest problem to address. processing techniques.” of inefficiency and the possibility for errors and Every MEMS company is forced to develop their Anthony Flannery, Director of Development, contamination.” own proprietary solution for packaging MEMS MEMS Gyroscope for Invensense, was a speaker So assuming the answer to MEMS packaging at the wafer level since there are no standardized in the Assembly Processes Session of the confer- is WLP and that this is a front-end responsibility, processes.” ence. Flannery believes that Wafer Level Inte- we asked our expert speakers what they believed “Cost is clearly one of the most significant gration, the term he prefers over WLP, must were the most significant technical and non- issues,” agrees David Fork, Principal Scientist absolutely be addressed by the MEMS foundry. technical issues facing the integration of MEMS with the Palo Alto Research Center who pre- According to Flannery, “The trend in the de-vices and Wafer Level Packaging and possibly sented in the Assembly Processes Session. “Wafer MEMS industry is moving towards a fabless holding them back from being fully commercial- level packaging has the potential to lower cost in

www.meptec.org 8 MEPTEC REPORT / QUARTER TWO 2004 MEPTEC Events Follow-up

comparison to conventional packages, but this issue for all MEMS devices and that wafer level panies have developed to help solve some of the will require a large application in volume produc- packaging may be just the solution. issues relating to the integration of MEMS and tion in order to achieve the economy of scale Dr. Marc Madou, Professor of Biomedical WLP. But they all agree that even as new solu- possible with batch fabrication.” Engineering and Integrated Nanosystems Re- tions are developed, there are still many issues According to some, cost isn’t the only issue to search at UC Irvine gave the keynote address at that need to be addressed before MEMS can be- be considered. Anthony Flannery of Invensense the conference. Dr. Madou says there is just too come fully commercialized. believes that available infrastructure in the areas much variability from one MEMS device to an- “They (MEMS) will become mainstream of equipment and training is a critical issue for other to come up with one overall strategy that when they get into the typical conventional com- the convergence of MEMS and WLP. “Because works for everything. puter industry, which will be in communication of the (justifiable) reluctance of MEMS foundries Flannery agrees, “I don’t see any major tech- – RF MEMS,” states John Heck. to spend on anything that looks like capital invest- nical issues. Many different bonding technologies Dr. Madou feels, “Only consumer applica- ment, there is a shortage of places MEMS compa- have been demonstrated in the last several years. tions really make MEMS worthwhile in the long nies can go to get wafer level packaging services, They all have their own challenges and strengths, run.” and when they do exist, there is a usually a lack but I don’t believe there are any show-stoppers.” “If we can figure out ways to lower cost,” of breadth or understanding on the part of the Along with the potential problems and pit- adds David Fork, “there would be more MEMS foundry. All the technical pieces exist out there falls, there are also some real advantages to applications and larger sales volumes, bringing it (bonders, plating setups, wafer aligners, etc.) but integrating MEMS and WLP. Most of the speak- closer to becoming fully commercialized. There it is up to the foundry to put it together. Right now ers agreed that cost can be one of the biggest are many more novel processes and approaches that has been lagging.” advantages. John Heck of Intel feels that parallel than the current infrastructures can support. Only As far as technical issues are concerned, the packaging of all devices on the wafer at once will some will be adopted. Sorting this out will take answers are wide ranging. Joe Brown of SUSS re-duce packaging cost dramatically. In addition, time and a mixture of success and failure.” believes, “The most significant technical issue is sealing delicate MEMS devices in the cleanroom Ultimately, the goal of the MEPTEC confer- to be able to provide "0" level packaging with her- will increase yield significantly which ultimately ence was to address some of these issues and metic sealing, maintaining vacuum < 1 x 10 -3 or reduces cost. begin discussions on some of the remaining ones controlled environments with 99.999% accuracy Dr. Madou explains, “It is obvious that if we so that MEMS and WLP can help each other get for 10 years, having electrical feed thru, with high succeed to make more of the back-end processes to a fully commercialized stage. yield of >95%.” front-end, we will drive costs down. We will also To learn more about upcoming MEPTEC David Fork of Palo Alto Research Center save space/volume and materials.” technical symposiums, as well as past symposium be-lieves the protection of fragile MEMS com- Most of the speakers at the May 11th confer- proceedings now available on CD, visit MEPTEC ponents at the dicing step is a critical technical ence discussed new technology that their com- at www.meptec.org. ◆

We Have Complete Solutions for All Your IC Packaging Requirements. Look to NTK Technologies, a world leader To find out how we can help you, please in semiconductor substrates and pack- visit our web site at www.ntktech.com or ages, for your most contact an NTK sales demanding require- office today. ments. Let us prove that Our ceramic we have solutions to components span the simplify even your gamut from ceramic most complex pack- PGAs and flip chips, aging tasks. to lead-less chip carri- Ceramic Flip-Chip LGA and PGA Organic Flip-Chip LGA ers and low-temperature co-fired ceramics.

Phoenix, San Diego, San Jose, Chicago, Boston, Richardson, Arizona California California Illinois Massachusetts Texas 602/470-9898 858/521-0545 408/727-5180 847/788-9795 508/820-0220 972/235-1625 www.meptec.org 9 MEPTEC REPORT / QUARTER TWO 2004 MEPTEC Events Follow-up

oversupply, stating that the increase in capex Similarly, ChipPAC/STATS will work on Positive pictures of comes from a low base because of decreased selling assembly services to STATS’ test cus- spending in recent years. Both Satya Chillara tomers. the SATS market (RBC Capital) and Ward noted that the ex- Analyst presentations tend to focus on the presented at MEPTEC pected ratio of capex to revenue was in a top tier SATS companies, but many smaller healthy 18 to 23 percent range, suggesting companies are doing well in their niches. conference that overcapacity would not be a problem. Another upcoming merger is that of UltraTera The increased trend in outsourcing is a and UTAC in the area of memory test services. Julia Goldstein, Technical Editor significant driver in the growth of the SATS Jack Snyder described UTAC as “test-centric Advanced Packaging Magazine market. Eric Gomberg (Thomas Weisel Part- and proud of it,” and expects that the merger MEPTEC is expanding beyond its traditional ners), who coined the acronym ‘SATS’ for will allow them to expand their product offer- audience of Semiconductor Assembly and this market, noted that this outsourcing trend ings. PSi Technologies, focused ex-clusively Test (SATS) engineers. Last year, it intro- needs to be demonstrated to analysts before on the power semiconductor market, stands duc-ed executive level membership (ELM) Wall Street will look kindly on SATS com- to benefit from growing demand for power to reach out to top decision-makers in the panies. Investors will also react positively to devices. Jim Knapp discussed transfer of ON SATS community. On May 12, MEPTEC in-creases in R&D spending, such as Amkor’s Semiconductor’s technology into PSi and held its first Interconnect Investors Confer- recent announcement. expanding PSi’s line of QFN packages. ence. MEPTEC Executive Director Phil Mar- Robert Krakauer from ChipPAC, and While the analysts presented overall posi- coux was delighted to present “the world’s Drew Davies and George Brathwaite of tive pictures of the SATS market for the next most knowledgeable collection of analysts” at STATS, discussed the upcoming ChipPAC/ one to two years and many SATS companies the conference, as well as presentations from STATS merger, due to be completed in June. are thriving, wafer-level packaging (WLP) large and small SATS companies. Krakauer described it as a “most perfect” fit was mentioned as a threat to the survival of There was some debate over how to view because of the minimal overlap in customer SATS companies. It is possible to envision the forecast increases in capital expenditures base and geographical footprint between the a future in which manufacturing goes from (capex). Jim Walker (Gartner Dataquest) ex- two companies. Once the merger is complete, wafer fabrication, including WLP processes, pressed concern about capex going too high one goal of the combined company is to iden- directly to board assembly, squeezing out the in 2004 and then crashing in 2005 or 2006, tify cross-revenue synergies, with the goal of packaging houses. It will be interesting to see similar to what happened in 2001 after an 84 increasing the percentage of ChipPAC’s as- what a SATS investor conference looks like a percent growth in capex during 2000. Lucas sembly customers who also use the company few years from now. ◆ Ward (WR Hambrecht) wasn’t worried about for test services from 45 to 75 or 80 percent.

UltraTera Corporation Stack-Die Assembly Solutions

System in Package

Si DRAM Stack

Elastomer Spacer ~2 mil Film

Multiple Any-Size Die Stacking UltraTera Corporation (UTC) has developed a patented portfolio of materials and processes that enables the thinnest multi-die stacking wire-bonded solutions. The die- attach material is selectively applied with our 3D stencil-printing process, while the die stack is encapsulated with traditional molding automated equipment and materials. UltraTera stack-die/SiP portfolio includes the unique capability to stack on top of silicon dice with centerline of bond pads, enabling compelling solutions for SiP with standard DRAM components. UltraTera provides full in-house package development and volume production, including laminate substrate design services. • Flexibility in stacking order, easier routing • Thinnest spacing between dice • In-house wafer thinning capability to 50µm • Low profile wire bonding • Unlimited overhang capability

Taiwan Headquarters California Office Korea - Seoul Office No.2 Li Hsin Road 3, Science-Based Ind. Park 46848 Lakeview Boulevard 601, #945-15, Janghak Foundation Bldg., Daechi-Dong Hsinchu, Taiwan, ROC Fremont, CA 94538 Gangnam-Gu, Seoul, Korea Mr. Sam Au Mr. Emilio Salvioni Mr. Anthony Roh +886 3 578-8780 x6610 510 354-6683 +82 2 557-4277 [email protected] [email protected] [email protected] Enabling GHz Technologies University News University of Maryland Physicists Show Nanotubes are Best Semiconductors Lee Tune, Senior Media Relations Associate, Science and Technology and Michael S. Fuhrer, Assistant Professor, Department of Physics and Center for Superconductivity Research University of Maryland at College Park

he University of Maryland’s The University of Maryland's first "smart building" is the soon to be completed Jeong H. Kim Nanoelectronics Research Engineering and Applied Sciences Building. This innovative and interactive building will be Group recently found that home to education and research in information technology, bioengineering, microelectronics semiconducting carbon nano- and MEMS, sensors and actuators, environmental engineering, transportation systems and tubes have the highest mobil- space research. Tity of any known material at room temperature. Mobility is a measure of how says. well a semiconductor conducts electric- Fuhrer’s group, in research support- ity. The finding provides new evidence ed by the National Science Foundation, that semiconducting carbon nanotubes found that the mobility of their carbon hold great promise for replacing conven- nanotube exceeds 100,000 square-cen- tional semiconductor materials in appli- timeters per volt-second at room tem- cations ranging from computer chips to perature. Mobility is the conductivity biochemical sensors. of a material divided by the number of The group, led by Michael Fuhrer, charges, which carry the current, and assistant professor of physics in the uni- is the number typically used to com- versity’s Center for Superconductivity pare the conduction properties of one Research, fabricated a semiconducting Students work in the Maryland MEMS lab on a university-developed polymer biochip that semiconductor to another. The previous nanotube transistor that shows a mobility contains thousands of microchannels for record for room temperature mobility almost 25 percent higher than any previ- analyzing protein signatures. was 77,000 square-centimeters per volt- ous semiconducting material and more second in indium antimonide and was than 70 times higher than the mobility ogy requirements, says that a replace- first measured in 1955. The mobility in of the silicon used in today’s computer ment material for silicon with higher mo- the silicon used to make today’s com- chips. These record-breaking results, bility will be necessary by the year 2010. puter chips is only about 1,500 square- which were published in the journal According to Fuhrer, the new findings by centimeters per volt-second. Nano Letters in December, have attracted he and his colleagues indicate nanotubes To perform their measurements, the wide attention. could fill that role. team had to prepare extremely long “This was the first measurement of “It’s true that many challenges remain nanotubes, and be able to place metal the intrinsic conduction properties of before nanotubes can be used instead wires precisely on one single nanotube. semiconducting nanotubes,” says Fuhrer, of silicon in computer chips,” notes They synthesized nanotubes with lengths assistant professor of physics in the uni- Fuhrer. “The contact resistance between up to 0.3 millimeters, or about 100,000 versity’s Center for Superconductivity nanotube and metal electrodes must be times the nanotubes’ diameter. This is Research. “It is an important step for- controlled. Nanotube batches must be some 100 times longer than nanotubes ward in efforts to develop nanotubes into prepared that contain only semiconduct- previously studied in electronic mea- the building blocks of a new generation ing nanotubes. And nanotubes must be surements. The nanotubes were grown of smaller, more powerful electronics.” placed with precision on substrates.” directly on flat silicon chips. A spe- The International Technology Road- However, significant progress is tak- cial technique using a scanning electron map for Semiconductors, an assessment ing place in all these areas, and the chal- microscope had to be developed in order of the semiconductor industry’s technol- lenges do not seem insurmountable,” he to locate the nanotubes on the chip so www.meptec.org 11 MEPTEC REPORT / QUARTER TWO 2004 University News

University of Maryland researchers have shown that semiconducting carbon nanotubes are the best known semiconducting material at room temperature. Carbon nanotube transistors, like those shown here, were used to make a memory cell that stores a bit of information in a single electron. One trillion of these nanotube transistors could fit on a 1 cm2 chip, storing 100 gigabytes of information, or about 100 times the Encyclopedia Britannica. Above are micrographs of the actual device in the accompanying box.

that wires could be connected to them. chemical sensors made from nanotubes ity Re-search (CSR) at the University of Carbon nanotubes can be thought of could detect a single molecule of a target Maryland. The center conducts interdis- as a single atom-thick sheet of graphite, compound. ciplinary research in the fields of super- rolled into a seamless cylinder. Nano- Fuhrer’s Nanoelectronics Research conductivity, magnetism, ferroelectricity, tubes were discovered in 1991 by Sumio Group focuses on several different as- quantum computation, nanoscale elec- Iiijima (NEC, Japan), and since then pects of nanoscale electronics. The unify- tronics, the synthesis of advanced elec- have been the subject of research around ing theme is the use of “pre-assembled” tronic materials, and the development of the world. Today nearly every major re- nanoscale components to build structures, scanning probe microscopes. Center research university has at least one group which are useful for studying the funda- search impacts technology in areas such studying carbon nanotubes. mental physics of electrons or pho-nons as communications, digital and analog Nanotubes are being considered for (lattice vibrations) in small structures, electronics, medical instrumentation, and many applications in electronic devices and also are likely to lead the way to new computers. including field-effect transistors, memory technologically relevant devices. “Pre- CSR is one of many centers at the cells, and chemical and biochemical sen- assembled” means materials, which are University of Maryland bringing togeth- sors. In each of these applications mo- made using macroscopic techniques but er researchers from numerous areas bility is the key to how well the device are naturally structured at the nano-meter (physics, engineering, computer sci- can perform. Mobility dictates how fast scale in one or more dimensions. As an ence, materials science, mathematics, the charges move through a device, so it example, consider the mineral mica: this etc.) to conduct research at both micro determines the ultimate speed of a tran- naturally occurring layered material may and nano scales. Other university units sistor. be cleaved (peeled apart) using ordinary leading this research include the Insti- Mobility also determines the change Scotch tape to obtain nearly atomically tute for Re-search in Electronics and in conductivity that is caused by a nearby flat pieces which are only a few nanome- Applied Phy-sics, the Materials Science electrical charge. Thus, mobility also is a ters thick. and Engineering Research Center, Insti- measure of the sensitivity of a transistor Research in the group combines these tute for Ad-vanced Computer Studies, for detecting charge (as in a memory pre-assembled nanoscale materials with the Small Smart Systems Center and cell) or detecting a nearby molecule (as state-of-the-art lithography and analysis the Micro El-ectro Mechanical Systems in a chemical or biochemical sensor). tools to build and study new nanoscale Lab. And like the nanotube research of Fuhrer’s group demonstrated last year electronic and electromechanical de- Fuhrer and his colleagues, the advances that high-mobility semiconducting nano- vices. being developed in these units promise to tube transistors could detect single elec- Fuhrer’s nanoelectronics group is help shape a new future for electronics. trons in a memory cell. This suggests that part of the Center for Superconductiv- ◆ www.meptec.org 12 MEPTEC REPORT / QUARTER TWO 2004 Industry News

Mr. Charbonnet has over 25 years of en- service provider, has announced a formal gineering, marketing, and sales experience agreement with Ferrian Sales & Associates in the high-tech arena, most recently as the (FSA), a manufacturer’s representative firm, head of Marketing with NewsStand Inc., a to act as Maxtek’s agent in the Midwestern digital publishing startup. United States. Hume Integration Software specializes “As representatives of a variety of manu- in developing software for Network Inte- facturers, our success is directly dependent grated Manufacturing in the semiconductor, upon our ability to select partners who flat-panel display, and electronic industries. complement our current offerings and aid us Hume software enables new levels of inte- in meeting the needs of our customers,” said gration efficiency, flexibility, and reliability. Greg Ferrian, president, Ferrian Sales & As- By carefully combining creative develop- sociates. “Needless to say, we’re excited to ment efforts with selected open source soft- be working with an assembly and test service ware, Hume is able to provide superior provider of Maxtek’s caliber and expertise.” function and value. The company’s products Maxtek Components Corporation is a are deployed in the latest semiconductor proven microelectronics assembly and test fabrication and test equipment, and are also company providing a complete range of used to integrate the diverse mix of equip- custom design, prototyping, manufacturing ment in established factories and test floors. and test services to equipment manufacturers. Headquartered in Beaverton, Oregon, Maxtek can be found on the web at www. August Technology Rohm and Haas maxtek.com. Appoints Cory Watkins Electronic Materials Chief Technology Officer IC Interconnect Names New President Joins the Entegris Final Technology leader joins August Microelectronic Technology's strategic team Manufacturing Partner Technologies MINNEAPOLIS, MN – August Technology Program Corporation, a leading supplier of inspection MARLBOROUGH, MA – Rohm and Haas and metrology solutions for the microelec- Electronic Materials has named Yi Hyon CHASKA, MN – Entegris, Inc., a leader in tronic industries, announced that Cory Wat- Paik, to succeed Stephen Robinson as Presi- materials integrity management, announced kins has been appointed Chief Technology dent Rohm and Haas Electronic Materials that IC Interconnect (ICI), an industry leader Officer. In this role Watkins will oversee Microelectronic Technologies. Most recent- in electroless nickel/gold under-bump-metal- strategic technology and product roadmaps ly, Paik was President Rohm and Haas Elec- lurgy joined in the Entegris Final Manufac- as well as the development of new products tronic Materials Asia. Robinson will lead turing Partner program. Through this part- and technologies. the company’s Architectural and Functional nership, Entegris, ICI and other companies Prior to being appointed CTO, Watkins Coatings business. will work closely together in the develop- most recently served as August Technology’s Paik joined Rohm and Haas in 1990 ment of world-class solutions for protecting Director of Advanced Technology Develop- as a senior scientist in the Research Divi- bumped wafers during shipping. ment and was directly involved in evalua- sion in Spring House, Pennsylvania. Assign- The Final Manufacturing Partner pro- tions of the Company’s 2003 acquisitions ments with Rohm and Haas have included gram is an alliance between Entegris, OEMs of Semiconductor Technologies and Instru- leadership roles in Strategic Planning and and service providers to demonstrate com- ments and Counterpoint Solutions, Inc. Electronic Materials Korea. In 1999, Paik patibility between high-performance semi- Additional information can be found at was named to lead the Electronic Materials conductor handling and shipping products www.augusttech.com. Asia-Pacific regional business and elected and process equipment. Current global part- Vice President of Rohm and Haas in 2002. ners of the program include: Entegris, Ac- He holds B.S., M.S. and PhD degrees in cretech, Disco, ESEC, IC Interconnect, IC Hume Integration Chemistry. Services, Integrated Dynamics Engineering, Additional information about Rohm and NEXX Systems, Inc., Teikoku Taping Sys- Software Appoints Vice Haas may be found at www.rohmhaas.com. tems Co. LTD. and Tru-Si. IC Interconnect is ISO 9001 and QS 9000 President of Business certified and prides itself in providing strong Maxtek Components customer service and engineering support Development to customers in the Americas, Europe and Signs Ferrian Sales & Asia. Additional information about ICI can Charbonnet named to lead be found at www.icinterconnect.com. major marketing and sales Associates as Midwest Entegris is ISO 9001 certified and has growth manufacturing or service facilities in the US, Representatives Germany, Japan, Malaysia and Singapore. AUSTIN, TX – Hume Integration Software Its advanced research laboratories are locat- has announced the appointment of Clark BEAVERTON, OR – Maxtek Components ed in Minnesota and Colorado. Additional Charbonnet as Vice President of Business Corporation, a Tektronix, Inc. company and information can be found at www.entegris. Development. a custom microelectronics assembly and test com www.meptec.org 14 MEPTEC REPORT / QUARTER TWO 2004 Industry News

Hestia Technologies, 990 Richard Ave. Suite SMT Magazine created the Vision Awards Hestia Awarded Patent 109, Santa Clara, CA 95050 12 years ago to acknowledge meaningful new products that meet significant industry for Fingerprint Sensor challenges, creatively apply new or existing Henkel Honored with technology, represent outstanding quality Package and performance, and answer current eco- Vision Award nomic throughput demands. SANTA CLARA, CA – Hestia Technolo- gies, Inc. has been awarded a US patent # Wins soldering materials 6,667,439 titled “ Integrated Circuit Pack- category with new lead free Taiwan Sunball age Including Opening Exposing Portion of solder paste an IC”. This technology is presently being Acquires Advanced used in volume manufacturing of fingerprint INDUSTRY, CA – Henkel Corporation re- touch sensor packages with an exposed por- ceived the 2003 SMT Vision Award in the Precision Technology tion of the die. Although the initial applica- category of soldering materials products tion was for touch sensors, this technology for Multicore® LF320™, a lead free solder SANTA CLARA, CA – Taiwan Sunball will have other applications where a portion paste with a minimum peak reflow tempera- announced that it has acquired Advanced of the die needs to be exposed. ture of only 229°C. Precision Technology Co. (APT). The acqui- This advanced technology provides a Designed to facilitate the transition to sition involves the purchase of APT’s pro- packaging solution and makes it possible to lead free processing, Multicore® LF320™ duction technology and certain manufactur- produce a low cost plastic molded package offers electronics manufacturers three-fold ing equipment. Sunball will also take over with an opening exposing a selected portion cost savings. 1) The 10°C advantage reduc- APT’s existing customers which include of the die. es damage to temperature-sensitive low Dt Carsem and UTAC and take care of relevant Hestia Technologies continues expanding boards, and 2) requires less energy to power customer service and support. its patent holdings by utilization of its unique reflow ovens. 3) Multicore® LF320™ re- According to Chihmin Chou, Country core technologies and capabilities. flows higher Dt designs at temperatures up Manager of Sunball, “Sunball has switched For additional information on this and to 260°C, allowing many types of boards to from propriety cutting technology to APT’s other packaging solutions provided by Hestia be easily processed using one product. jetting technology on partial production lines Technologies, Inc. Please visit their website Henkel Corporation is one of 15 com- and this move helps to lower production at www.hestiatechnologies.com or contact: panies honored with 2003 Vision Awards. costs by increasing yield rate.”

www.meptec.org 15 MEPTEC REPORT / QUARTER TWO 2004 Industry News

“Together, our customer base is now proved, Maxtek’s quality control process. electronics packaging applications. Find out broader and more comprehensive” Chou The quality assurance of Harris GCSD more at: www.asymtek.com. noted. “This means we are capable to handle products, along with components and mate- For more information about Cookson all types of customers from assembly house, rials received from suppliers, is a vital aspect Electronics visit www.cooksonsemi.com. IDM to IC testing company.” Chou also of Harris’ success in fulfilling their role as a reported that companies’ product lines have provider of mission-critical government and been consolidated, resulting in a wide range military communication systems. Verifying SunSil Inc. Appointed to of specification of solder balls now available the quality control capabilities of vendors is from a single source. also important to Harris’ product develop- Represent JDS Uniphase Taiwan Sunball, established in 1999, is ment programs. Working with high-quality an ISO14001 and QS9000 certified solder vendors eliminates the added time and ex- Fiber Laser Marking sphere manufacturer. Sunball products have pense of micromanaging vendors, applying been certified by Amkor, ASAT, ChipPac, additional controls to verify incoming qual- Systems Hynix and ST Micro. ity and, at worst, the selection of and transfer Sunball products are available in the US of work to, a new vendor. ALAMO, CA – The JDS Uniphase Com- through Cumulative Technologies in Santa “Ensuring the quality of product pro- mercial Laser Division of Santa Rosa, Calif., Clara, California. For more information call vided by our vendors is a key component has appointed SunSil Inc. to represent its 408-969-9918 or e-mail [email protected]. of Harris’ success in consistently exceeding complete line of fiber laser marking (FLM) our customers’ requirements and expecta- systems in North America. tions. We regularly survey our suppliers The FLM offers many unique advantages Carsem Receives Special to confirm they have the requisite quality in marking applications, according to Seth processes in place, and are executing to those Alavi, SunSil president. “Unlike conven- Achievement Award from procedures,” said Jeff Smith, supplier rating tional solid-state lasers, the FLM systems systems supervisor at Harris GCSD. em-ploy a double-clad optical fiber that has Analog Devices Headquartered in Beaverton, Oregon, been doped with a rare-earth lasing mate- Maxtek can be found on the web at www. rial. CITY OF INDUSTRY, CA – Carsem, a maxtek.com. “The FLM has also been pumped with leading provider of turnkey packaging and multiple, high-power laser diodes. This com- test services to the semiconductor industry bination of technology, that fuses all the announced that they each recently received Asymtek and Cookson components together through to the fiber, a Special Achievement Award for calen- makes the laser immune to misalignment dar year 2003 from Analog Devices, Inc. Materials Group Work and optical contamination,” Alavi added. (ADI). The FLM is the ideal marking system During a ceremony held in Boston on Together on Jetting for a wide variety of semiconductor pack- March 10, 2004 the award was presented to age types. The fiber laser produces marks David Comley, Carsem’s Group Managing Underfill Project in the continuous wave operating mode that Director by John Hassett, Vice-President of provide great uniformity, making it highly Assembly and Test; and Gene Hornsby, Di- CARLSBAD, CA – To obtain optimal pro- desirable for today’s thinner semiconductor rector of External Assembly & Test Foundry cess solutions for their customers, Asymtek packages. Quality. teamed with Cookson Electronics’ Semi- The FLM can be easily integrated with a Out of thousands of ADI suppliers around conductor Products Division on a new proj- wide range of other OEM parts and products. the world Carsem was among only ten to ect to jet underfill. Cookson Electronics The unit is rack-mountable and includes receive an achievement award. – Semiconductor Products of Alpharetta, software that enables the FLM to be integrat- “Analog Devices chose to recognize Georgia visited Asymtek’s application labs ed and controlled by most standard marking Carsem for their collaboration on the suc- to test their fluid materials on Asymtek’s systems and test handlers. cessful Plastics Assembly Project,” said X-1000 Series, configured with the new DJ- Gene Hornsby. “ADI was able to make a 9000 DispenseJet®. “Many of our customers significant strategic change without affecting use Asymtek’s technology,” explains Man- March Plasma Systems customer service or manufacturing metrics. dar Painaik, Technical Services Engineer We really appreciate the hard work and focus at Cookson Materials Group. “We wanted Opens Offices in Japan displayed by Carsem on helping us redeploy to learn about Asymtek’s equipment so we some of our assembly manufacturing.” can recommend the best materials for our March Plasma Systems has recently estab- customers.” This collaboration enables the lished direct operations in Japan. The new in-vestigation of new and innovative jetting March offices are located in the Nordson Harris Approves methods and material optimization. facility in Tokyo, Japan. “With a growing The two companies work together as a customer base in Japan, our new offices in Maxtek Components as part of Asymtek’s “Win3” program, in which Tokyo allow us to provide our customers key fluid formulators, technology institutes with local sales and service support,” reports Quality Supplier and equipment suppliers join together for Peter Bierhuis, President, March Plasma the benefit of customers, each other and the Systems. BEAVERTON, OR – Maxtek Components industry as a whole. The combined expertise The Japan facilities will be equipped with Corporation, a Tektronix, Inc. company and results in a “Win-Win-Win” situation that in- March plasma treatment systems for custom- a custom microelectronics assembly and test creases business for all. er training, demonstration and applications service provider, today announced that Har- Asymtek supplies award-winning auto- support. To manage their Japanese op-era- ris Government Communications Systems mated fluid dispensing systems, special- tions, March appointed Terumitsu Tsuji as Division (GCSD) has surveyed, and ap- izing in semiconductor, surface mount, and Business Manager, Japan and named Yuji www.meptec.org 16 MEPTEC REPORT / QUARTER TWO 2004 Industry News

Takai their Regional Sales Manager. Other used in a copper wire application. “In certain the entire 18” x 16” (458 x 407 mm) inspec- recent activities include the appointment of ap-plications with wires of larger diameters, tion area. This precise manipulation allows new distributors for the semiconductor and copper can be an efficient replacement for the XD7600 to inspect all interconnections PCB market segments, and the formation of gold wires. Our Eagle-60 gold wire bonder – ball, bond and wire – on BGA and CSP strategic alliances with key allied equipment platform offers the flexibility to extend pro- devices. But Dage hasn’t stopped there – the partners in the Japanese market. cess recipes to copper. We believe ASM is enhanced viewing capability of the XD7600 With over 20 years of continuous inno- the world leader in copper wire bonding platform is further enhanced with Dage’s vation, March designs and manufactures a technology, having delivered over 200 ma- revolutionary new ‘filament-free’ x-ray tube, complete line of award winning and patented chines to a variety of customers for applica- the Dage NT250. plasma systems that support all markets. tions requiring one to six mil wire diameter The NT250 x-ray tube, the first of its See the March web site for more details: copper capabilities.” kind in the semiconductor packaging mar- www.marchplasma.com. Launched in 2002, the award-winning, ket, provides feature recognition down to Eagle-60 gold wire bonder is the industry’s 0.25 microns (250 nanometers) in a unique first production machine capable of 35-mi- maintenance-free package. This innovative STATS and ChipPAC Agree cron fine pitch bonding. It also offers 20-per- x-ray tube, coupled with a standard ‘active cent higher productivity than its predecessor anti-vibration control’ raises the bar for the to Merge model. ASM has gained market share with highest resolution, the best image quality each generation of new gold wire bonders available in the market and in a maintenance ST Assembly Test Services Ltd (STATS) and since introduction in 1998. Continued mar- free package. ChipPAC, Inc. have announced the signing ket penetration, particularly in bonders, has Visit Booth 10316 at Semicon West to of a definitive agreement for the companies made ASM the leader in the global semi- see the future of x-ray inspection. to merge in a stock-for-stock transaction to conductor assembly equipment market since create one of the world’s premier indepen- 2002. For more information, visit ASM’s dent semiconductor assembly and test solu- web site at www.asm.com. STATS Introduces tions company. The combined company expects to have Design-for-Test to over US$1 billion in revenues in 2004. It will be the 2nd largest test house and will have Reduce Cost of Test and leadership in mixed signal testing. It will also have one of the broadest portfolios of assem- Time-to-Market bly products and leadership in advanced packaging technologies such as stacked die, DFT capabilities extend STATS’ SiP and wafer level packaging. total turnkey solutions Charles Wofford, Chairman of STATS, will remain Chairman of the combined com- SINGAPORE and MILPITAS, CA – ST pany, Dennis McKenna, Chairman and Chief Assembly Test Services Ltd. (STATS) has Executive Officer of ChipPAC, will be the expanded its integrated turnkey solutions Vice-Chairman, and Tan Lay Koon, Presi- with Design-for-Test (DFT) capabilities that dent and Chief Executive Officer of STATS, will assist customers in improving testability will be the President and Chief Executive and throughput of their devices for a lower Officer of the combined company. The Board cost of test and faster time-to-market. of Directors of the combined company will Drawing from its test expertise in the have 11 members, with STATS designating areas of wireless, broadband, networking 7 members, and ChipPAC designating 4 and high end digital consumer, STATS can members. The new company is proposed to engage with customers upstream in the be named STATS ChipPAC Ltd, and it will A Revolution in design and test process to improve test be headquartered in Singapore. coverage and quality, reduce overall cost X-Ray Inspection of IC test as well as shorten time to volume production. ASM Receives Wire Dage Launches the Future of X- As part of its DFT capabilities, STATS ray Inspection at Semicon West will provide consultation and technical train- Bonder Order from Major ing to share the advantage of deploying SEMICON WEST, SAN JOSE, CA, Booth DFT and various DFT techniques including New US Customer 10316 – Building on their globally accepted Scan Insertion and Automatic Test Pattern superior image quality and ease of use, Dage Generation (ATPG), Built-In-Self-Test and BILTHOVEN, THE NETHERLANDS Precision Industries is again setting the mark Boundary Scan (JTAG). A leader in mixed – ASM International N.V. has announced for X-Ray Inspection Technology. Dage has signal test, STATS is also one of the few that its 54%-owned subsidiary, ASM Pacific announced the launch of its revolutionary assembly and test service providers in the Technology, Ltd., received its first Eagle-60 new flagship system the XiDAT XD7600. industry offering Mixed Signal DFT consul- gold wire bonder order from an American top The XD7600 will be featured and formally tation, which is a design methodology that five manufacturer of semiconductors princi- introduced at Semicon West, July 14–15, incorporates design with test considerations. pally used in a broad range of ad-vanced 2004 in San Jose, CA. In addition to DFT consultation, STATS communications applications. The equip- The XD7600’s innovative look and provides other upstream services as part of ment is scheduled for immediate delivery to manipulator design provides for oblique its total test solution. These services include an Asian factory of this new customer. angle views of up to 70-degrees for any multi-site test, concurrent test, tester plat- According to Patrick Lam, managing position 360-degrees around any point of form selection, test hardware and software di-rector of ASMPT, the equipment will be as well as test program development and www.meptec.org 17 MEPTEC REPORT / QUARTER TWO 2004 Industry News

pre-engineering test services. Test Taiwan will also provide ASE Test with DispenseMate® 550 series. The powerful industry-leading Cobra probe card repair ser- benchtop unit offers advanced capability vices, assisting ASE in offering best-in-class, with a small footprint. Ideal for many batch K&S and ASE Group rapid turn-around services to its customer dispensing operations including potting, gas- base, which comprises major international keting, solder paste and adhesive dispensing, Establish Test Operations wafer manufacturers. the DispenseMate 550 features a precision For more information about the ASE motion system with closed-loop brush- Partnership Group visit www.aseglobal.com. Kulicke & less DC motors. It also features control for Soffa’s web address is www.kns.com. Asymtek’s pumps and valves, digital gages WILLOW GROVE, PA – Kulicke & Soffa for precise fluid delivery and ease of setup, (K&S) and The ASE Group are pleased to and an optional vision system. announce a strategic relationship between Asymtek Introduces Two models of the DispenseMate 550 Kulicke & Soffa’s Test Products Group and ® Series are available with different dispensing ASE Test Limited. As part of the agreement, the DispenseMate 550 areas. The 555 model has a dispense area K&S will provide onsite services at ASE of 525 x 525 mm, or 20.7 x 20.7 in. The Test’s facilities in Taiwan. Benchtop Dispensing DispenseMate 553’s dispense area is 325 x The establishment of K&S probe card 325, or 12.8 x 12.8 in. Configured with the re-pair services at ASE Test’s Taiwan facil- System DJ-9000 Dispense-Jet®, the DispenseMate ity will give ASE continuous access to K&S offers the latest, most advanced dispensing technical support. In addition to supplying CARLSBAD, CA – Asymtek has introduced technology in a cost-effective system. standard epoxy probes for wafer test, K&S its newest compact dispensing system, the Find out more at: www.asymtek.com.

North American Semiconductor Equipment Industry Posts March 2004 Book-To-Bill Ratio of 1.10

SAN JOSE, CA – North American-based The SEMI book-to-bill is a ratio of Shipments and bookings figures are in manufacturers of semiconductor equip- three-month moving average bookings to millions of U.S. dollars. ◆ ment posted $1.32 billion in orders in three-month moving average shipments. March 2004 (three-month average basis) and a book-to-bill ratio of 1.10, accord- 12 Months Ending March 2004 ing to the March 2004 Express Report 2000 published by SEMI. A book-to-bill of 1.10 means that $110 worth of new orders were received for every $100 of product billed Average Bookings for the month. in Millions of Dollars The three-month average of worldwide 1500 bookings in March 2004 was $1.32 bil- $1320.7 lion. The bookings figure is even with the revised February 2004 level of $1.32 billion and 70 percent above the $777 million in orders posted in March 2003. 1000 $1201.2 The three-month average of worldwide billings in March 2004 was $1.20 billion. The billings figure is five percent above the revised February 2004 level of Average Shipments $1.14 billion and 40 percent above the in Millions of Dollars 500 March 2003 billings level of $857 million. “Stable bookings levels are indicative Book-to-BillBook-to-Bill of healthy growth as companies invest Ratio in capacity expansion that is rational,” Ratio 0 Bar scale starts at 25 1.23 said Lubab Sheet, research development 1.19 1.15 1.10 5 per increment 1.01 1.05 director of SEMI “Looking forward, guid- .90 .90 .93 .90 .92 .96 ance from companies points to continued strength in bookings and billings.”

Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar 04

Data compiled for SEMI by the independent financial services firm of David Powell, Inc. www.meptec.org 18 MEPTEC REPORT / QUARTER TWO 2004 Industry News

22 bumps-per-second, depending on bump Assembly Test Services Ltd. (STATS) has type, size and pitch. It offers + 5 µm posi- introduced a new dual row version of its tional accuracy at 3 sigma and can bump popular Quad Leadless Package which deliv- down to 65 µm. This next-generation K&S ers higher input/output (I/O) performance in stud bumper offers large table travel to a cost effective package for wireless and handle 12” wafers in a single pass. other hand held applications. K&S is also offering the new WaferPRO Compared to the current Quad Flat No- plus kit that provides a fast upgrade path lead (QFN) style of packages available in for all existing WaferPRO customers. By the industry today, STATS’ Dual Row Quad in-stalling the kit, which includes hardware, Leadless Package (QLP-DR) features a sig- specialized servo code, and motion profiles, nificantly higher number of I/O terminal customers can increase the performance of pads in a smaller footprint. The key to their existing WaferPRO stud bumpers to 22 the increased performance capability of the bumps-per-second. QLP-DR is in the leadframe design featur- K&S offers a wide selection of manual ing two rows of staggered I/O terminal pads chucks and fully automatic wafer handling with an exposed die pad for die grounding options with the new WaferPRO plus. and im-proved thermal performance. STATS K&S released the WaferPRO plus for full QLP packages are also available with non- production in May 2004. Upgrade kits will ex-posed pad to enable higher density board be shipped upon request from WaferPRO level routing. customers globally. Utilizing the same assembly and test pro- K & S Announces cess as the standard Quad Leadless Package, ™ QLP-DR offers a high performance device WaferPRO plus STATS Expands with high yield and reliability at a lower cost than many laminate or tape substrate based Next generation in stud bumping Quad Leadless Package chip scale packages and wafer level chip technology scale packages. In terms of environmentally Capabilities with friendly solutions, QLP-DR is a lead free/ WILLOW GROVE, PA – Kulicke & Soffa green package which is more cost effective Industries, Inc. introduces a new high-speed, Dual Row Design than laminate based packages. ◆ single-pass stud bumper that handles wafers up to 300 mm. The WaferPRO plus bonds SINGAPORE and MILPITAS, CA – ST WHY PUT OFF TODAY WHAT A CONSULTANT COULD HAVE DONE YESTERDAY?

Outsourcing, Planning, Analysis, Quality and other management tasks require skilled resources.

When the resources aren’t readily available use an experienced consultant. Phil Marcoux of PPM Associates, and Executive Director of MEPTEC provides this experience. Past experience includes executive management, including CEO and Board positions, engineering and quality management positions within leading corporations. Clients have included NASA, USAF, Harris Semiconductor, Cypress Semiconductor, National Semiconductor, Ericsson, Cisco, 3Com, Dupont and other multinational companies.

Phil Marcoux • PPM Associates 650-961-7909 • email: [email protected]

www.meptec.org 19 MEPTEC REPORT / QUARTER TWO 2004 MEPTEC Member Company Profile NS Electronics BANGKOK

L ong considered one of the best kept secrets in the subcon world, NS Electronics Bangkok (NSEB), has developed a strong reputation for high quality, short cycle times, and excellent customer service. These attributes are the core of an overall strategy by NSEB management to create a superior subcon experience for major semiconductor manufacturers worldwide. NSEB engineers review MSL sonoscan results. A well balanced portfolio of packages and services serve the entire community of IC manufacturers the last four or five years they have been ranked in the top five whether in memory, linear, logic, or RF products. or six subcons world-wide in terms of units shipped. Under any circumstances, to ship this volume (averaging about 67M ith more than 30 years experience as an IC units per day, including turnkey) to world-class customers assembly and test facility, the NSEB team can throughout the world, indicates a system which is both tightly easily argue that they may be the single most controlled as well as motivated to achieve best-in-class per- experienced collection of assembly and test formance. The test floor, currently running at capacities of W about 4M to 5M units per day, must be considered one of the engineering expertise available in the Far East. Their collec- tive experience means that they can speak the lingo needed largest, and most successful, independent test floors in Asia. to support top-of-the-line semiconductor companies in the Additionally, extra services available include burn-in, wafer US who are seeking competent support for their production sort, failure analysis and reliability labs, and creates an envi- needs. This applies to the smallest start-up company up to the ronment very much like the large IDM companies in the US. largest Fortune 500 company; all their customers deserve the At least part of the success of NSEB can be attributed to best in service available. The most frequently heard complaint the fact that the company has not strayed from its primary from our visiting customers? “Why can’t our other subs per- capabilities. Due to the fact that the many smaller conven- form as well as NSEB?” tional packages in their portfolio tend to be more manual Born from the decision of National Semiconductor to re- intensive, NSEB has found they are much more competitive duce its offshore factory base in the early 1990’s, NSEB was than some of the larger SATS companies in Korea, Singapore, purchased by local Thai investors in 1993. It is now com- Taiwan, and Japan. Also, they have found that the popularity pletely independent of National. Taking advantage of the core of these products is growing, primarily due to the natural competence in IC assembly and test, the new management trend in semiconductors to continually decrease the die size. team has developed NSEB into what may be the single best These days what used to require a package like an 8 SOIC, medium size IC assembly/test house in the Far East. During can easily fit into a smaller package like an SC70 or a SOT23.

NSEB utilizes only the best production equipment available in order to NSEB technician reviews leadframe quality check. satisfy its world class customer base with reliable high-volume capacity. www.meptec.org 20 MEPTEC REPORT / QUARTER TWO 2004 A world class test floor makes NSEB a leader in turnkey assemb;y and NSEB operator and an Ismecca NT116. test solutions.

Similarly, these packages require less material, and therefore associated with this product, they were able to develop their offer a more cost-effective solution to their customers. own intellectual property associated with QFN products of the Being ranked “best-in-class” by several of NSEB’s most sawn type. NSEB is now able to offer one of the most reliable, important customers is not simply a consequence of setting flexible, and innovative products available to semiconductor strategy. Due to the high-volume nature of the core business, houses interested in either chip-scale or leadless packages. it’s necessary that they create a factory which utilizes the best, The technical advantage of the low impedance leadless pack- highest quality equipment available. This equipment is spe- age, plus the inherent excellent thermal characteristics, makes cifically designed to handle the high quality, and short cycle this a package, which is just now starting to gain momentum. time nature of this volume driven IC business. NSEB cannot NSEB sees the popularity of this package as a bellwether of achieve anything if their equipment breaks down at the wrong the future and plans to continue to utilize it’s extensive engi- time, and they have to tell their customer… “sorry, but we neering capabilities to find solutions for our its customers IC can’t deliver.” For this reason they only work with equipment production issues. suppliers who provide them with the most reliable, best made Additional technical efforts have been required from equipment available world-wide. It may cost a little more, but NSEB to satisfy the industry needs for not only Lead Free if the customers are happy with the end results, then it’s well components, but also green components. It’s no accident that worth it. the joint development of the most advanced materials avail- Coupled with a proud Thai history and culture dating back able in the industry accounts for NSEB to being a leading sup- several hundreds of years leads to a workforce which is both plier of both types of components. Their NiPdAu compatible motivated, and capable of competing at the highest level. The production line has also been a key draw for major custom- country of Thailand is one of the shining jewels of the Far ers. East, in terms of its developing economy, and democratic In addition to new products, NSEB is in the midst of the government. Additionally, NSEB employees in Thailand suc- most serious expansion of facilities in its 30 year history. They cessfully compete with counterparts worldwide through their have purchased land, and developed facilities in keeping with hard-working nature, and creative solution finding. The Thai their overall strategy to be best-in-class. The new facility education system followed by extensive in-house training outside Bangkok gives NSEB about 50% more manufactur- allows NSEB to utilize the naturally industrious, creative, and ing space without diluting the overall focus of the company. intelligent characteristics of the Thai people. Quality certifi- The new facility with available land space of about 25 acres cates not withstanding, NSEB has been certified to the highest has the capacity to add additional one million square feet of standards available, including ISO/TS 16949, SAC Level 1, manufacturing space. And certainly, with the new Bangkok and ISO 140001. For most of their customers, “quality is a International Airport scheduled to open in 2005, it will not given”. However, for NSEB employees, quality is an exten- be long before NSEB will have two facilities, one on either sive part of their working life. With numerous QC committees side of the new airport, giving NSEB customers even more meeting both during and outside of regular hours, competing options, and access to an ever improving cycle time and deliv- successfully on a national level for new ideas and process ery. improvements to continually improve performance, quality An exceptional dedication to customer service, forever has become an everyday part of the working life. driving improving quality levels, meeting the most difficult However, with an eye on the future, NSEB has not been cycle time goals in the industry; these are all part of what has satisfied to rest on its laurels. Besides its strong competency made NSEB among the leaders of the SATS industry. As any in conventional IC packages, NSEB has taken the extra step professional knows, these accomplishments do not occur by to develop advanced packages like the QFN and BCC prod- accident, rather through hard work, planning, and searching uct line, which was licensed from Fujitsu of Japan. The BCC for creative solutions. ◆ line was developed first, but from the many technical inputs www.meptec.org 21 MEPTEC REPORT / QUARTER TWO 2004 Advertisement Advertisement SiP Technology Solving SiP Time-to-Market Challenges

Young Gon Kim, Ph.D. GSM Baseband Director, Packaging Technology Tessera, Inc. SRAM

he packaging industry has FLASH been en-gaged in extensive discussions on system-in-a- package (SiP) as a system miniaturization tool for years. TPopular comparisons with system-on-a-chip Figure 1: Main board for a GSM Cellphone, with the Baseband block highlighted in the blue box. (SoC) normally ended up with positive con- (Courtesy of Flextronics, San Jose, California.) clusions on the future of SiP. On the other hand, the cross-examination with multi-chip well mixed but it was possible to identify although passives are not shown in these module (MCM) history revealed hurdles major differences between SiP and MCM. simplified cross-sections. Design [A] com- to be overcome for SiP market ex-pansion. SiP has much stronger market needs with bines two standard memory packages on the Sometimes, a lack of a clear definition the recent explosion in portable products. In top of a custom designed baseband package. of SiP created unnecessary confusion in general, high volume production is the most All of the components can be tested before market analysis and its data interpretations. effective avenue to reduce manufacturing assembly, and standard packages can typi- This article aims to address the barriers to cost. KGD price has come down due to test cally be purchased at a lower cost. A limita- SiP development infrastructure for achieving technology progress, including wafer level tion of this package is the relatively large time-to-market goals. test and burn-in. At the same time, more package height and wide footprint as indi- In Advanced Packaging magazine, Sep- suppliers are participating in selling bare cated in the drawing. Design [B] provides tember 2003, Smith defined SiP as “a die. Legacy CPU sale from Intel, which was a thinner profile SiP solution by replacing single package having one or more ICs not an option before, indicates a significant standard packages with custom designed plus passives with multiple interconnec- business environment change with bare die. thin packages. [1] tions” . With this broad definition, Assembly technology development with thin Design [C] has a much smaller footprint SiP includes 3D packages and memory die die, and lower cost substrates with greater than [A] or [B], but it can only be considered stacked multi chip packages (MCPs). As far routing density, are additional elements pav- when all three die are available as KGD, as development in-frastructure is concerned, ing the road for the SiP future. because this structure does not allow indi- 3D packages and MCPs are facing similar vidual die replacement after functional test. barriers. Therefore, it is appropriate to SiP Design Case Study De-sign [D] can solve KGD and logistics adopt Smith’s SiP definition in this article. Figure 1 shows the main board for a problems with the smallest footprint. A For discussion purposes, a baseband SiP GSM cellphone designed and manufactured fully tested stacked memory is mounted on for cellphone applications will be used as a by Flextronics. An SiP can replace three the fold-over flap of the Baseband package, reference package. single chip packages (Baseband, SRAM, which can be pre-tested independently. An and Flash) and all of the passives within EMS company can assemble the top and bot- MCM vs. SiP the blue outlines. A small form-factor SiP tom packages during main-board assembly In the past, the MCM series (-L, -D, and provides several benefits to an electron- pro-cess. -C) were understood as very promising tech- ics manufacturing services (EMS) provider. All design options here are technically nologies for small form-factor and high-per- The main board can be designed with fewer feasible, but manufacturing cost varies sig- formance packaging solutions. Fully tested metal layers because the most dense routing nificantly. Depending on the development known-good-die (KGD) was the primary between the Baseband and memory ICs can goal, one design could perform better than barrier for the MCM market expansion. A be transferred to an SiP interposer. Here, the other. However, it is very important to lack of industry standards kept MCMs as interposer refers to the primary substrate in remember that the effective lifetime of a cell- only a small-volume and application-spe- a SiP combining bare and/or packaged die. phone is less than one year. In other words, cific packaging solution. MCMs could be In this case study, it was possible to reduce SiP benefits may disappear with an increase un-derstood as a subset of SiP with two- the main board metal layers from six to four. in the development time. This article reviews dimensional IC layouts. However, as far as Also, the main board area can be reduced five infrastructure barriers that could length- functionality is concerned, there is no major because of the smaller SiP footprint. Board en development turn-around-time (TAT), difference. Before discussing infrastructure assembly simplification is an additional ben- and proposes possible solutions for each. strengthening strategy, we need to confirm efit be-cause all ICs and passives can be SiP has a different destiny than MCM. placed or removed at the same time. Barrier 1 – SiP Ownership Panelists at the MEPTEC Symposium A Baseband SiP can be designed in many The product owner and service providers on February 19, 2004 were asked, “Is SiP different configurations. Figure 2 shows four are well defined for a package with a single different from MCM?” Their views were possible options for discussion purposes, die. Package design, assembly, and test are www.meptec.org 24 MEPTEC REPORT / QUARTER TWO 2004 SiP Technology

Scenario 3 – IDM Ownership Another possible case is the IDM taking over the ownership role. The supplier of the key IC, the Baseband chip, can facilitate and drive the overall SiP development activity. There are significant die-to-die interconnections between the Baseband and memory chips. Also, the IDM knows best about the test requirements and test programs for their internally developed ICs. Therefore, IDM- driven SiP development can provide several technical benefits by changing chip design, Figure 2: SiP design options. [A] Custom baseband and standard memory packages. [B] Custom like built-in self test (BIST), extra test pad, packages. [C] Folded Package, and [D] Fold-Over Package. The width and height are illustrated pad function swap, or pad location change. in each drawing and the depth of the SiP is indicated by the “y” dimension. Die shrink related issues can also be addressed most effectively by IDMs. also well defined and guided by the product sions on detailed questions to optimize SiP SATS companies know best about the owner. A single SiP has multiple ICs owned routing efficiency, assembly process yield, package itself and provide package design, by integrated device manufactures (IDMs), and test efficiency. This is because many of package assembly, and test services. How- and the target functionality could be defined the design iterations are related to the SiP ever, SATS may not be a good candidate for by either the original equipment manufac- footprint and ball function swap, which is SiP ownership due to the limited understand- turer (OEM) or the EMS provider. For this mainly handled at the EMS provider. ing on device/system functionality. Lack of reason, unfortunately, a current SiP might the system knowledge may make it difficult be de-veloped by a loosely defined set of Scenario 2 – EMS Ownership to address technical issues at the right time. multiple owners. For a short development The EMS gets more benefits than any In the case of a clearly defined SiP, SATS TAT, clearly defined single ownership is other company for SiP adoption – simpler can lead the development activity without more efficient than loosely defined multiple main board routing, board size reduction, unnecessary time delay. With standardiza- owners. The industry has to reach a con- and board assembly simplification. EMS tion pro-gress on SiP, SATS roles will be sensus to differentiate product owner and can adjust the main board design for simpler increasing with time. material/service pro-viders. It is essential to interposer routing, higher assembly yield, assign SiP ownership to a party who could and low cost test solution implementations. Barrier 2 - CAD Tool facilitate quicker decisions on numerous All of these ideas and questions are com- Numerous CAD tools are available for technical specification changes for easier ing from package design, assembly, and single chip package design and verifica- design, simpler assembly, and better test- test en-gineers. Minor changes at the EMS tion. Electrical performance, thermal per- ability. Figure 3 illustrates the supply chain level al-low creative engineering solutions. formance, and reliability issues can be sorted for Baseband SiP development. In order to The SiP interposer can be designed by either out in the early stages with reasonable con- manage SiP development with shortest TAT, the EMS provider or the design services fidence. However, these tools are not suf- three possible scenarios can be considered. organization in a semiconductor assembly ficient to analyze multi-die interconnections and test service (SATS) provider. In the case with 3D stacking configurations. Figure 4 Scenario 1 – OEM Ownership of a complex SiP with challenging package shows die-to-die and die-to-board intercon- An OEM, such as Nokia for this cell- assembly and test processes, the latter case nections for a Baseband SiP with a wireless phone example, defines the product, includ- could be more effective. In summary, as module, which is a typical configuration for ing SiP functionality specifications. A system illustrated in Figure 3, the EMS can directly next generation cellphones[2]. Typical bare schematic is created to communicate with communicate with the OEM, IDM, and die and a wireless module were chosen for the main board supplier, an EMS company. SATS company. Therefore, EMS ownership this diagram. Only a portion of the connec- The OEM can provide product qualification can allow fast decision making processes for tions are shown to ensure clarity. criteria and the target development schedule. the shortest TAT. The first challenge for a CAD tool is an However, OEM ownership could delay deci- optimal SiP structure search. Each die can be placed on the SiP interposer with either face-up (wire bond) or face-down configuration (flipchip, stud bump, or lead bond). Die orientation can impact the interposer routing efficiency as well, and four or eight different die orientations (0°, 45°, 90°, 135°, …) could be considered. The stacking order (3D) and die placement variations (2D) can create more than ten different configurations. Stacking bare die or CSP, adopting a folded or flat interposer format, substrate types, and use of conventional or embedded passive solutions can add significant design options. The current case study in Figure 4 can easily create over 100 different SiP configurations. Many of them are obvious to eliminate from the list, but a significant quantity of them Figure 3: Supply chain for Baseband SiP development. should be carefully analyzed. www.meptec.org 25 MEPTEC REPORT / QUARTER TWO 2004 SiP Technology

design but for single chip package substrate a powerful technique to test a specific IC design. Therefore, in general, SiP interposer within the assembled SiP. It makes other die routing is more complex than the single chip electrically transparent during the test, which case and may create signal integrity issues. enables use of existing test programs[2]. Fre-quently, a few pad function swaps or However, the test data could be distorted by pad location changes can simplify interposer nearby multiple ICs and passives. de-sign significantly. For example, in Figure SiP level test program development is a 4, there are four cross over lines between big challenge. Testing requires detailed IC the DSP and SDRAM die. By eliminating design information. This data is often dif- these cross over lines, a cost effective and ficult to obtain but it can often be acquired quick turn design solution can be more easily with the help of friendly, neutral, or a com- achieved. petitor’s source. Overall test cost reduction is From the IDM viewpoint, this may not as important as development time reduction. be an attractive approach because one more The industry needs to invest more resources mask set would need to be added to capture to develop technologies on built-in-self-test, a relatively small market. However, the re- test pattern on interposer, known good die, turn on investment can be justified by high known good package, process monitoring, Figure 4: Interconnection nets for a Baseband volume, and volume could be increased failure detection, and repair. SiP with a wireless module. through industry cooperation – SiP standard- Barrier 5 – Substrate and Embedded ization. There are a variety of SiP types, but It is essential to have a CAD tool to sort it is possible to classify by application, like Passives out design options violating specified design Baseband SiP or RF front-end SiP. Such a All conventional package substrate mate- rules – signal integrity, heat dissipation, foot- grouping can increase specific IC production rials can be used for SiP interposer fabrica- print size, product height, and package reli- volume by capturing the same or similar tion – lead frame, polyimide, laminate, and ability, for example. Detailed performance application markets. SiP grouping or classi- low temperature co-fired ceramic (LTCC). and reliability optimization can be done with fication could be understood as the first step Integration of small form factor passives, a few designs only. John Park, Senior Tech- of SiP standardization. like 0201, can add cost and may adversely nical Leader of CADENCE, highlighted the The SiP standardization process explain- affect assembly yield. Another approach is requirements for a new CAD tool for SiP ed above can be summarized by Figure 5. embedding passives within the SiP interpos- development as: The first step, SiP grouping, can increase er. This can simplify the assembly process • Constraint driven layout with support the required IC production volume. The by reducing the total number of components for 3D rules – Design to manufacturing, increas-ed production volume can then jus- to be picked-and-placed. However, it is not a electrical, and thermal constraints. tify additional mask investment for pad trivial task to get high quality passives with • Interactive and automatic constraint function/ location customization. This activ- tight process tolerance. Trimming is one tech- driven routing – Handle multi-layer, ity will provide positive feedback to the SiP nology to compensate process driven data build-up, and differential signaling market to make all of the activity even more shifts, but it increases substrate cost. Mater- issues. active. The SiP market can expand rap- ial and equipment suppliers in Japan orga- • High flexibility and scalability – No size idly by this kind of standardization activity. nized the SiP Consortium (www.sip-c.com) limitations in number of layers, pins, JEDEC recently formed Product Committee to address some of the issues discussed in and nets. JC-63, whose scope is to define and propose this article. • Flexible logic entry – Schematic driven standards for multi-chip packages[3]. Summary and/or logic assignment on-the-fly signal Barrier 4 – SiP Test The SiP solution has a high potential assignment. Component level test, assembly process and will impact the semiconductor industry • Embedded component support – Any- monitoring, and post assembly subsys- significantly in the next five years. Semico layer passive and active component tem test should be balanced to minimize estimates production volumes of 100K to placement. the overall SiP test cost. Assembly related 10M parts as a sweet spot for SiP technol- • Automated substrate or interposer cre- defects increase with process progress. Pro- ogy having clear benefit over SoC technol- ation – Support for multiple substrate [4] cess monitors can save time and money by ogy . A common assumption behind their materials and manufacturing/design purging SiPs with process defects. However, analyses is that SiP can be developed in a processes. intensive process monitors may introduce much shorter time than SoC. If this assump- Barrier 3 - SiP Standardization test re-dundancy issues. Test in early stages tion is not accurate, SiP may follow the Individual ICs for a SiP are the same is simpler and less expensive, and it is desir- earlier MCM track, finding limited success. as ICs developed for standard single chip able to utilize test programs and test sockets Five major barriers to SiP time-to-market packages. Die pad location and functional developed for single chip packaging. Die were reviewed in this article. SiP ownership, order are determined not for SiP interposer isolation by controlling impedance (Z) is CAD tool, standardization, test, and high- density substrate capability were identified as areas where the in-frastructure needs to be strengthened. ◆

Author Young Gon Kim may be reached at [email protected].

References [1] Paul Smith, “Getting your SiP to Market,” Advanced Packag- ing, Sept. 2003, pp. 55 – 57. Figure 5: SiP standardization loop with positive feedback. [2] HK Kwon et al., “SIP Solution for High-End Multimedia www.meptec.org 26 MEPTEC REPORT / QUARTER TWO 2004 For production in the millions, a System on a Chip is the best way to go. But it’s not the fastest way to market because, in many cases, it is extremely difficult to implement. If time is of the essence… Go SiP (System in Package). You can mix digital, analog, RF and passives into one small package creating single-package soutions for Bluetooth™ and other applications. There’s no faster way to go from product concept, to prototype, to production. You know it and so do we.

That’s why Carsem has a first-class SiP prototype and manufacturing capability to support your SiP requirements. We can integrate a variety of ICs and components using flip chip, wire bond and stacked die technologies on both organic (BT) and ceramic substrates. For wireless applications, we can also “tune while testing” for even higher RF performance. Let us tell you how we can turn your SiP design into a production product quickly and easily. For the best choice in SiP manufacturing call Carsem today.

Visit www.carsem.com or email [email protected] Your Technology Partner

Malaysia Europe USA USA USA USA Ipoh UK Silicon Valley Los Angeles Dallas Boston tel: 60-5-5262333 tel: 44-1793-853888 tel: 831-438-6861 tel: 626-854-0939 tel: 972-580-1706 tel: 508-699-4720 fax: 60-5-5265333 fax: 44-1793-855388 fax: 831-438-6863 fax: 626-854-9139 fax: 972-580-1806 fax: 508-699-4512

Carsem—A member of the Hong Leong Group Malaysia Component Packaging Technology Components – A Process Engineers Perspective

Robert Rowland Process and Supplier Engineering Manager RadiSys Corporation

omplex components (i.e. Components. < 30˚ C/60% RH fine pitch devices and ball • IPC-9501 • Level 6 – time on label floor life at grid arrays) drive board level PWB Assembly Process Simulation < 30˚ C/60% RH assembly pro-cesses (i.e. paste for Evaluation of Electronic Compo- printing, component place- nents (Preconditioning IC Compo- J-STD-033 provides recommendations Cment, reflow soldering, etc). Assembly nents). technology must keep pace with compo- for handling, packing, shipping and baking nent packaging. The challenge for SMT • IPC-9502 moisture sensitive devices. The em-phasis process engineers is to develop robust PWB Assembly Soldering Process is on packaging and preventing moisture processes that keep up with rapid advance- Guideline for Electronic Components. absorption, post drying (baking) should only be used as a last resort after excessive ments in component packaging technol- • IPC-9503 exposure has occurred. ogy. SMT process engineers en-counter Moisture Sensitivity Classification for Dry packing involves sealing moisture the expected (planned process improve- Non-IC Components. ments) and the unexpected (de-fects and sensitive devices in moisture barrier bags reliability problems).Two complex and • IPC-9504 with desiccant and a humidity indicator challenging issues for SMT pro-cess engi- Assembly Process Simulation for card. Moisture sensitive caution labels neers are moisture sensitive de-vices and Evaluation of Non-IC Components must also be placed on the outside of the component placement. (Preconditioning Non-IC Compo- bag. Labels are important because they nents). provide critical information (see J-STD- Moisture Sensitive Devices 033) for the end user. Here are the basic When non-hermetic components, such For complex IC devices (i.e. BGAs) dry packing guidelines. as fine-pitch devices and ball grid arrays, the primary documents are J-STD-020 are exposed to the elevated temperatures and J-STD-033. J-STD-020 defines the Level 1 – Drying before bagging is option- that occur during reflow soldering, mois- classification procedure for moisture sen- al, bagging and desiccant are optional, and ture trapped inside of these devices will sitive components; in other words non- labeling is typically not required. hermetic packages made from moisture- produce enough vapor pressure to damage Level 2 – Drying before bagging is option- permeable materials such as plastic. The or destroy the package. Common failure al, bagging and desiccant are required, and classification process includes exposure modes include delamination, wire bond labeling is required. damage, die damage, internal cracks, and, to reflow soldering temperatures followed in extreme cases, cracks that extend to the by detailed visual inspection, scanning Level 2a – 5a Drying before bagging is surface of the package. In severe cases the acoustic mi-croscopy, cross-sectioning required, bagging and desiccant are re- package will bulge and pop (referred to as and electrical testing. Based on the test quired, and labeling is required. results, devices will be assigned to one of the “popcorn” effect). Level 6 – Drying before bagging is option- the eight moisture classification levels. The Association Connecting Electronic al, bagging and desiccant are optional, and Industries (IPC) has created and released • Level 1 – unlimited floor life at labeling is required. Level 6 components IPC-M-109, Moisture Sensitive Compo- < 30˚ C/85% RH are unique, they are so moisture sensitive nent Standards and Guideline Manual. It that they must always be baked prior to • Level 2 – one year floor life at includes the following seven documents: reflow soldering. < 30˚ C/60% RH • IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classifi- • Level 2a – four week floor life at Baking is a little more complicated cation for Plastic Integrated Circuit < 30˚ C/60% RH than many people realize. J-STD-033 contains baking recommendations for pre and Surface Mount Devices. • Level 3 – 168 hour floor life at post dry pack based on level and package < 30˚ C/60% RH • IPC/JEDEC J-STD-033 thickness. Pre-baking is used to prepare Standard for Handling, Packing, Ship- • Level 4 – 72 hour floor life at components for dry packing. Post baking ping and Use of Moisture Reflow < 30˚ C/60% RH is used to recondition components after the Sensitive Surface Mount Devices. floor life has expired. Baking temperatures • Level 5 – 48 hour floor life at can decrease lead solderability by oxidiz- • IPC/JEDEC J-STD-035 < 30˚ C/60% RH Acoustic Microscopy for Non- ing the leads or by causing excessive inter- Hermetic Encapsulated Electronic • Level 5a – 24 hour floor life at metallic growth. Some companies store www.meptec.org 28 MEPTEC REPORT / QUARTER TWO 2004 Component Packaging Technology

components in a baking oven; this is not a en-tire component at one time are faster images. The vision system converts a gray good idea. than systems that must compile a complete scale image to a binary (black and white) view from several sub-views. Resolution image. The system then uses an algorithm Component Placement is related to the number of pixels in the to determine the center of a white feature Vision systems have revolutionized camera, more pixels mean better resolu- that is placed against a black background. component placement. There are two im- tion. Some systems use sub-pixel process- Binary imaging works very well with per- portant elements for successful component ing, which improves resolution, but it ipheral leaded components. imaging. First, the placement machine in-creases processing time. Vision systems Gray scale imaging operates in a man- must contain a capable vision system. employ two lighting methods, referred to ner similar to binary imaging; however a Second, the component must be camera- as binary or gray scale. Both methods are gray scale image (with surface features) friendly. Contrast is a critical element in sensitive to contrast and lighting changes. is used which means more component image processing. If the vision system can Binary systems illuminate the component de-tails are analyzed. Because more infor- not clearly distinguish surface features it from above, which creates a component mation is processed gray scale imaging will not be able to accurately position the outline. The component outline is pro- systems require more computing power component on the substrate. For example, jected into the CCD camera for process- and processing time Gray scale imaging is ceramic BGAs are difficult to image being. Gray scale systems illuminate the preferred for BGAs. ◆ cause the contrast between the component component from below, which allows the body and the solder balls is poor. Unusual vision system to detect surface features. Robert Rowland is the process and supplier surface features, for example a non-sym- The surface features (i.e. solder balls) are engineering manager at RadiSys Corp. in metrical component, can also cause prob- reflected into the CCD camera for process- Hillsboro, OR. He is a member of SMT lems by confusing the vision system. ing. Both methods use vision alignment in Magazines Editorial Advisory Board and co- Vision systems typically use a CCD the same fundamental manner. The vision author of the book Applied Surface Mount (charge coupled device) camera for imag- system determines the X, Y and theta off- Assembly. Robert is an active member of the ing. Important vision system elements set of each component prior to placement. SMTA where he serves as technical confer- include field of view (FOV) and resolu- Binary imaging locates a feature using ence director of SMTA International. He is tion. Vision systems that can view the the contrast between black and white a recipient of the SMTA Founders Award.

www.meptec.org 29 MEPTEC REPORT / QUARTER TWO 2004 MEMS Technology Wafer Scale Vacuum Packaging of a MEMS Optical Scanner

Kelly D. Linden, Mark P. Helsel, Jason Tauscher and David Bowman Microvision, Inc.

pplications for MEMS opti- a critical challenge in creating a techni- • There must be a vacuum compatible cal scanning technology are cally and commercially viable device.2 di-electric barrier between the high voltage ever in-creasing as the scanner For example, the Texas Instrument’s DLP traces and the grounded silicon scanner. design fundamentals and fab- chip is hermetically sealed in a package • The substrate must maintain a hermetic rication process matures. We with an optical window.3 As the window seal between the scanner and itself. Ahave de-monstrated the cost effectiveness requirements and the hermeticity specifica- • The thermal coefficient of expansion of using a MEMS optical scanner to drive a tions be-come more complex, the cost of must closely match that of silicon up to a head worn display for the industrial market. goods of the MEMS subassembly increas- temperature close to 425˚C. The technical performance of the SVGA es. Microvision’s scan engine used in the The substrate wafer fabrication process biaxial scanner used in this application has Nomad product has similar challenges.4 is fairly straight-forward. A Pyrex wafer is been described in a previous paper.1 The Introducing a wafer level, hermetic package masked off and a multi step cavity structure next generation of products is targeted to itself re-quires a high yielding inexpensive is etched into the surface using hydrofluoric the consumer market in applications such process in order to overcome the expense of acid (HF). These depths are approximately as electronic viewfinders for digital camer- losing die due to packaging failures. Wafer 90µms and 200µms deep. The added HF as, automotive heads-up displays and web level packaging is not truly viable unless etches Pyrex isotropically. The isotropic enabled cell phones. The transition to the both subassemblies are mature and high etch has its benefits but also a significant consumer market, however, puts higher de- yielding. downside. The etch results in a very sharp mands on the optical scan engine in regards edge between the top surface and the cavity. to cost and size. One way to achieve the Wafer Level Packaging This edge prevents the electrical traces from required cost and size objectives is to There are four components to this traversing from the lower level cavity to the package the scanners in a vacuum-sealed assembly. They include the Substrate Wa- package at the wafer level. Packaging of the fer, MEMS Scanner Wafer, a Spacer Wafer scanners, especially at the wafer level, is a and an Optical Window. Each one of the complex process with tight requirements. subcomponents has stringent requirements This paper describes the process to package each with their own set of challenges. The a complete, hermetically sealed scanner as- method of bonding the four components sembly in a reduced pressure atmosphere at together is of critical importance to a wafer the wafer level. The process brings together level packaging technology. Wafer bonding an ultrasonically milled (USM) thick spacer has been an active area of research for many wafer, an anti-reflective (AR) coated, op- years in the areas of MEMS and semicon- tical quality window, the electrostatic drive ductor packaging.5 Some techniques that substrate and the MEMS scanner into one have been used successfully include fusion completed assembly. The AR coated wafer, bonding, reaction bonding6 with RIE pre- USM spacer wafer and substrate are screen treat7, glass frit bonding, bonding with printed with a glass frit and fired. The com- many different metal eutectics8, sodium Figure 1. Cross-Section SEM image of the slope. plete assembly is placed in vacuum system, silicate bonding9, anodic bonding using aligned and evacuated to a predetermined bulk glass10 and sputtered glass films11 pressure for a specific amount of time. The and gold thermocompression bonding.12 chamber is then purged with a controlled In this case we have chosen glass frit as the gas before the final temperature is reached best method for joining the four compo- and bonding force applied. The outcome nents together.13 is a four-wafer, hermetic, reduced pressure atmosphere assembly that is easily handled. Substrate Wafer Resist Breaks Over Edge By balancing the yields and costs of wafer- The substrate wafer is the component level packaging technology, the cost and that provides the electrostatic drive to the size requirements of the consumer market scanning mirror. The requirements are as can be realized. follows: • It needs to allow clearance for the mir- Introduction ror to move more than 6.2 degrees in the Resist Coat Over Pyrex Edge without Slope MEMS or micro-electromechanical sys- horizontal direction while the vertical plate tems are changing the world we live in. is moving 4.6 degrees in the vertical direc- Figure 2. Discontinuity of the resist over the Packaging of a MEMS device is considered tion. edge. www.meptec.org 30 MEPTEC REPORT / QUARTER TWO 2004 MEMS Technology

• Must have an opening for connection to expertise is in ultrasonic milling. Ultra- the substrate drive voltage bond pads. sonic milling uses high frequency vibrating • Real estate must be provided for pack- tools in conjunction with abrasive slurry to aging, bonding and alignment tolerances grind away material underneath the contact between the various components. points of the tool. By working closely with • The packaging components must be the supplier a design was conceived and able to withstand up to a temperature close wafers fabricated See Figure 4. to 425˚C to allow for the glass frit process. Optical Window These requirements are easily applied One of the more critical components of to the scanner wafer. The traces inside the an optical system is the window providing hermetic seal are routed from an internal the seal across the optical path. For the 6µm thick gold plated structure to the wafer level package this becomes an optical external wire bond pad using a thin sput- quality wafer. The requirements for it are as tered layer of gold and titanium-tungsten. follows: Next, the opening in the wafer to allow for • Anti-Reflective (AR) coated so that the Figure 3. A cross-section of the metal electrode easy access to the substrate wirebond pads desired wavelengths of light are transmitted as is traverses up and out of a 90um cavity. can be created at the same time that the mir- with limited loss or scatter. ror structure is released during the DRIE • Scratch/Dig specifications must be met. top surface in subsequent standard photo process. The most expensive requirement • The wafer and AR coating must be able process steps. Figure 1 is a cross-sectional is to sacrifice extra real estate on the scan- to survive a dicing and cleaning operation. image of the resulting slope of an isotropic ner wafer to allow room for the alignment • Flatness and total thickness variation etch using 49% HF. Figure 2 shows the and bonding process. The bond process is (TTV) must be specified to minimize im- resulting discontinuity of the standard 6µm completed using a glass frit that has similar pact to the shape of the light beam. resist process as it traverses over the slope. TCE properties as those of silicon and a Tg • Must be able to handle temperatures up To overcome this problem the process of less than 425˚C. The glass frit conforms to 425˚C. had to be customized so that the resulting easily over the thin metal traces and pro- • Strong enough not to deform signifi- slope of the etched cavity was compatible vides a very good and reliable seal. cantly under 14.4 psi across the optical with a standard 6µm photo process. See aperture. Figure 3. With this new etch process we Spacer wafer were able to deposit and pattern metal trac- This was one of the more challenging One of the biggest concerns was find- es into cavities 90µms deep and deeper. components. The requirements are as fol- ing an AR coating that would withstand This advanced etch process enabled a lows: temperatures of 425˚C for the duration simple hermetic seal with the scanner wafer • The thickness of the wafers needs to be of the Frit process without degrading the using glass frit which easily conforms to the 4mm thick for reasons related to the optical properties of the film. A series of test were topography of the substrate wafer. Because design. performed and a supplier was found to meet through hole vias are not required, this pro- • The wafer must allow clearance for the the requirements. cess is much easier to control and repro- mirror to move. Assembly duce. One impact of this process is that the • The wafer must not obstruct the wire scanner wafer needs to provide access for bond pads. With the components defined and avail- the wire bonder. To maintain the proper • The wafer must maintain a hermetic seal able, the bonding process can begin. First electrical isolation between the scanner between the scanner wafer and itself. the glass frit is patterned onto the substrate wafer and the substrate wafer, a 3µm layer • The thermal coefficient of expansion and spacer wafers using a screen printing of silicon dioxide is deposited over the must closely match that of silicon up to a process. These wafers are then fired to set/ capacitive drive electrodes. temperature close to 425˚C. glaze the glass frit. All components are then • The bonding surface of the spacer must loaded into tooling designed to maintain MEMS Scanner Wafer be as small as possible to minimize the alignment and the entire assembly is put The MEMS scanner wafer is the heart of space required on the scanner wafer for into a custom wafer bonder. The bonding Microvision’s imaging and image capture bonding. chamber is cycled from atmosphere to the devices. The MEMS scanner is designed to desired vacuum level and then allowed scan in both horizontal and vertical direc- The most challenging aspect of this tions (biaxial), so that a single beam of light component was finding a method to create can be precisely steered at very high speeds through holes in a 4mm wafer. The spacing to project a complete video image or used between adjacent holes was as narrow as as an optical sensor or camera by rapidly 0.8mm, causing some concern about struc- scanning light reflected from the surface of tural rigidity. Silicon was ruled out because an object onto a photoreceptor. Because the of yield loss and edge protection during goal is to provide hermetic packaging at the fabrication concerns. In addition, even if wafer level, a number of factors must be a silicon structure of this shape could be ac-counted for in the design and layout of manufactured, it would be expected to the MEMS device: be prone to breaking. Given that Pyrex is already em-ployed for the substrate wafer, • Must provide an electrical path for the it was the next obvious choice for the spac- sensors and drive coil outside of the her- er. These constraints and the design con- Figure 4. A completed ultrasonically milled metic seal. cept were presented to a company whose 4mm thick Pyrex wafer. www.meptec.org 31 MEPTEC REPORT / QUARTER TWO 2004 MEMS Technology

to dwell for a minimum of 2 hours at an cal window at the edge of the scanner unit elevated temperature to outgas the compo- to allow removal of the glass strips that are nents. The glass frit provides enough of a in the way. A final cut is made to singulate stand off and thickness variation to allow the assemblies. The optical window can each of the individual chambers on the easily be protected during the dicing opera- as-sembly to outgas and achieve the same tion with dicing tape. The final operation level of pressure. Once the assembly has requires careful cleaning of the bond pads, completed the purge cycle, the chamber is but the mirror and other electrical compo- brought to the proper pressure and tempera- nents are entirely isolated during the opera- ture for bonding to occur. The pressure at tion. This greatly simplifies the require- seal is increased slightly from the final tar- ments of the cleaning process compared to get seal pressure to account for the elevated a non-hermetic MEMS device. The shape temperature during the bond. To determine of the packaged device requires a special the sealing pressure a straight-forward cal- measurement system to test each device at Figure 6. A singulated wafer level vacuum culation is required using the following the die level but this testing can be limited packaged MEMS optical scanner with the formula: to determining the seal pressure and check- dicing tape removed. ing for any catastrophic damage that might Pseal = Ptarget x (Tchamber / Tatm) have occurred during the assembly. All and contributing to the assembly of the package, Jon other testing can happen at the wafer level Barger for dicing the first fully assembled package and Selso Luanava for support on the design drawings. Where Pseal is the pressure (Torr) of the prior to bonding. The dicing tape can be left chamber before the Tg (Kelvin) of the glass in place until the MEMS unit has been fully frit is surpassed, Ptarget (Torr) is the target mounted into its final assembly and then the pressure of the final assembly at room tem- tape removed. This provides protection to References: perature, Tchamber is the temperature (Kel- maintain a pristine optical window. Figure 1 - D. W. Wine, M. P. Helsel, L. Jenkins, H. Urey and vin) at which the seal is finally made and T. D. Osborn, “Performance of a Biaxial MEMS- 6 is a picture of a singulated device. Based Scanner for Microdisplay Applications”, Proc. Tatm is room temperature. It is assumed in Of SPIE Micromachining, Micromanufacturing and this calculation that the pre seal volume and Future Work Microelectronic Manufacturing 2000, Vol. 4178, pp. post seal volume are the same and can be Future efforts will be focused on reduc- 186-196, 2000. ignored. ing the thickness of the spacer wafer by 2 - Stephen D. Senturia, Microsystem Design, pp. 453- The assembly is compressed with a tilting or adjusting the optical window to 459, Kluwer Academic Press, USA, 2001. uniform load at the proper time and tem- di-rect the stray reflections from the inci- 3 - http://www.dlp.com/dlp_technology/dlp_technol- perature. This force is maintained through- dent beam angle in a preferred direction. ogy_white_papers.asp out the cooling process and released once At this time AR coatings are not good 4 - Mark P. Helsel, Jon D. Barger, David W. Wine, Thor the assembly is below 150˚C. In order to D. Osborn, “Wafer Scale Packaging for a MEMS Video enough to eliminate all reflections from Scanner”, Proceedings of SPIE MEMS Design, Fab- in-crease the cooling rate the chamber is the optical window and the resulting stray rication, Characterization, and Packaging, Vol. 4407, brought back up to one atmosphere. It is light must be clipped mechanically. By pp.214-220, 2001 important not to cool the assembly too tilting the optical window the reflection is 5 - A.R. Mirza and A. A. Ayon, “Silicon Wafer Bonding: quickly or damage to the bonds and subas- easier to eliminate. In addition, the costs to Key to MEMS High Volume Manufacturing”, Sensors, semblies might occur. The wafer is then manufacture the spacer will decrease with December 1998 removed from the tooling and is ready for a reduction in thickness. Newer designs to 6 - W. P. Maszara, G. Goetz, A. Caviglia and J. B. dicing. See Figure 5 for a completed assem- McKitterick, “Bonding of Silicon Wafers for Silicon- reduce the minimum sidewall width of the on-Insulator”, J. Appl. Phys., Vol. 64, pp. 4943-4950, bly. spacer and still make the component easy to 1988. manufacture are also in consideration. 7 - G. G. Goetz, “Generalized Reaction Bonding”, Dicing and Test Proceedings of the First International Symposium on Dicing of the assembly provides an Conclusions Semiconductor Wafer Bonding: Science, Technology additional complexity in that the top optical This work demonstrates that a wafer and Applications”, Proceedings Vol. 92-7, pp. 65-72, 1992. wafer is continuous and therefore blocks scale vacuum package is feasible. Further access to bond pad area. To account for this, work is required to make the process more 8 - A. L. Tiensuu, J. A. Sshweitz and S. Johnson, “In Situ Investigation of Precise High Strength Micro Assembly two cuts are made over the top of the opti- compatible with the latest system design. Using Au-Si Eutectic Bonding”, Proceedings of Trans- The aforementioned process requires four ducers ’95, Stockholm, Sweden, pp. 236-239, 1995. subcomponents that all add opportunities 9 - H. Quenzer and W. Benecke, “Low Temperature for yield loss, but when the assembly is Wafer Bonding”, Eurosensors, 1991. complete the package is very robust. Im- 10 - W. H. Ko, J. T. Suminto and G. J. Yeh, “Bonding proving the yield and cost on each of the Techniques for Microsensors”, Micromachining and subcomponents is essential to making this a Micropackaging of Transducers, pp. 41-61, Elsevier, Amsterdam, 1985. production worthy process. However, even at this early stage the cost at the component 11 - M. Esashi, A. Nakano, S. Shoji and H. Hebigu- chi, “Low-Temperature Silicon-to-Silicon Bonding with level is less than alternative packaging Intermediate Low Melting Point Glass”, Sensors and op-tions especially machined metal cans Actuators A, vol. A23, pp. 931-934, 1990. with a vacuum compatible sealed window. 12 - C.H. Tsau, M. A. Schmidt, and S. M. Spearing, ◆ “Characterization of Low Temperature, Wafer-Level Gold-Gold Thermocompression Bonds,” Materials Science of Microelectromechanical Systems (MEMS) Figure 5. A complete wafer level vacuum pack- Acknowledgements We would like to thank Lori Potts and Lloyd Johnson Devices II, pp. 171-182., Materials Research Society, age assembly. for their key contributions into making the substrates 1999. www.meptec.org 32 MEPTEC REPORT / QUARTER TWO 2004 Bringing you international coverage of microelectronic packaging and surface mount technology.

■ Advanced Packaging ■ Advanced Packaging China ■ Advanced Packaging Taiwan

■ SMT ■ SMT China ■ SMT Germany ■ Surface Mount Technology Korea

Measure Performance: Parts per Auer

Auer Precision is the premiere supplier of media handling products for: ■ Semiconductor Assembly (boats, carriers, magazines) ■ Opto-Electronic and MEMS assembly Warpage Analysis ■ Advanced Interconnect Technologies Wafer Handling (film frames, magazines) ■ is a global provider of semiconductor assembly BGA warp at 240˚C Consumables and test services for the world’s most successful AkroMetrix LLC’s TherMoiré® in-process In addition to this established line of products, electronics companies. Our company provides a warpage measurement and analysis system – Auer provides manufacturing services and solu- full turn-key solution with services that include: model PS88+. Fully automated shadow moiré tions in diverse markets: design and characterization, wafer probe and based system enables routine characterization of backgrind, assembly, test program development ■ Chemical/Genomic analytical equipment surface planarity at 0.1 mil (2.5 micron) sensitivi- components and final test as well as drop shipping and storage ties or better during time-temperature profiling ■ Pacemaker and Biosensor precision programs. A.I.T. offers an expansive portfolio of (i.e. curing, reflow, operation). Essential tool leaded and array packaging solutions including components for substrate/package development, qualification, ■ Flip Chip BGA, System-in-package (SIP) and reliability, FEA/FEM and failure analyses. Tem- Defense and Aerospace assemblies ■ our QFN package family. perature range: - 60˚ C to 300˚+ C. Collaborative product design and For more information about AIT, our prod- For more information about AkroMetrix and engineering ■ ucts and services visit our website or contact AIT their products email [email protected] or call Lean Automation at (408) 734-3222. 404-486-0880 in Atlanta, Georgia. Auer can deliver solutions tailored to your requirements. Let us show you how. For more information visit the Auer website, call 480-834-4637 or Fax 480-964-8337. www.aitsales.com www.warpfinder.com www.auerprecision.com

Test Handlers that give you the competitive edge

CAD Design Software offers complete ANALYTICAL SERVICES EDA Packaging Layout and Simulation tools for RELIABILITY TESTING Delta Design Advanced Packaging: TECHNICAL CONSULTING 12367 Crosthwaite Circle BGA • Stacked Die • Flip-chip Poway, CA 92064 Leadframe • MMIC DESIGN SERVICES 858-848-8000 µBGA™ • RF/Microwave • SEMS/EDS Pre-route Bond Wire Optimization improves bond wire yield rates. Advanced DRC includes • Thermal Conductivity Singapore more than 100 customized design and manufacturing checks from the world’s leading IC and • Failure Analysis 65-6-288-6949 packaging companies. Signal Integrity electrical • Mechanical Testing simulation during design. With the most advanced 3D graphics available, CDS provides • Thermal Stress Taiwan advanced solutions to leading-edge companies. • Environmental Stress 886-2-8226-2209 Fastest time-to-market layout designs, rapid ROI. CAD Design Software: Tempe, Arizona (480) 496-5120 Helping you work smarter, not harder. www.cad-design.com www.cmcinterconnect.com www.deltad.com www.meptec.org 34 MEPTEC REPORT / QUARTER TWO 2004 MEPTEC Network

Fusion of Automation & Test

FastSpares pioneering concept of a single source for customers to purchase spares via the Internet for production lines comprised of multiple equipment manufacturers provides one stop shopping. The comprehensive database listing parts by manufacturers name and model number allows maintenance and technical support personnel to quickly identify the fight part. This ability plus FastSpares strategically located warehouses around the world minimizes any potential down time for production lines. Dynaloy Inc. engineers and manufactures a variety of specialty chemistries for the electron- When you need spares fast…. AUTOMATED 200mm & 300mm DIE SORTING SOLUTIONS ics/semiconductor industries. A leading supplier Think FastSpares. 1200 SERIES of chemistries to the wafer bumping industry, ■ Die Sort Dynaloy’s unique product formulations include; • “Cluster Tool” Concept for aqueous, semi-aqueous and solvent based photo Backend Assembly resist removers, flux cleaners, PCB and stencil • Maximum Configurations & Flexibility cleaners and a wide range of other specialty ■ Process Integration materials for the microelectronics industry. • Mark Headquartered in Indianapolis Indiana, • Vision Inspection Dynaloy has world wide sales and technical • Test support capabilities with offices and warehouses • Multiple Binning in Phoenix, Taiwan, Korea, Singapore and the • UV Curing United Kingdom. For more information on Dynaloy products, ■ Secs/Gem Compliance visit their website or call at 1-800-669-5709. www.dymatix.com www.dynaloy.com www.fastspares.com

Hestia SIP PACKAGING

The only Flip Chip wafer bumping source Film and Wafer to combine Low Cost with High Quality.

Thickness Metrology ENGINEERING - PROTOTYPE - PRODUCTION IC Interconnect (ICI) is a U.S. based, global service provider to the semiconductor industry. Foothill Instruments, LLC Hestia Technologies, Inc. has been provid- provides film Distinguished as a flip chip and wafer level ing packages and sub-assemblies for multi-chip and wafer thickness metrology solutions for CSP technology leader in electroless nickel/gold packaging, hybrids and MCM’s for over 10 packaging, MEMS, semiconductor, and related under-bump-metallurgy and stencil printed sol- years. Hestia supplies packages for SIP applica- markets. Our film thickness tools are capable der. For the last 6 years ICI has been delivering tions in lead frame/substrate combination or in of measuring dielectrics such as SU-8 of thick- low cost/high quality contract wafer bumping organic substrates. ness greater than 500 microns and layers on services to the microelectronics industry. ICI’s If your packaging requirements call for mul- difficult Cu substrates. Our new wafer thickness philosophy minimizes cost while accommodat- tiple die, with active and or passive components products use breakthrough technology to enable ing the widest possible range of wafer configura- in either a lead frame or substrate based package wafer thickness measurements from 10 – 600 tions. ICI is ISO 9001 and QS 9000 certified and contact Hestia for its innovative and refreshing microns. This includes Si, GaAs, SOI, and prides itself on providing strong customer service approach to packaging. Hestia provides pack- bumped wafers. and engineering support to customers in the aging from inception through design, material Americas, Europe and Asia. For complete techni- selection, and specifications, along with proto- cal details and design guides, visit our website or type and production volume quantities. SEMICON West Booth #5782 contact Angie King at (719) 533-1030 ext. 10. San Francisco Contact Hal Shoemaker at (408) 844-8675 for more information. Building our Reputation on Performance… www.foothill-instruments.com www.hestiatechnologies.com www.icinterconnect.com www.meptec.org 35 MEPTEC REPORT / QUARTER TWO 2004 MEPTEC Network

Automatic DAF Laminator Model LH8360 Die Attach Film Laminator from Longhill Industries Ltd.: Adapting the Automatic Back Grind Tape & SEMI-Automatic 300mm Wafer Mounter proven Longhill roller-LESS vacuum laminating Photo Resist Film Laminator process to wafer scale packaging. DAF film and Model LH8320 Wafer/Substrate Mounter wafer are brought together in a vacuum chamber Model LH836 Back Grind Taper and Photo for Dicing Tape from Longhill Industries, with very high quality and uniform results. The Resist Film Laminator from Longhill Indus- Ltd., utilizing the unique and proven Longhill vacuum laminating process virtually eliminates tries, Ltd., utilizing the unique and proven vacuum mounting process, no troublesome roll- air bubbles captured between the film and the Long-hill vacuum laminating process, no trouble- ers to clean and adjust, the tape and wafer are wafer. Both DAF covering layers automatically some rollers to clean and adjust, the tape or film brought together inside a vacuum chamber. Easy removed prior to the laminating process, no post and wafer are brought together inside a vacuum change with options to alternate wafer and film laminating film removal required. The LH8360 chamber. Vacuum laminating is especially adapt- frames sizes. Pieces of wafer can be mounted is designed from the ground up with very thin ed to bumped wafers. During the vacuum lami- with ease. Film frames and wafers are opera- wafer capabilities. Input from cassettes or coin nating process there is a reduced atmosphere cap- tor loaded. The system automatically mounts stack wafer boxes. Equipped with a Bernoulli tured between the wafer surface and the tape, this the wa-fer and excises the film frame from the Effect wafer robotics, non contact alignment and effect causes the tape to more readily conform tape. Operator unloads finished product. Typi- tolerant of severely warped wafers. Program- evenly over the bumps, especially around the cally there is contact with the face of the wafer mable cutting blade cleanly excises the wafer wa-fer edge. Programmable 360° uniform tape only along the SEMI Specified non-active wafer from the film. Various curing and heat assisted tension minimizes wafer warp caused by uneven edge. Non-contact roller-LESS mounting is options can be implemented. Model LH8362, tape tension. Programmable cutter excises the especially advantageous when mounting wafers the 300mm capability version is also available. wafer from the tape leaving no strings, burrs or with bumps, 3D surface features or sensitive For more information and/or possible sample leftover tape protrusions. Double side laminating surface elements. preparation, contact: in one pass is added optional feature. Factory email: [email protected] Factory email: [email protected] Factory email: [email protected] Sales: [email protected] Sales: [email protected] Sales: [email protected] www.etcslaes.com www.etcslaes.com www.etcslaes.com

Automatic 300mm Wafer Mounter Model LH8600 Automatic 300mm Wafer Mounter from Longhill Industries Ltd., an-other example of the Longhill unique roller- LESS vacuum mounting and laminating systems. The wafer and the dicing tape are brought together in a vacuum chamber without the need for troublesome rollers. The sophisticated vac- 300mm Wafer Code Reader/Bar Code uum pro-cess is fully computer controlled and Printer & Applicator Automatic Wafer De-Taper very gentle with wafers. During the mounting Model LH8900 from Longhill Industries Model LH838 Wafer De-Taper from Long- process there is contact at the wafer face only Ltd. hill Industries, Ltd., around the SEMI Specified non active edge area, Stand alone system to read wafer codes/ remover tape is applied absolutely safe for bumped wafers. Wafer adhe- print-apply bar code labels. Programmable wafer onto the back grinding tape by a floating roller sion and resultantly die adhesion is excellent and code reader camera position and label application to minimize wafer stress. The uniquely designed improves shortly after mounting due to a reduced position. Labels can be applied to the film frame, peeling mechanism can accommodate very thin atmosphere captured between the wafer and the dicing tape alongside the wafer or on the wafer wafers. Wafer input by cassette or coin stack dicing tape. Available options: LH8600-XT it-self. Mounted wafer Input from film frame cas- wafer box. Non contact wafer centering with flat configured for extra thin wafers, FOUP or coin sette carrier. Convertible to 200mm wafers using or notch finder. the same 300mm wafer film frame. stack wafer box input, film frame cassette output, Options: UV irradiator for back grind tape release, De- Factory email: [email protected] • UV irradiator for UV release tape. Taper for back grind tape removal post mounting, Sales: [email protected] • Bernoulli robotics for very thin wafers. Wafer code reader/bar code printer with bar code • Double side de-taping in single pass. applicator. Factory email: [email protected] Factory email: [email protected] Sales: [email protected] Sales: [email protected] www.etcslaes.com www.etcslaes.com www.etcslaes.com

Visit Longhill Industries Ltd. at SEMICON West 2004 in San Jose - Booth #10319 MEPTEC Network

Operational Performance Excellent Results Reflect An Silicon Valley’s Premier Effective Process Packaging Foundry provides worldwide Integrated Packaging Assembly Corp. simple solutions for (IPAC) provides IC package assembly, testing accelerating your factory’s rate of improvement. and manufacturing support to the semiconductor Excellent Results: industry. The company’s manufacturing services • Active Management Metrics. are carried out at its Silicon Valley facility where • Customer’s Perception - “The Best to Buy from”. a wide range of package offerings are combined • Financial Performance. with superior service and fast delivery. • Cycle Times, Yield. Mitsui Chemicals, Inc. manufactures sub- IPAC’s domestic operations and experienced • Operator & Equipment Effectiveness. strates based on its BN300 high heat resistant material developed using Mitsui’s unique polym- staff bring a number of benefits to the semicon- Reflect the Process: erization technology. Mitsui BN300 material is ductor industry, including: • Enhance vital performance requirements by a high heat resistant glass fiber reinforced resin defining and maintaining a visible cascading with a glass transition temperature of 300˚C, a • Volume production in a domestic facility link of mission critical management and dielectric constant of 4.4 and low Z-axis CTE. functional disciplines. • Package selection - QFP, QFN, BGA The high heat resistance and low warpage chara- • Advanced technologies - CSP, Flip-Chip, • Achieve Manufacturing Excellence as a result of tristics of the BN300 is suitable for Flip Chip WLP, SiP modifying Man, Method & Machine Practices. substrates, Multi-Chip Modules and Ultra-Thin • Package & substrate design services • Institutionalize an “Operating System of packages. The BN300 is used in both the build- • “Hot Lot” services - quick as one-day Compliance” to maintain Visibility, Excellence up layer and the core, allowing the substrate to and Continuous Progress. • Superior customer service resist warpage and improve wirebonding strength due to its stiffness at higher temperature. Desire these results? Contact: Gary Lorenzen at [email protected]. www.ipac.com [email protected] www.mitsuichemicals.com/sem.htm

Underfill for Your Current and Future Requirements Pac Tech USA offers a full range of advanced • Low K Die packaging services in Santa Clara, California. • Lead Free Bumps Wafer Bumping • Fine Pitch ■ Maskless Orthodyne Electronics, a California based ■ Electroless Ni/Au under-bump metallization Corporation is a leading manufacturer of ultra- on Al or Cu pads Namics Corporation is a leading source for sonic wire and ribbon bonders for semiconductor ■ Solder and Au stud bumping and microelectronic applications. Recognized as high technology underfills, encapsulants, coat- ■ ings and specialty adhesives for use by the an industry leader, Orthodyne has been awarded 4- to 12-inch wafers producers of semiconductor devices. Headquar- for customer satisfaction in VLSI Research’s “10 ■ Eutectic solder Sn63/Pb37 tered in Niigata, Japan with subsidiaries in the BEST” list for 12 years in a row. ■ Leadfree solder SnAgCu USA, Europe and China, the company serves its ■ worldwide customers with enabling products for Low-alpha solder leading edge applications and superior technical ■ Second sourcing from Pac Tech GmbH support. Other Services For more information visit our website or call ■ Wafer sawing, thinning 408-907-8430. ■ Wafer backside marking/scribing ■ Flip-chip, BGA, CSP assembly

www.namics.co.jp www.orthodyne.com www.pactech-usa.com www.meptec.org 37 MEPTEC REPORT / QUARTER TWO 2004 MEPTEC Network

LEAD FREE SGP Ventures, Inc. is the exclusive North SOLDER SPHERES American sales agent for San-Ei Kagaku Co., Ltd., a Japanese manufacturer of chemicals used in the processing of Printed Wiring Boards.

The PHP-900 Series of non-conductive, solvent-free via fill materials is used worldwide by the leading PWB manufacturers for advanced build-up and area array package substrates. A new and complementary UC-3000 Series has been developed for the filling of vias and the gaps between circuit traces on the board surface, all in a single, simple process.

For more information about San-ei’s products, Profound Material Technology Co. Ltd. call 408-879-6224 or e-mail [email protected]. (Formally Sunball International) is a producer of high quality solder spheres for BGA and CSP Phoseon Technology offers the MX plat- packages and other interconnect applications. form for infrared imaging and automated inspec- Our solder spheres are available in alloys from tion of silicon structures for applications such as eutectic to lead free, in a variety of diameters to MEMS, Silicon on Insulator and Die Alignment. meet your requirements and applications. Our Phoseon’s Automated Optical Inspection (AOI) flexible approach enables us to meet your solder capability includes proprietary algorithms that sphere requirements by supplying a high qual- are used to enhance images and to identify and ity product with low oxidation, highly accurate classify defects. Several MX platform configu- sphere diameter and sphericity, better oxidation rations are available ranging from a fully auto- resistant along with quick delivery. Our factory is mated inspection system with a wafer autoloader ISO 9001, ISO 14001 and QS 9000 certified.Con- to a manual system. tact Hal Shoemaker at (408) 969-9918 for more information on our products and capabilities. www.phoseon.com www.sgpv.biz

Sonoscan® Sets “Off-the-Top” the Standard – Again!

IC Package Design Sonoscan’s applications division, SonoLab™, SiliconPipe is licensing a revolutionary new IC offers analytical and high volume nondestructive package technology that provides a path to screening services to save you money and keep Silicon Bandwidth provides performance- higher chip-to-chip interface speeds. your production lines operating. SonoLab, the enabling technologies that also reduce system ■ Up to 25Gbps world’s largest inspection service for Acous- costs. The eXo™ backplane/mezzanine con- tic Micro Imaging (AMI) of integrated circuit ■ nector delivers 50+ Gbps data rates and the No IC redesign necessary packaging, utilizes state-of-the-art AMI systems industry’s lowest crosstalk. Cluster Grid Array™ ■ Enabling higher levels of FPGA integration to provide solutions. Let SonoLab help set your sockets and CapCore™ interposers enhance ■ Eliminates impedance discontinuities standard for product quality! Whether you need power delivery and improve mechanical usabil- ■ to test a few components or screen through a ity, vastly increasing overall system performance. Virtually zero skew interconnects large quantity, such as 250,000 units, trust us with Deployed with Welltech™ PCB technology, ■ Ideal for gaming systems such as your inspection needs. these platforms even further enhance system PlayStation, Xbox, and multimedia set-top performance and reduce layer count, simplify For more information call 1-800-950-2638, lamination, liberate routing space, while lower- boxes. e-mail: [email protected], or visit the Sonoscan ing costs. For further information please phone 408-282-3500 Web site . 408-965-1260. www.siliconbandwidth.com www.sipipe.com www.sonoscan.com www.meptec.org 38 MEPTEC REPORT / QUARTER TWO 2004 and

present

The First Annual International Wafer-Level Packaging Congress™ October 10-12, 2004 • San Jose, Calif.

Co-Chairs:

Dr. Ken Gilleo Joseph Fjelstad ET-Trends LLC SiliconPipe

Keynote Address by Dr. W.R. “Bill” Bottoms, Third Millennium Test Solutions Terrence E. Thompson, Technical Liaison, Chip Scale Review

IWLPC ‘04 and exhibition will include a three-day technical program and two days of exhibits in the heart of Silicon Valley. This event will host the leaders and innovators in wafer-level and chip-scale packaging in an exciting, world-class assembly. Attendees will hear experts from the United States, Asia and Europe who are working at the leading edge of the technology.

A few of the WLP topics include: • WLP trends for the 21st Century • Interconnect Schemes for Gigascale Integration • Equipment Considerations • Packaging MEMS, MOEMS and Opto Devices • Materials • Lead and Lead-Free Processes • 3D Wafer Bonding • Test Strategies • Wafer Thinning and Bonding • Wafer-Level CSPs

Visit www.chipscalereview.com/iwlpc and smta.org for further details. And mark your calendar for the premiere conference of the semiconductor industry’s recovery year! West2004 Fueling the Industry Road to Recovery

July 12–14 | Wafer Processing | Moscone Center, San Francisco, CA July 14–16 | Final Manufacturing | San Jose Convention Center, San Jose, CA

SEMICON® West 2004 integrates education, information exchange and exhibi- tions through focused themes highlighting innovation and best practices. Learn the latest manufacturing methods, next generation processes and interact with other industry profes- sionals. The focused themes will Register for also feature keynote addresses SEMICON West from leading industry luminaries 2004— the largest and sharing their insight and exper- most tise. diverse meeting place Focused themes include: for the global • Fab Management microelectronics • Supply Chain Management • Test Assembly and Packaging industry. • International Technology Roadmap for Semiconductors

For a complete list of specialized themes and program details, visit: www.semi.org/semiconwest SEMICON

MEPTEC_05.04 SUNDAY MONDAY TUESDAY WEDNESDAY THURSDAY FRIDAY SATURDAY

1 2 3 4 5

6 7 8 9 10 11 12 SOUTHWEST MEPTEC LUNCHEON SUNNYVALE Dobson Ranch Inn MEPTEC LUNCHEON Mesa, AZ Ramada Silicon Valley 13 14 15 16 17 18 19 J U N E 2 0 0 2 20 21 22 23 24 25 26

FATHER’S DAY SUMMER BEGINS

27 28 29 30 1 2 3

4 5 6 7 8 9 10

INDEPENDENCE DAY

11 12 13 14 15 16 17

SEMICON WEST 2002 July 12–14 / Wafer Processing / San Francisco July 14–16 Final Manufacturing / San Jose

18 19 20 21 22 23 24 J U L Y 2 0 0 2

25 26 27 28 29 30 31

1 2 3 4 5 6 7

8 9 10 11 12 13 14

15 16 17 18 19 20 21 WAFER LEVEL PACKAGING INTERCONNECTS CONFERENCE The Westin Santa Clara Santa Clara, CA 22 30 23 31 24 25 26 27 28 AUGUST 2002

41 www.meptec.org MEPTEC REPORT / QUARTER TWO 2004 Editorial Everybody’s talking ‘bout the new sound, funny, but it’s still rock and roll to me…

Mark Hartung NW Regional Sales Manager Chip Supply, Inc.

uch has been said and writ- is starting up again with SiPs, one might abled designer’s to push their technological ten lately about the SiP, or wonder what happened to the MCM? The advantages to the max. Today’s SiP devices System in Package. Whether demise of the MCM was blamed on several will allow the designer to utilize the high- it is multiple die side by factors, not the least of which was the KGD est levels of technology without paying the side or stacked die, more debate. But there appears to be another price for a full custom chip containing an Mcompanies are starting to look at multi interesting factor that the MCM and the SiP entire system. There are companies that die packaging as a method of improving are starting to have in common, and that is have been building these circuits/systems performance, enhancing functionality, and the perception that they were created out for years have considered and met the chal- keeping costs (relatively) low. Additional- of thin air, with seemingly little regard or lenge of combining various die of vary- ly, time to market can be much faster using ing complexity within the same package. the SiP ap-proach versus the custom ASIC, These companies have succeeded without or SOC approach. SiP circuits can and the Holy Grail of KGD, and many of these will play an increasingly important role as History scholars companies have weathered the ups and ASIC costs continue to head upwards. As History scholars downs of the semiconductor industry to the major supplier of bare die, we at Chip re-main in business for the long term. Dur- Supply welcome any and all attention and oftenoften warnwarn thatthat ing a recent MEPTEC Symposium on SiP the increased demand for bare die devices I had the privilege of assembling a session and related testing and assembly services. ifif wewe ignoreignore thethe of four speakers that offered a combined 73 We believe that one of our most important years of multi die design and manufactur- roles is to empower potential users of bare pastpast wewe simplysimply ing experience. During this same sympo- die as well as empowering semiconductor sium one of the speakers in the first session manufacturers who are looking to offer repeatrepeat itit withwith referred to the “MCM Graveyard” and their products in bare die formats. We have listed several of the companies, started in been bridging the gap and providing bare similarsimilar results.results. the early nineties, that no longer exist. Con- die value added services for over twenty- spicuously absent from this list were the five years. You might ask, since the MCM companies that thrived integrating bare die and the SiP are somewhat younger than and continue to thrive today. Companies that, to whom have we been providing respect for the past. History scholars often such as Advanced Analog (now part of IR), these services? As the debate swells about warn that if we ignore the past we simply Maxtek Components, Hytek Microsystems, what definition of a SiP should be, and as repeat it with similar results. Will the SiP and Crane Interpoint are all companies that the call for standards inevitably comes, I meet with the same fate as the MCM for have been building multiple die packaging cannot help feel a sense of déjà vu all over this very reason? for numerous end market applications for again. There are a number of companies that many years, and continue to do so. Once Working within the microelectronics have been building SiP, formerly MCM, again at this symposium the discussions industry since the late eighties, I have had formerly hybrid circuits since the late six- had to do with KGD and it’s availability, the honor of watching this same debate be- ties. These advanced forms of packaging and there seemed to be a distinct lack of fore. At times, it is hard to find a definitive have all arisen due to a need for solutions interest in discussing the prior experience start and end to the debate about multi-die that are not readily available off the shelf of engineers that have been building multi- packaging. During one point in the early to the designer, or are not available at the die packaging for years without it. nineties many companies began to “dis- costs necessary to move the application The engineers that have worked for cover” the advantages of the multichip off the drawing board and into the market- years in the “old” hybrid industry have module, much the way that Columbus “dis- place. There are those who claim that the traveled this road before and continue to covered” America. New companies were Hybrid was unlike the MCM, which in turn travel it today. They have an important started, new standards were discussed, is unlike the SiP, but one cannot ignore the contribution to make to the newer SiP pro- forecasts were promulgated, and the possi- fact that all have varying degrees of inte- ponents if, and when, they decide to take bilities seemed endless. Now that the cycle gration of bare die. Yesterday’s hybrids en- advantage. ◆ www.meptec.org 42 MEPTEC REPORT / QUARTER TWO 2004 Magazines and Carriers for Process Handling Solutions

Film Frames Film Frame Film Frame Shippers Grip Rings Magazines

Grip Ring Magazines Grip Ring Shippers Lead Frame Stack Magazines - E.O.L. Magazines - F.O.L./E.O.L.

Process Carriers Boat Magazines I. C. Trays - I. C. Tubes and Rails (Boats) Multi-Channel

Miscellaneous Substrate Carrier TO Tapes & Wafer Carriers Magazines Magazines Magazines

Accept Nothing Less.

Perfection Products Inc. 1320 S. Indianapolis Ave. • Lebanon, IN 46052 Phone: (765) 482-7786 • Fax: (765) 482-7792 Check out our Website: www.perfection-products.com Email: [email protected] the idea:

High performance flip chip underfills for lead-free, fine pitch and low K die.

Introducing Staychip™ Capillary and No Flow Underfills.

Staychip Capillary Underfills • Superior high temperature adhesion for JEDEC 3/260 and lead-free • Low warpage appropriate for large die • Minimal induced stress for low K die

Staychip No Flow Underfills • Compatible with standard eutectic and lead-free reflows • Not limited by pitch, gap or die size • Void free assembly

To find out how this advanced new line of Staychip Underfills can help you maximize productivity while meeting today’s packaging requirements, call 678-624-7391 or visit www.cooksonsemi.com.