(12) United States Patent (1O) Patent No.: US 7,489,538 B2 Mari Et Al
mu uuuu ui iiui iiui mu mil uui uui lull uui uuii uu uii mi (12) United States Patent (1o) Patent No.: US 7,489,538 B2 Mari et al. (45) Date of Patent: Feb. 10, 2009 (54) RADIATION TOLERANT COMBINATIONAL 5,406,513 A * 4/1995 Canafis et al . .............. 365/181 LOGIC CELL (Continued) (75) Inventors: Gary R. Maki, Post Falls, ID (US); OTHER PUBLICATIONS Jody W. Gambles, Post Falls, ID (US); Sterling Whitaker, Albuquerque, NM "Ionizing Radiation Effects in MOS Devices and Circuits", Edited by (US) T.P. Ma., Department of Electrical Engineering, Yale University, New Haven Connecticut and Paul V. Dressendorfer, Sandia National (73) Assignee: University of Idaho, Moscow, ID (US) Laboratories, Albuquerque, NM, A Wiley-Interscience Publication, John Wiley & Sons, pp. 484-589. (*) Notice: Subject to any disclaimer, the term of this (Continued) patent is extended or adjusted under 35 U.S.C. 154(b) by 263 days. Primary Examiner Vu A Le (74) Attorney, Agent, or Firm Haverstock & Owens LLP (21) Appl. No.: 11/527,375 (57) ABSTRACT (22) Filed: Sep. 25, 2006 A system has a reduced sensitivity to Single Event Upset (65) Prior Publication Data and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system US 2007/0109865 Al May 17, 2007 includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The Related U.S. Application Data logic block is for implementing a logic function, receiving a (60) Provisional application No. 60/736,979, filed on Nov.
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