Cadence Virtuoso DFM In-Design Manufacturing Signoff at Advanced Nodes

Cadence Virtuoso DFM In-design manufacturing signoff at advanced nodes

Cadence® Virtuoso® DFM gives designers the ability to accurately assess the design’s manufacturability for both physical and electrical variability for custom and mixed-signal designs, libraries, and IPs. Designers can now achieve speedy silicon convergence—without ever leaving the Virtuoso Layout Suite environment.

Advanced-Node When design teams migrate to In-Design DFM Experience For Manufacturability And advanced integrated circuit (IC) Custom Flow Implementation Variability Yield Loss process nodes to increase performance while reducing area and To meet the design-for-manufacturing At the 45nm technology process, power, layout-dependent effect (LDE) (DFM) requirements of advanced foundries have added mandatory variability can compromise the timing, nodes, Virtuoso DFM delivers ground- DFM checks to address lithography, performance, and predictability. LDE breaking in-design DFM technology etch, and mask systematic-manufac- variability caused by stress, litho, in the Virtuoso Layout Suite cockpit. turing variations that surpass random and well-proximity effects change Virtuoso DFM provides detection and variations as the prime limiters to transistor electrical performance and automated optimization of physical catastrophic and parametric yield can only be detected after layout and electrical variability so custom loss. The interaction of manufacturing completion, parasitic extraction, and and library designers can easily meet shapes within the optical proximity simulation. This is because there is no foundry mandatory checks. halo and the lithography projection feedback during the layout-creation This Cadence solution integrates systems creates highly non-linear process between the different tools, award-winning, foundry “golden” systematic variations at different leading to costly iterations and technologies enabling the fastest process conditions that cannot be parametric yield loss. Most IC design deterministic path to DFM conver- captured by a rules-based approach. teams handle LDE-induced variability gence for custom designers’ silicon The minimum design rule check (DRC) by simply applying guardbands. realization. Virtuoso DFM preserves rules fail to capture many potential design intent (such as electrical yield issues, while relaxing DRC rules Starting at 45nm to 40nm process constraints), achieves fast conver- causes an unacceptable increase in nodes, comprehending DFM goes gence through accurate abstraction, design area. These systematic shape from a “nice-to-have” to a “must- and provides highly convergent results variations are dependent on specific have” and is a mandatory step in the through near-linear scalability and layout-shape context, and result in IC design flow. Due to the increasing automatic fixing of errors. This enables predictable catastrophic errors such as design cost and time-to-market engineers to implement a “correct-by- necking (opens) and bridging (shorts). pressure, a redesign or a few weeks’ design” flow for their leading-edge These yield-limiting patterns must be delay because of poor yield could lead designs, efficiently and predictably, to detected and fixed prior to tapeout. to the financial death of a project or losing a market-window opportunity. multiple foundry partners. Cadence Virtuoso DFM

• Improves systematic and parametric Industry’s first in-design, constraint- Schematic yield and chip performance by driven layout-dependent-effects variability Conventional accurately determining the impact of detection and optimization Custom Flow Simulation systematic variations during design • Static checks detect large current or Vt Production-proven “golden” pattern variations due to LDE, without running Pass? Yes, continue matcher for in-design DRC+ for extraction or simulation GLOBALFOUNDRIES 28nm • Generated guidelines drive layout Layout • Uses foundry-certified library of yield- modifications detractors or customer-specific yield- • Supports Cadence proprietary and Extraction Identify root detractor pattern library cause of failure third-party litho and stress modeling • Quickly detects litho-unfriendly • Enables designer to verify that the Simulation patterns or yield detractors and layout meets intended matching Costly automatically fixes litho violations No Iteration constraints while layout is being Pass? • Applies recommended DFM rules locally constructed to matched areas • Integrates with Cadence QRC Figure 1: Lack of feedback between tools during • Delivers convergent silicon realization Extraction for contour-based transistor layout creation leads to costly iterations and parametric yield loss in-design with multiple fixing heuristics extraction Virtuoso DFM allows designers to identify, • Provides incremental recheck after Boosted productivity and predictable analyze, and automatically optimize the fixing tapeout schedules design on chip parameters for the impact Foundry-golden, comprehensive, model- • Near-linear multi-CPU scalability of physical effects such as lithography, based litho hotspot analysis enables fastest time-to-convergence mask, OPC, etch, and RET; as well as layout-dependent effects such as litho, • Quickly detects litho hotspots • Hierarchical methodology ensures easy overlay, context-dependent stress, strain, path for engineering change orders • Automatically fixes litho violations and well proximity, unintentional stressors like (ECOs) performs incremental rechecks/fixes shallow-trench isolation, contact-to-contact • Performs incremental and what-if spacing, and more. In addition, the Virtuoso analysis and exploration in-design methodology provides an accurate, model-based flow for designers to minimize the impact of manufacturing variations on design performance.

Benefits

In-design DFM and predictable DFM closure for custom-design implementation Yield Detractor or Litho Hotspot • Provides fastest deterministic path to physical and electrical DFM variability convergence

• Enables ease-of-setup and ease-of-use

• Offers flexibility to choose DFM signoff technology depending on technology Automatic Fix – node and foundry partner One at a Time or All Litho Hotspots • Provides seamless error reviewing and automatic fixing of errors within the Virtuoso environment

• Enables convergent automated fixing with on-the-fly, post-fix checks Hints and Guidelines Figure 2: Virtuoso DFM delivers a true in-design experience for detecting and fixing yield-detractors patterns or litho hotspots

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with GLOBALFOUNDRIES in the devel- Virtuoso DFM also enables in-design Schematic opment of DRC+ flow, which leverages litho hotspot detection and correction. Variability- Cadence pattern-classification technology The built-in foundry-golden Litho Aware Simulation to classify yield detractors into pattern Physical Analyzer delivers model-based Custom Flow families, and Cadence pattern-matching litho hotspot analysis fast enough to let technology to find the yield detractors designers uncover yield critical hotspots Pass? Yes, continue on designs. Designers can use their own during custom-design implementation. yield-detractor pattern library or foundry- Again, with a few clicks in the GUI Layout Quick Iteration certified pattern library to use fast, designers can perform real-time automatic Layout-Dependent production-proven 2D pattern matching fixing for each hotspot or all hotspots in Virtuoso DFM Effects Analysis and Fixing to search the design for potential yield one shot with an automated recheck to detractors. With just a few clicks in the ensure no new hotspots were created. GUI, designers can perform automatic Extraction In-design, constraint-driven, layout- fixing for each error at a time or all in one shot, with an automated recheck to dependent-effects variability analysis Simulation ensure no new hotspots were created. and optimization The targeted application of relaxed DRCs At advanced nodes, a leading cause of Pass? at identified critical locations improves systematic variability is the application of printability and yield without sacrificing mechanical stress to transistors. Stress is Figure 3: In-design LDE variability analysis on design area. commonly used to enhance performance incomplete layout in CMOS ICs, but it also causes layout- dependent variability that can make it Features

Golden pattern matching and model-based litho hotspot engines

Traditional approaches to dealing with manufacturing variations are no longer adequate. DRC alone does not prevent catastrophic yield loss due to systematic shape variations. In addition, DRC rules to address growing DFM issues become prohibitive in number and complexity. Post-GDSII OPC uncovers printability problems that frequently require actual design changes when there is limited freedom after tapeout, making design closure unpredictable. Designers can Virtuoso DFM restrict their design style in an attempt Layout-Dependent Variability Violations and Fixing Guidelines to improve yield, but this method limits Effect Analysis the use of leading-edge processes that optimize area and performance.

For advanced nodes to achieve the fastest path to DFM convergence, designers need the flexibility to choose technologies ranging from pattern matching, hybrid litho analysis to full model-based litho analysis. Virtuoso DFM incorporates these three types of analyses.

In-design DRC+ and litho hotspots analysis and fixing

Virtuoso DFM enables in-design DRC+, an innovative DFM approach launched by GLOBALFOUNDRIES for 28nm. Cadence Figure 4: In-design LDE analysis indicates the root cause and fix with Virtuoso has been an early development partner

www.cadence.com 3 Cadence Virtuoso DFM difficult to close timing. The variability of stress is the problem—not the stress itself. But stress is also unintentionally induced through various technologies such as shallow trench isolation (STI), a widely Constraints used technique that uses oxide to isolate (Ex: Matching) transistors. The well proximity effect (WPE) results from the location of well bound- Variability Violations and Fixing Guidelines aries with respect to transistors. WPE is not match a stress effect, but it does impact mobility and threshold voltage, and it is a proximity effect that impacts the stress liner. These Is match effects and others constitute what is Virtuoso DFM known as LDE variability. Layout-Dependent Effect Analysis master Evaluating LDE variability is not straight- slave 2*Ibias forward, because the evaluation must LDE-aware current matching consider “proximity effects.” This means Differential Pair Schematic that designers can’t just look at transistors in isolation. The location and dimen- sions of neighboring layout features change the surrounding stress, creating mismatches between the layout and the schematic—resulting in long iteration loops and delayed time to market. These loops can be painstakingly long for an analog designer as they go from completed layout to extract stress parameters, and then run Figure 5: Constraint-driven, layout-dependent, effect-aware analysis full simulation to complete a loop.

Virtuoso DFM integrates silicon-accurate, Comprehensive foundry support Specifications layout-dependent-effect electrical analyzer technology to deliver in-design Cadence signoff DFM technologies are Foundry support LDE analysis and optimization. With certified by leading foundries and are • Certified and supported by leading Virtuoso DFM, designers can perform also the internal tool of choice at multiple foundries and IDMs layout-dependent-effect electrical analysis foundries. Cadence pattern matching during the creation of the layout, without analysis is the golden internal pattern • Flow-tested and qualified with foundry requiring a complete layout and full matching engine to support the leading DFM design kits (DDKs) and yield- simulation information. Virtuoso DFM 28nm DRC+ flow. Cadence Litho Physical detractor libraries performs a static check on the transistor Analyzer is the golden engine at major Platforms layout to quantify the impact of layout- foundries and their customers to system- dependent effects on transistor current, atically detect hotspots on designs prior • Linux (32-bit, 64-bit) and then excessive variations are flagged to manufacturing. Layout-dependent- and reported to the layout designer for effect electrical analyzer has proven to layout optimization. deliver silicon accurate variability analysis and is used by leading foundries and IDMs Virtuoso DFM also supports designer’s to characterize their libraries for stress- constraint-driven, layout-dependent- proximity effects. effect variability analysis. Designers verify that the layout meets intended matching constraints while layout is being constructed, and provide guidelines to drive layout modifications to mitigate the layout dependent effects.

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Cadence Services And Support

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