UltraFast Design Methodology Quick Reference Guide (UG1231)

INTRODUCTION BOARD AND DEVICE PLANNING DESIGN ENTRY AND IMPLEMENTATION The UltraFast™ Design Methodology is a set of best PCB Designer FPGA Designer Logic Designer practices recommended by Xilinx to maximize productivity and reduce design iterations of complex systems, including Examine Key Interfaces Analyze Device for Pinout Define a Good Design Hierarchy embedded processor subsystems, analog and digital . Validate part orientation . Examine transceiver and . Define relevant hierarchies to help global placement and processing, high-speed connectivity, and network and key interfaces bonded I/O locations floorplanning . Examine SSI technology I/O . Insert I/O and clock components near the top level processing. See the UltraFast Design Methodology Guide for Examine the PCB Layout planning . Add registers at main hierarchical boundaries the Vivado Design Suite (UG949) for more information. . Perform the Memory Interface and Transceiver . Validate part orientation . Generate IP and review target device utilization The UltraFast Design Methodology Checklist (XTP301) Checklists and key interfaces Build and Validate RTL Submodules includes common questions that highlight typical areas . Follow PCB layout Define I/O Pinouts for Key . Ensure design adheres to RTL coding guidelines where design decisions have downstream consequences recommendations Interfaces . Add sufficient registers around DSP and memories and draws attention to potential problems that are often . Ensure final FPGA pinout is . Create I/O planning projects . Use control signals only when absolutely necessary unknown or ignored. It provides easy access to related signed off by FPGA . Define and validate memory . Use synthesis attributes to control final logic mapping controllers, GTs, and PCIe® . Create simple timing constraints to review estimated collateral. The checklist is available within the Xilinx designer technology locations timing and address paths with too many logic levels Documentation Navigator tool (DocNav). Review the Schematic . Establish a clocking skeleton . Review synthesis log files, utilization report, and . Complete PCB Checklist . Minimize floorplan distance elaborated view to identify sub-optimal mapping This quick reference guide highlights key design review between connected IP . Run Methodology and RTL checks and review issues methodology steps to achieve quicker system integration . Check PDS, configuration, . Implement the submodule in out-of-context (OOC) mode and design implementation and to derive the greatest value and power supplies Define Final Pinout to validate implemented performance from Xilinx® devices and tools. Pointers to related collateral . Validate I/O state before, . Merge interface projects . Review utilization and power against original budget are also provided. The main design tasks covered in this during, and after into a final I/O project . Validate DRCs and SSN . Simulate the design to validate functionality guide include: configuration analysis Assemble and Validate Top-Level Design . Board and Device Planning Manufacture and Test . Implement design to check . Synthesize the top-level RTL design and resolve all . Verify the configuration . Design Entry and Implementation clocking and I/O rules connectivity issues sequence, power supplies, . Top-Level Design Validation . Use the final I/O project for . Review top-level utilization and clocking guidelines and I/O performance with . Design Analysis production test . Create and validate top-level constraints the test I/O project . Design Closure Estimate Power . Iterate the RTL and constraints to fix Methodology and DRC issues and meet timing Refer to the UltraFast Design Methodology – System-Level . Determine power budget and thermal margin using . Proceed to implementation Design Flow available within the Xilinx Documentation Xilinx Power Estimator (XPE) Navigator tool (DocNav) for pointers to all design hubs and . Apply toggle rates using specific collateral. See Also: See Also: knowledge of prior designs UG949: Design Creation and Implementation UG949: Board and Device Planning See Also: Designing with IP Design Hub PCB Design Checklist UG949: Board and Device Planning Using IP Integrator Design Hub Memory Interface IP Design Power Estimation and Optimization Logic Synthesis Design Hub Checklists Design Hub Applying Design Constraints Design Hub Schematic Design Checklists I/O and Clock Planning Design Hub Implementation Design Hub

UG1231 (v2019.2) October 30, 2019 UltraFast Design Methodology Quick Reference Guide (UG1231)

TOP-LEVEL CONSTRAINTS VALIDATION DESIGN ANALYSIS AND CLOSURE Baseline the Design Identify Timing Violation Root Causes Reduce Control Sets . Validate timing closure feasibility early in the design . Try report_qor_suggestions for automated analysis and . Avoid MAX_FANOUT on control signals process after most blocks and key IP are available timing closure recommendations . Increase synthesis control set threshold . Specify essential constraints only: . Use report_timing_summary or . Merge equivalent control signals with opt_design . Use all IP constraints report_design_analysis to find the root cause Optimize High Fanout Nets . Define realistic primary and generated clocks . For setup paths, check for high datapath delay due to: . Use hierarchy-based register replication in RTL . Define all clock domain crossing constraints . Large cell delay (7 series > 25%, UltraScale devices > 50%) . Use opt_design -merge_equivalent_drivers . Add multicycle paths where required . Large net delay (7 series > 75%, UltraScale devices > 50%) -hier_fanout_limit for replication efficiency . Do not use I/O constraints at this stage . For hold paths, check for hold requirement > 0 ns . Promote to global clocking if not critical . Ensure path requirements are reasonable . Check for high clock skew (> 500 ps), high clock uncertainty . Force replication with phys_opt_design . Validate WNS ≈ 0.0 ns using report_timing_summary at (> 200 ps), or both Address Congestion each stage of the flow: Reduce Logic Delay . Lower device utilization and balance SLR utilization . After synthesis . Modify RTL to use parallel or efficient operators . Try placer directives AltSpreadLogic* or SSI_Spread* . Before placement . Add pipeline registers and use synthesis retiming . Identify congested modules with . Before and after routing . Add registers on DSP or block RAM outputs report_design_analysis -complexity -congestion . Address timing violations early in the flow . Use LUT_REMAP to collapse small LUTs in the longest path . For congested modules, use the AlternateRoutability . Fix QoR issues in RTL and synthesis for the biggest impact . Pull registers out of the SRL on the SRL input, output, or both block-level synthesis strategy, reduce MUXF*/CARRY* with Validate Timing Constraints . Remove KEEP/DONT_TOUCH/MARK_DEBUG opt_design, or use the CELL_BLOAT_FACTOR property . Run report_timing_summary or check_timing to Reduce Net Delay . Use global clocking for high fanout nets in congested regions ensure all clocks are defined and all registers, input ports, . Review and adjust floorplan constraints . Reuse DSP and block RAM placement from previous and output ports are constrained . Optimize high fanout nets implementations with low congestion . Run report_methodology and address all TIMING* and . Address congestion if level > 4 is reported in: Tune the Compilation Flow XDC* issues . report_design_analysis placer congestion table . Try several place_design directives . Run report_clock_interaction to ensure each clock . Initial estimated router congestion in log file . Use block-level synthesis strategies for an optimal netlist pair is safely timed with reasonable path requirements Reduce Clock Skew . Overconstrain critical clocks during placement and physical . Run report_cdc to verify all asynchronous clock domain . Use parallel buffers instead of cascaded buffers optimization with set_clock_uncertainty crossing paths are properly constrained and use safe . Use CLOCK_DELAY_GROUP between synchronous clocks . Use incremental compile after minor design modifications to synchronization circuitry originating from the same input or PLL preserve QoR and improve runtime . Run report_exceptions to identify timing exceptions . Add timing exceptions between asynchronous clocks that overlap, are ignored, or are inefficient Analyze and Optimize Power Reduce Clock Uncertainty . Constrain activity, environment, and process . Ensure all Critical Warnings are resolved when the design is loaded and constraints are applied . Optimize MMCM settings . Try power_opt to reduce power consumption . Divide clocks with BUFGCE_DIV in UltraScale™ devices . Maximize use of block RAM cascading See Also: See Also: UG949: Design Closure See Also: UG949: Implementation and Design Closure . Checking That Your Design is Properly Constrained UG949: Design Closure . Analyzing and Resolving Timing Violations . Baselining The Design . Understanding Timing Reports . Applying Common Timing Closure Techniques Applying Design Constraints Design Hub . Identifying Timing Violations Root Cause Implementation Design Hub Timing Closure and Design Analysis Design Hub Timing Closure and Design Analysis Design Hub Timing Closure and Design Analysis Design Hub

UG1231 (v2019.2) October 30, 2019