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Constraint Driven I/O Planning and Placement for Chip-Package Co-Design ∗

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Constraint Driven I/O Planning and Placement for Chip-Package Co-Design ∗ Constraint Driven I/O Planning and Placement for Chip-package Co-design ∗ Jinjun Xiong1 Yiu-Chung Wong2 Egino Sarto2 Lei He1 EE Department, University of California at Los Angeles1, CA 90095, USA Rio Design Automation, Inc.2, Santa Clara, CA 95054, USA ABSTRACT support chip-package co-design. Moreover, I/O placement System-on-chip and system-in-package result in increased also needs to address many issues on timing closure, signal number of I/O cells and complicated constraints for both integrity (SI) and power integrity for chip-package co-design. chip designs and package designs. This renders the tradi- To tackle these problems, complicated design constraints are tional manually tuned and chip-centered I/O designs subop- generated in practice to guide the I/O placement. However, timal in terms of both turn around time and design quality. to the best of our knowledge, there is no study on I/O place- In this paper we formally introduce a set of design con- ment in the literature that has formally considered these straints suitable for chip-package co-design. We formulate a real design constraints [2, 3, 6, 7] except [8], where only I/O constraint-driven I/O planning and placement problem, and standard compatibility constraints are considered for FPGA solve it by a multi-step algorithm based upon integer linear I/O placement. By making use of FPGA restricted but well- programming. Experiment results using real industry de- defined regular structures, [8] proposed to solve it via integer signs show that the proposed algorithm can effectively find linear programming. However, for high speed ASIC designs, a large scale I/O placement solution and satisfy all given design constraints on I/O placement are more complicated design constraints in less than 10 minutes. In contrast, the than those in FPGA. state-of-the-art without considering those design constraints The major contributions of this work include: (1) a for- simply cannot meet all design constraints by relying solely mal definition of a set of design constraints suitable for upon the conventional iterative approach. chip-package co-design; (2) a new formulation of constraint- driven I/O placement problem (CIOP ); and (3) an effec- tive multi-step algorithm to solve CIOP for chip-package 1. INTRODUCTION co-design. To the best of our knowledge, it is the first au- I/O placement plays a key role as the interface between tomatic I/O planning and placement algorithm available in chip and package designs in a co-design flow. I/O placement industry for chip-package co-design. not only significantly affects chip performance, but also de- termines the feasibility of package designs. Moreover, be- 2. PRELIMINARY cause the manufacturing cost is proportional to the number In traditional wire-bonding designs, I/O cells are placed of routing layers used for both chips and packages, a good on chip boundaries and I/O pads on these cells are then I/O placement not only helps to achieve design closure, but bonded to the substrate through wires. Because of the lim- also reduces the number of layers. However, because of the ited boundary area, the number of I/O cells is also limited. ever-increasing requirement for functionality, the number of Moreover, high inductance and high crosstalk effects due to I/O cells in a single die keeps increasing, rendering tradi- wire bonding also limit the use of this traditional packaging tional manually tuned I/O placement extremely difficult. technique in today's high performance IC designs. Recently, flip-chip packaging emerges as an increasingly ¦ § ¥ £ ! ¥ £ £ ¥ " £ popular alternative technology for many high performance ¥ IC designs [1]. Compared to wire-bonding packaging, flip- § £¦ ¡ £ chip technology allows shorter connection between chips and packages and it permits more I/O cells to be implemented on the die. However, flip-chip packaging also brings many new ¢ £ design challenges for I/O placement. For example, instead of being restricted to chip peripherals, I/O cells now can be ¢¡ £ ¥ $ £ placed anywhere on the die, and the placement of I/O cells ¤# § % ¡ $ £ also needs to consider the bump locations on the package ¤¦¥ § ¨ ¥ © £ & ' ( ) ( in order to minimize the number of extra die layers for con- & necting I/O cells to the bumps. Therefore, the traditional timing-driven I/O placement formulation [2, 3, 4, 5] with- out considering package design issues is no longer applicable. Figure 1: Area I/O Flip-chip design. A more realistic I/O placement formulation is necessary to On the contrary, flip-chip technology eliminates wires for ∗ This work was partially supported by NSF award CCR- chip-package bonding. The bonding is achieved through 0093273/0401682. bumps via the surface mount technology (SMT). As shown in Figure 1, I/O cells are first connected to bumps on the be other set(s) of P/G driver cells that may supply power die via redistribution layer (RDL) routing, then the die is at levels different from those of the primary P/G cells, and \flipped" and mounted on the surface of the substrate, where are required for either SI or power integrity concerns. We bumps are connected to bump pads on the substrate. Finally, call these P/G cells as secondary P/G cells. Examples of package trace routing is performed to furnish the connection secondary P/G cells include pre-drive power cells, reference between bump pads to balls (or package pins). Because of power cells, and core power cells. In practice, it is required the pitch mis-match between bumps (on the chip side) and that a ratio between the number of I/O cells to the number balls (on the package side), package trace routing can be of neighboring P/G cells (the so-called signal-power-ground further divided into two parts. The first part is routing ratio, or SPG ratio) be maintained such that the design can traces under the die, which is called escape route as its main have a reliable power supply. Different SPG ratios may be goal is to escape traces from the die through an appropri- derived for different groups of signal I/O cells. ate number of substrate layers. The second part is routing traces after escaping and we call it substrate route. Pack- 3.2 Timing Constraints age trace routing is preferred to be planar, as it not only It is observed that substrate routes in a package vary sig- reduces the number of high cost buried vias on the package, nificantly. For example, for a typical chip size, the sub- but also makes timing and SI analysis more predictable as strate route length can span from 1mm up to 21mm. One transmission line modeling can be used for package traces. of the impacts of such variation is on timing measured from I/O cells to package pins. Through 3D EM simulation [9], 3. I/O PLACEMENT CONSTRAINTS we find that ignoring package substrate route length vari- ation per se can impact the timing by more than 70ps for To tackle timing closure, signal integrity, and power in- 2.5V SSTL 2 [10] I/O cells. In another words, different sub- tegrity problems resulting from chip-package co-design, com- strate route lengths result in significantly different delays. plicated design constraints are generated in practice to guide If power supply variation and package stackup variation are I/O placement. We discuss some of the common design con- taken into account, more significant delay variation would straints that we encountered in a number of real industrial exhibit, making timing closure extremely difficult to attain. designs in this section. Therefore, for I/O cells that have critical timing relations 3.1 Power Integrity Constraints like differential pairs, we have to take this delay variation into account when we place them. A common practice is Signal I/O cells' voltage specification describes the nomi- to place differential pairs close to each other so that the nal voltage level as well as various voltage levels associated corresponding package routes will have similar route length. with the signal switching, like the allowable voltage over- shoots, undershoots and ring-back values. All signal I/O 3.3 I/O Standard Related Constraints cells that share the common power and ground nets fall into It is not unusual to see that a number of common I/O one power domain, and they are expected to be physically interfaces are implemented in the same chip in today's high- placed close to each other. speed IC designs (e.g., DDR2, SSTL, PCI-express, Serdes). Moreover, in order to provide good reference planes for Each I/O interface has its own specification on the relative signal I/O traces in the package, the power/ground planes timing requirements for signals within that interface (like in the package have to be cut based upon I/O cells' power differential pairs). Moreover, because all signals belonging domain properties and their physical locations. For exam- to the same I/O interface will be very likely routed to the ple, the power/ground planes in Figure 2 are cut into three same I/O interface in other chips on the PCB, it is desir- parts by the plane cut-lines. How to define plane cut-lines able to have the I/O cells belonging to the same interface heavily depends on the physical locations of I/O cells. If no physically close to each other (or even in a preferred order), attention were paid to I/O cells power domain constraints, which reduces the delay and SI variations between signals I/O cells might scatter all over the die, which means that of the same interface.
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