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Designing a Chip Challenges, Trends, and Latin America Opportunity Designing a chip Challenges, Trends, and Latin America Opportunity Victor Grimblatt R&D Group Director © Synopsys 2012 1 SASE 2012 Agenda Introduction The Evolution of Synthesis SoC IC Design Methodology New Techniques and Challenges IP Market, an opportunity for Latin America © Synopsys 2012 2 Introduction © Synopsys 2012 3 Interesting Facts from Cisco • Last year’s mobile data traffic eight times the size of the entire global Internet in 2000 • Global mobile data traffic grew 2.3-fold in 2011, more than doubling for 4th year in a row • Mobile video traffic exceeded 50% for the first time in 2011 • Average smartphone usage nearly tripled in 2011 • In 2011, a 4th generation (4G) connection generated 28x more traffic on average than non-4G connection Source: Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2011–2016, Feb 14, 2012 © Synopsys 2012 4 Drives Exploding Need for Bandwidth and Storage Bandwidth Increase A Decade of Digital Universe Growth 7.910 Zettabytes 8000 7000 6000 5000 4000 3000 1.2 2000 Zettabytes 130 1000 Exabytes 0 2005 2010 2015 © Synopsys 2012 5 • One zettabyte = stacks of books from Earth to Pluto 20 times (72 billion miles) • If an 11 oz. cup of coffee equals 1 gigabtye, then 1 zettabyte would have the same volume of the Great Wall of China Source: IBS and Cisco © Synopsys 2012 6 Tomorrow’s World Reality Augmented Reality Blended Reality Search Agents Info That Finds You (and networks that know you) 2D 3D Immersive Video Holographics Medical Mobile Medical Personal Medical Person to Person Machine to Machine Human Machines © Synopsys 2012 7 What the Future Has in Store © Synopsys 2012 8 How Does This Affect Design? © Synopsys 2012 9 Megatrends Change Design Requirements Used to Be… Today It’s… Computing Connectivity Creating Info Consuming Info Compute Power Battery Power Business Consumer At your desk Anywhere, anytime Work Entertainment © Synopsys 2012 10 Trends Drive Process Migration Last Current Next 35% 31% 30% 25% 20% 20% 15% 13% 13% 10% 5% 6% 5% 5% 4% 3% 0% ≥250nm 180nm 130nm 90nm 65/55nm 45/40nm 32/28nm 22/20nm <20nm Synopsys Global User Survey, Feb 2012 N = 1290 © Synopsys 2012 11 and Increasing Gate Count 50% 45% 40% >100M, 13% 35% 30% 50-100M, 6% 25% 20-50M, 7% >100M, 3% 20% 50-100M, 3% 10-20M, 5% 20-50M, 3% 15% 10-20M, 5% 5-10M, 9% 10% 5-10M, 4% 5% 2-5M, 6% 2-5M, 7% 0% 2010 2011 Synopsys Global User Survey, Feb 2012 © Synopsys 2012 12 and Faster Designs 100% >2GHz 1-2GHz 751MHz-1GHz 80% 42% 501-750MHz 401-500MHz 60% 301-400MHz 40% 201-300MHz 20% 101-200MHz 51-100MHz ≤50MHz 0% 2004 2005 2006 2007 2008 2009 2010 2011 Synopsys Global User Survey, Feb 2012 N = 962 © Synopsys 2012 13 … while requiring aggressive Power Management 400% Other Back-biasing/Well-biasing 350% Library Variables (e.g., multi-channel length libraries) 300% Low Vdd Standby 250% State retention MTCMOS/Power gating 200% Lower Vdd operation 150% Dynamic Voltage/Frequency Scaling (DVFS) Multi-Corner, Multi-Mode (MCMM) 100% optimization Multi-voltage domains 50% Multi-Vt leakage optimization Clock gating 0% 2010 2011 Synopsys Global User Survey, Feb 2012 N = 282 © Synopsys 2012 14 Design Challenges are Multiplying Example of 28-nm challenges • Unidirectional Poly (and other RDRs) – Requires separate layouts, verification & test effort. GF and TSMC have different preferred orientations (N/S v. E/W) – No poly for local routing • Device segmentation – Limited device28 sizes, nm large is analog 2X devicesharder broken than up into 40 smaller nm pieces; Increases analog area 28 nm analog layout • Complexity 28 nm IP – area increases 9% larger than 40 nm due to limitations – Approximately 1700w designithout rule checkscircuit at 28nm innovation vs. 700 at 65nm on poly area – 8x the # of corners at 65 v. 28nm – Lower Vddmin resulting in less design headroom – Metal resistance doubles from 40 nm to 28 nm • Global versus local Vth variations due to random doping effects • Device Aging – Must take into account device degradation over time due to 40 nm layout threshold voltage instability (NBTI/PBTI) and mobility degradation (HCI) © Synopsys 2012 15 SoC = Software System on a chip HW & SW Development Costs App-Specific SW $2.50 Low-Level SW $2.00 OS Support Design Management $1.50 Post-silicon Validation Masks $M $1.00 Physical Design RTL Verification $0.50 RTL Development Spec Development $- IP Qualification 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627 Source: IBS, Synopsys Months Software is Half the Time to Market For a Typical SoC ! © Synopsys 2012 16 … And Half the Cost $175 $150 Software $125 Hardware $100 Cost ($M) $75 $50 $25 $0 90nm (60M) 65nm (90M) 45/40nm (130M) 32/28nm (180M) 22/20nm (240M) Feature Dimension (Transistor Count) © Synopsys 2012 17 Source: IBS and Synopsys, 2011 Unlike Moore… Software Guys are Pessimists Page’s Law: 2009 Software gets twice as slow every 18 months.” Wirth’s Law: 1995 Software is getting slower more rapidly than hardware becomes faster. ” © Synopsys 2012 18 What Can We Do About It? © Synopsys 2012 19 The Evolution of Synthesis © Synopsys 2012 20 Placement & Routing Ronald L. Rivest, Charles M. Fiduccia, Robert M. Mattheyses, GE & MIT, 1982 Source: GE, 1986 © Synopsys 2012 21 Logic Synthesis David Gregory, Karen Bartlett, Aart J. de Geus, Gary D. Hachtel, GE & University of Colorado at Boulder, 1986 © Synopsys 2012 22 Until Late 80’s The Implementation Flow Was Quite Straight Forward There Was Already a “Wall”… • Schematic Capture Front-End • Timing Simulation • Place & Route Back-End • DRC/LVS © Synopsys 2012 23 Early 90’s The Relationship Needs Improvements Badly: “Walls” Now Lead to Iterations, Often Out of Control • RTL Simulation Front-End • Logic Synthesis • Place & Route Back-End • DRC/LVS • Delay Calculation Sign-Off • Timing Simulation © Synopsys 2012 24 Early 00’s, 130nm, 7+ Metals PC and Astro+Blast+SilEnsemble – The Relationship Matures Still, Too Many “Walls”, and # of Iterations Too High • RTL Simulation • Logic, Power & Test Synthesis Front-End • Floorplan • Physical Synthesis • Floorplan Back-End • P&R • Extraction & STA Sign-Off • DRC/LVS © Synopsys 2012 25 The Evolution Of The Relationship Convergence ! 2003 2005 2007 2009… 90 Nanometers 65 Nanometers 45/40 Nanometers 32/28 Nanometers “Interoperability” “Correlation” “Look Ahead” “In-Design” © Synopsys 2012 26 The Evolution Of The Relationship Quick Summary • Late 80’s - Early 90’s. Attempt #1 : – Predict the future based on the past – Wire load models, broken by nanometer wires • Mid 90’s. Attempt #2 : – Predict the future based on the present – Front-end floorplanning, broken by “Frankenstein flows” • Late 90’s – Today. Attempt #3 : – Partner to create the future , rather than attempt to predict it – Convergence of synthesis and place & route – But underlying mathematics is different © Synopsys 2012 27 Logic Synthesis And Place & Route A Revolutionary… Evolution : Convergence ! Logic Compiler, ca. 1986 Design Compiler, 2010.03 From Equations to Gates, to… Placed and Routable Gates © Synopsys 2012 28 SoC © Synopsys 2012 29 What is High-Level Synthesis? Designer User inputs: Design technology and methodology Intent • High-level algorithm • Constraints • Develop and verify hardware at a higher level of abstraction c a*b c; – Much smaller code with fewer bugs introduced – Rapid architecture exploration Automation using • Automate implementation and verification High-Level Synthesis – Automatic optimizations that equal hand-coded QoR – Eliminate manual RTL coding & verification HLS outputs: Example benefits • Synthesizable RTL • 2-5X productivity for initial designs • C-model HLS • 5-10X productivity for design re-use Results • RTL testbench • Scripts for synthesis, • Increased exploration leading to better results verification and • Multi-million gate designs in weeks vs. months downstream tools © Synopsys 2012 30 High-Level Synthesis Advantage Traditional Block Design Algorithm RTL Coding RTL Verification Design Exploration Architecture Architecture Implementation Spreadsheets For single architecture only Cycle by cycle functional debug HLS-based Block Design RTL automatically generated Algorithm High-Level RTL Better Designs, Design Design Verification Faster Implementation Faster design at Quickly evaluate Faster, more automatic model-to-RTL higher abstraction multiple architectures validation, reduced RTL-level debug © Synopsys 2012 31 Changing FPGA Design Methodology Classic FPGA • Best Quality of Results Methodology • May not be suitable for largest FPGA Top Down designs (long runtimes and large memory Implementation requirements) “Divide and Conquer” • Reduced Quality of Results Top Down • Shorter runtime -preserve unchanged parts Incremental • “Design Preservation”, block based flows, Implementation and Incremental P&R with “SmartGuide” Emerging • Distributed development • Better design preservation and isolation “Mix and Match” • Design style adjustments needed to achieve Bottom Up and Top optimal timing Quality of Results (e.g. Down Flow registering module boundaries © Synopsys 2012 32 Unified RTL Flow for FPGA and SOC FPGA Synthesis DesignWare IP Synplify Premier/Certify DW Implementation Your IP ASIC Implementation DesignWare Building Blocks Galaxy DW Implementation Common RTL from prototype to production a combination of IP and tools All DW Building blocks, minPower and Macrocell Blocks are supported in Synplify Premier and Certify for FPGA-based prototyping © Synopsys 2012 33 Today’s SOC Designs • Designs are getting larger and larger. • Schedule stays the same or shorter despite the increases in design complexity. • Engineering resources are not increasing to handle this complexity. How can EDA help manage this complexity? © Synopsys 2012 34 Many Methods of Designing “SOC Design”… Similar Approach But End Results Vary … Final Product Varies Building Blocks Instructions Instructions 1. Preheat the oven to 450. 2. Melt butter and chocolate together in the top of a double broiler or in the microwave. Add sea salt. 3. Meanwhile, beat together the egg, egg yolks, and sugar with a whisk or an electric beater until light and slightly foamy. 4. Add the egg mixture to the warm chocolate; whisk quickly to combine.
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