Physical Design of a 3D-Stacked Heterogeneous Multi-Core Processor
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A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design
2118 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 10, OCTOBER 2018 A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design Zhengyu Chen , Student Member, IEEE, Huanyu Wang, Student Member, IEEE, Geng Xie, Student Member, IEEE,andJieGu , Member, IEEE Abstract— In order to fulfill different demands between challenges due to the conflicting requirements between low ultralow energy consumption and high performance, integrated power consumption and high performance. To achieve low circuits are being designed to operate across a large range of power consumption, supply voltage V is typically reduced to supply voltages, in which resiliency to timing violation is the DD key requirement. Unfortunately, traditional timing analysis which near-threshold voltages, e.g., around 0.5 V. At such a voltage, focuses on setup timing tolerance for higher performance cannot stochastic variation associated with transistor threshold volt- model the hold violation efficiently across different voltages. ages becomes a major factor in determining logic timing which In this paper, we proposed a complete flow of computationally makes timing analysis extremely time consuming [1]. Conven- efficient methodology for guaranteeing hold margin, which is tional solution which introduces extra timing margin to avoid particularly important for low-power devices, e.g., Internet-of- Things devices. Leveraging both the conventional static timing timing violation at low-voltage region leads to performance analysis and a most probable point (MPP) theory, we develop a degradation at high-voltage region. In addition, the inefficiency new hold-timing closure methodology across voltages eliminating of conventional static timing analysis (STA) cannot meet the expensive Monte Carlo simulation. -
Efficient Checker Processor Design
Efficient Checker Processor Design Saugata Chatterjee, Chris Weaver, and Todd Austin Electrical Engineering and Computer Science Department University of Michigan {saugatac,chriswea,austin}@eecs.umich.edu Abstract system works to increase test space coverage by proving a design is correct, either through model equivalence or assertion. The approach is significantly more efficient The design and implementation of a modern micro- than simulation-based testing as a single proof can ver- processor creates many reliability challenges. Design- ify correctness over large portions of a design’s state ers must verify the correctness of large complex systems space. However, complex modern pipelines with impre- and construct implementations that work reliably in var- cise state management, out-of-order execution, and ied (and occasionally adverse) operating conditions. In aggressive speculation are too stateful or incomprehen- our previous work, we proposed a solution to these sible to permit complete formal verification. problems by adding a simple, easily verifiable checker To further complicate verification, new reliability processor at pipeline retirement. Performance analyses challenges are materializing in deep submicron fabrica- of our initial design were promising, overall slowdowns tion technologies (i.e. process technologies with mini- due to checker processor hazards were less than 3%. mum feature sizes below 0.25um). Finer feature sizes However, slowdowns for some outlier programs were are generally characterized by increased complexity, larger. more exposure to noise-related faults, and interference In this paper, we examine closely the operation of the from single event radiation (SER). It appears the current checker processor. We identify the specific reasons why advances in verification (e.g., formal verification, the initial design works well for some programs, but model-based test generation) are not keeping pace with slows others. -
Overcoming the Challenges in Very Deep Submicron for Area Reduction, Power Reduction and Faster Design Closure
Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By K. RAKESH Roll No: 20507010 Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007 Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By K. RAKESH Roll No: 20507010 Under the Guidance of Prof. K. K. MAHAPATRA Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007 National Institute of Technology Rourkela CERTIFICATE This is to certify that the thesis entitled, “Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure” submitted by Mr. Koyyalamudi Rakesh (20507010) in partial fulfillment of the requirements for the award of Master of Technology Degree in Electronics & Communication Engineering with specialization in “VLSI Design & Embedded System” at the National Institute of Technology, Rourkela (Deemed University) is an authentic work carried out by him under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma. Prof. K.K. Mahapatra Dept. of Electronics & Communication Engg. Date: National Institute of Technology Rourkela-769008 ACKNOWLEDGEMENTS This project is by far the most significant accomplishment in my life and it would be impossible without people who supported me and believed in me. -
Three-Dimensional Integrated Circuit Design: EDA, Design And
Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change. -
Design Closure: Power Constraints, Best Practices for an Accurate Report Power Estimation
Design Closure: Power Constraints, best practices for an accurate Report Power estimation Feb 2021 © Copyright 2021 Xilinx Design Closure Sessions Session 1 Methodology, tips, and tricks for achieving better Quality-of-Results Session 2 Using Timing Closure Assistance tools to address tough timing issues Session 3 Power Constraints, best practices for an accurate Report Power estimation 2 © Copyright 2021 Xilinx Agenda Power impact and Time to Market Design Closure an efficient approach Understanding design power Design Power Constraints Vivado Commands 3 © Copyright 2021 Xilinx Power impact and Time to Market © Copyright 2021 Xilinx Why is Power Closure so important? Board Design is Fixed Power and Thermal Issues take a long time to correct Design Changes (Typically Weeks) Re-Run P&R HDL Changes Reducing design specifications Hardware changes (Typically Months) Board Re-spin Power Delivery Changes Thermal Solution Changes 5 © Copyright 2021 Xilinx Power / Thermal / Board Design Methodology Power Estimation Thermal Design Define Power Delivery If power cannot be reduced, Thermal and Define / Simulate PDN Board Design needs to be redone Define Board / Sch Checklist (very time consuming) Constrain Vivado Modify Run report_power Design DISSECTION No Designed within • What went well? Budget? • Lessons learned? Yes Converge and ensure all original assumption/ design constraints are met SUCCESS 6 © Copyright 2021 Xilinx Design Closure an efficient approach © Copyright 2021 Xilinx Design closure – combining Timing and Power More efficient, -
Understanding Performance Numbers in Integrated Circuit Design Oprecomp Summer School 2019, Perugia Italy 5 September 2019
Understanding performance numbers in Integrated Circuit Design Oprecomp summer school 2019, Perugia Italy 5 September 2019 Frank K. G¨urkaynak [email protected] Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 2/74 Who Am I? Born in Istanbul, Turkey Studied and worked at: Istanbul Technical University, Istanbul, Turkey EPFL, Lausanne, Switzerland Worcester Polytechnic Institute, Worcester MA, USA Since 2008: Integrated Systems Laboratory, ETH Zurich Director, Microelectronics Design Center Senior Scientist, group of Prof. Luca Benini Interests: Digital Integrated Circuits Cryptographic Hardware Design Design Flows for Digital Design Processor Design Open Source Hardware Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 3/74 What Will We Discuss Today? Introduction Cost Structure of Integrated Circuits (ICs) Measuring performance of ICs Why is it difficult? EDA tools should give us a number Area How do people report area? Is that fair? Speed How fast does my circuit actually work? Power These days much more important, but also much harder to get right Integrated Systems Laboratory The performance establishes the solution space Finally the cost sets a limit to what is possible Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 4/74 System Design Requirements System Requirements Functionality Functionality determines what the system will do Integrated Systems Laboratory Finally the cost sets a limit -
NOT for Printing
New York City Transit ADC60 Waste Management and Resource Efficiency in Transportation SUMMER CONFERENCE IN NEW YORK CITY JULY 13—JULY 15, 2009 2 Broadway, New York Monday July 13, 2009 Tuesday July 14, 2009 Wednesday July 15, 2009 8:30AM – Registration and Breakfast 8:30AM Registration and Breakfast 8:30AM Registration and Breakfast 9:00AM – Welcome/Opening Session 8:45AM Hazardous Materials Investigation/Remediation – 8:45AM Environmental Focus 1 PDH, .1 CM Thomas Abdallah, PE, LEED AP, NYCT Panel Discussion 1 PDH, .1 CM 1. US EPA EPA Region 2 Transportation and Construction Initia- Ernest Tollerson, MTA 1. The Triad Approach: Theory, Practice, and Expectations, Joel tive, Charles Harewood, EPA Collette Ericsson, PE, LEED AP, MTA Regional Bus S. Hayworth, PhD, PE, Hayworth Engineering 2. Hot LEED Topics, Lauren Yarmuth, LEED AP, YRG Ed Wallingford, Committee Chair TRB ADC-60 2. A TRIAD investigation combining Electrical Resistivity Imaging 3. Storm water Retrofitting to Restore Ecosystems, Ted Brown, 9:30AM Sustainability Initiatives 1PDH, .1 CM (ERI), Soil Conductivity/Membrane Interface Probe (SC/MIP), P.E., LEED AP 1. Assessing Green Building Performance, Thomas Burke, PE, Todd R. Kincaid, Ph.D., Kevin Day, P.G., Roger Lamb, P.G., 4. Western Railyards Air Quality, Helen Ginzburg &Tammy Pet- LEED AP, U.S. GSA H2H Associates sios, PB 2. Climate Change and the Port Authority, Chris Zeppie, Chrstine 3. Geologic Framework Modeling for Large Construction Projects, 10:15AM Environmental Engineering Around the World Wedig, PANYNJ Christine Vilardi, PG, CGWP, STV, Inc. 1PDH, .1 CM 3. The High-Line: Conversion of an Abandoned Railway to an Additional Panel Members 1. -
SEMICONDUCTOR COLLABORATIVE DESIGN PROCESS Enable Collaborative Design for Complex Semiconductor Projects
HIGH PERFORMANCE SEMICONDUCTOR INDUSTRY SOLUTION EXPERIENCE SEMICONDUCTOR DESIGN DATA MANAGEMENT HIGH PERFORMANCE SEMICONDUCTOR INDUSTRY SOLUTION EXPERIENCE Achieve higher efficiency and zero re-spins in developing IoT-ready systems-on-chip Project & Portfolio Requirement, Issue, Defect & Management Traceability & Change Advancements in integrated circuit (IC) density and competition for market leadership drive demand for more complex devices from semiconductor Test Management manufacturers. To compete successfully, manufacturers must use teams of diverse design specialists and complex project workflows to maximize device differentiation and team productivity. As a result, IC projects carry increasing business risk. Dassault Systèmes' High Performance Semiconductor Industry Solution Experience powered by the 3DEXPERIENCE® platform provides a portfolio of IC design and engineering performance enhancements that help mitigate project risk, shorten time-to-market, and increase product quality and yield. High Performance Semiconductor provides these benefits through: IP Management Design Data Verification Management & Validation • Efficient intellectual property (IP) management and reuse • Graphical analytics to manage design closure • Instant access to the latest design data for all design teams • End-to-end traceability, from requirements to verification and validation • Packaging reliability simulation and testing • Enhanced product variation and defect management Manufacturing Packaging Manufacturing With this solution portfolio, semiconductor -
CSE 141L: Design Your Own Processor What You'll
CSE 141L: Design your own processor What you’ll do: - learn Xilinx toolflow - learn Verilog language - propose new ISA - implement it - optimize it (for FPGA) - compete with other teams Grading 15% lab participation – webboard 85% various parts of the labs CSE 141L: Design your own processor Teams - two people - pick someone with similar goals - you keep them to the end of the class - more on the class website: http://www.cse.ucsd.edu/classes/sp08/cse141L/ Course Staff: 141L Instructor: Michael Taylor Email: [email protected] Office Hours: EBU 3b 4110 Tuesday 11:30-12:20 TA: Saturnino Email: [email protected] ebu 3b b260 Lab Hours: TBA (141 TA: Kwangyoon) Æ occasional cameos in 141L http://www-cse.ucsd.edu/classes/sp08/cse141L/ Class Introductions Stand up & tell us: -Name - How long until graduation - What you want to do when you “hit the big time” - What kind of thing you find intellectually interesting What is an FPGA? Next time: (Tuesday) Start working on Xilinx assignment (due next Tuesday) - should be posted Sat will give a tutorial on Verilog today Check the website regularly for updates: http://www.cse.ucsd.edu/classes/sp08/cse141L/ CSE 141: 0 Computer Architecture Professor: Michael Taylor UCSD Department of Computer Science & Engineering RF http://www.cse.ucsd.edu/classes/sp08/cse141/ Computer Architecture from 10,000 feet foo(int x) Class of { .. } application Physics Computer Architecture from 10,000 feet foo(int x) Class of { .. } application An impossibly large gap! In the olden days: “In 1942, just after the United States entered World War II, hundreds of women were employed around the country as Physics computers...” (source: IEEE) The Great Battles in Computer Architecture Are About How to Refine the Abstraction Layers foo(int x) { . -
Design for Manufacturing (Dfm) in Submicron Vlsi Design
DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY August 2007 Major Subject: Computer Engineering DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Jiang Hu Committee Members, Weiping Shi Duncan Walker Vivek Sarin Head of Department, Costas N. Georghiades August 2007 Major Subject: Computer Engineering iii ABSTRACT Design for Manufacturing (DFM) in Submicron VLSI Design. (August 2007) Ke Cao, B.S., University of Science and Technology of China; M.S., University of Minnesota Chair of Advisory Committee: Dr. Jiang Hu As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII file to the foundry and expect very good man- ufacturing and parametric yield. This is largely due to the enormous challenges in the manufacturing stage as the feature size continues to shrink. Thus, the idea of DFM (Design for Manufacturing) is getting very popular. Even though there is no universally accepted definition of DFM, in my opinion, one of the major parts of DFM is to bring manufacturing information into the design stage in a way that is understood by designers. Consequently, designers can act on the information to improve both manufacturing and parametric yield. -
Designing a Chip Challenges, Trends, and Latin America Opportunity
Designing a chip Challenges, Trends, and Latin America Opportunity Victor Grimblatt R&D Group Director © Synopsys 2012 1 SASE 2012 Agenda Introduction The Evolution of Synthesis SoC IC Design Methodology New Techniques and Challenges IP Market, an opportunity for Latin America © Synopsys 2012 2 Introduction © Synopsys 2012 3 Interesting Facts from Cisco • Last year’s mobile data traffic eight times the size of the entire global Internet in 2000 • Global mobile data traffic grew 2.3-fold in 2011, more than doubling for 4th year in a row • Mobile video traffic exceeded 50% for the first time in 2011 • Average smartphone usage nearly tripled in 2011 • In 2011, a 4th generation (4G) connection generated 28x more traffic on average than non-4G connection Source: Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2011–2016, Feb 14, 2012 © Synopsys 2012 4 Drives Exploding Need for Bandwidth and Storage Bandwidth Increase A Decade of Digital Universe Growth 7.910 Zettabytes 8000 7000 6000 5000 4000 3000 1.2 2000 Zettabytes 130 1000 Exabytes 0 2005 2010 2015 © Synopsys 2012 5 • One zettabyte = stacks of books from Earth to Pluto 20 times (72 billion miles) • If an 11 oz. cup of coffee equals 1 gigabtye, then 1 zettabyte would have the same volume of the Great Wall of China Source: IBS and Cisco © Synopsys 2012 6 Tomorrow’s World Reality Augmented Reality Blended Reality Search Agents Info That Finds You (and networks that know you) 2D 3D Immersive Video Holographics Medical Mobile Medical Personal Medical Person -
Processor Architecture Design Using 3D Integration Technology
Processor Architecture Design Using 3D Integration Technology Yuan Xie Pennsylvania State University Computer Science and Engineering Department University Park, PA, 16802, USA [email protected] Abstract (4)Smaller form factor, which results in higher pack- ing density and smaller footprint due to the addition of The emerging three-dimensional (3D) chip architec- a third dimension to the conventional two dimensional tures, with their intrinsic capability of reducing the wire layout, and potentially results in a lower cost design. length, is one of the promising solutions to mitigate This tutorial paper first presents the background on the interconnect problem in modern microprocessor de- 3D integration technology, and then reviews various ap- signs. 3D memory stacking also enables much higher proaches to design future 3D microprocessors, which memory bandwidth for future chip-multiprocessor de- leverage the benefits of fast latency, higher bandwidth, sign, mitigating the “memory wall” problem. In addi- and heterogeneous integration capability that are offered tion, heterogenous integration enabled by 3D technol- by 3D technology. The challenges for future 3D archi- ogy can also result in innovation designs for future mi- tecture design are also discussed in the last section. croprocessors. This paper serves as a survey of various approaches to design future 3D microprocessors, lever- 2. 3D Integration Technology aging the benefits of fast latency, higher bandwidth, and The 3D integration technologies [25,26] can be clas- heterogeneous integration capability that are offered by sified into one of the two following categories. (1) 3D technology. 1 Monolithic approach. This approach involves sequen- tial device process. The frontend processing (to build the 1.