DOCSLIB.ORG

UNIVERSITY of CALIFORNIA SAN DIEGO IC Physical Design

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
UNIVERSITY of CALIFORNIA SAN DIEGO IC Physical Design UNIVERSITY OF CALIFORNIA SAN DIEGO IC Physical Design Methodologies for Advanced Process Nodes A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical Engineering (Computer Engineering) by Kwangsoo Han Committee in charge: Professor Andrew B. Kahng, Chair Professor Chung-Kuan Cheng Professor Rajesh Gupta Professor Ryan Kastner Professor Farinaz Koushanfar 2018 Copyright Kwangsoo Han, 2018 All rights reserved. The dissertation of Kwangsoo Han is approved, and it is ac- ceptable in quality and form for publication on microfilm and electronically: Chair University of California San Diego 2018 iii DEDICATION To my family, without whose love, encouragement and sacrifice this thesis would not have been finished. iv TABLE OF CONTENTS Signature Page . iii Dedication . iv Table of Contents . v List of Figures . viii List of Tables . xiii Acknowledgments . xv Vita ............................................. xvii Abstract of the Dissertation . xx Chapter 1 Introduction . 1 1.1 Challenges in Physical Design . 2 1.1.1 Limitation of Manufacturing . 4 1.1.2 Severe Process Variation . 5 1.1.3 Escalating Interconnect RC Delay . 7 1.2 This Thesis . 8 Chapter 2 Manufacturing-Aware Design Methodologies . 12 2.1 MILP-Based Optimization of 2D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts . 13 2.1.1 Background . 16 2.1.2 MILP-based 2D Block Mask Optimization . 21 2.1.3 Overall Flow . 31 2.1.4 Experimental Setup and Results . 34 2.1.5 Conclusion . 42 2.2 Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints . 43 2.2.1 N10 FEOL and Cell Placement Constraints . 43 2.2.2 Related Work . 47 2.2.3 Our Approach . 48 2.2.4 Experimental Setup and Results . 57 2.2.5 Conclusion . 61 2.3 Evaluation of BEOL Design Rule Impacts Using an Optimal ILP-based Detailed Router . 62 2.3.1 Related Work . 64 2.3.2 Optimal Routing Formulation . 65 2.3.3 Empirical Studies . 72 2.3.4 Conclusion . 79 v 2.4 Acknowledgments . 79 Chapter 3 Process-Aware Design Methodologies . 81 3.1 OCV-Aware Top-Level Clock Tree Optimization . 82 3.1.1 Motivation and Related Work . 82 3.1.2 Our Approach . 84 3.1.3 Clock Tree Optimization . 86 3.1.4 Experimental Setup and Results . 92 3.1.5 Conclusion . 98 3.2 A Global-Local Optimization Framework for Simultaneous Multi-Mode Multi-Corner Clock Skew Variation Reduction . 100 3.2.1 Related Work . 101 3.2.2 Problem Formulation . 102 3.2.3 Optimization Framework . 103 3.2.4 Experimental Setup and Results . 113 3.2.5 Conclusion . 117 3.3 Improved Performance of 3DIC Implementations Through Inherent Awareness of Mix-and-Match Die Stacking . 118 3.3.1 Related Work . 120 3.3.2 Problem Formulation . 122 3.3.3 ILP-Based Partitioning Methodology . 123 3.3.4 Heuristic Partitioning Methodology . 125 3.3.5 Experimental Setup and Results . 131 3.3.6 Conclusion . 135 3.4 Acknowledgments . 136 Chapter 4 Interconnect-Aware Design Methodologies . 137 4.1 Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees . 138 4.1.1 Related Work . 141 4.1.2 Problem Formulation . 142 4.1.3 The PD-II Spanning Tree Construction . 144 4.1.4 The Detour-Aware Steinerization Algorithm (DAS)..... 148 4.1.5 Experimental Setup and Results . 149 4.1.6 Conclusion . 156 4.2 A Study of Optimal Cost-Skew Tradeoff and Remaining Suboptimality in Interconnect Tree Constructions . 158 4.2.1 Related Work . 160 4.2.2 Flow-based ILP Formulation . 162 4.2.3 Experimental Setup and Results . 167 4.2.4 Conclusion . 169 4.3 Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution . 170 4.3.1 Motivation and Related Work . 172 4.3.2 Our Approach . 176 4.3.3 Experimental Setup and Results . 190 vi 4.3.4 Conclusion . 198 4.4 Acknowledgments . 199 Chapter 5 Conclusion . 200 Bibliography . 204 vii LIST OF FIGURES Figure 1.1: Design cost and transistor count trends [140]. 1 Figure 1.2: Design Capability Gap [102]. 2 Figure 1.3: Roadmap of future technology [193]. 3 Figure 1.4: History of timing signoff [101]. 3 Figure 1.5: Wafer price trend [215]. 4 Figure 1.6: Design rules and operations explosion [214]. 5 Figure 1.7: Timing corner explosion [101]. 6 Figure 1.8: Cost of design margin. 7 Figure 1.9: Interconnect RC increase as technology nodes scale down [44]. 7 Figure 1.10: Scope and organization of this thesis. 8 Figure 2.1: SAMP process: (a) post-route layout; (b) cut mask application; (c) layout after cut mask application; (d) block mask application; and (e) final layout after block mask application. 14 Figure 2.2: Block mask rules: (a) minimum width and length rules; (b) minimum over- lap rule; (c) minimum U-shape rule; and (d) minimum L-shape rule. 16 Figure 2.3: Illustration of the material selectivity-based block approach. 18 Figure 2.4: Comparison between selective block and non-selective block: (a) selective block mask in red removes only red segments; (b) selective block mask in green removes only green segments; and (c) a complex non-selective block mask is required to remove the same dummy segments. 19 Figure 2.5: Cut mask rules: minimum spacing. 20 Figure 2.6: Comparison between selective cuts and non-selective LELE cuts. (a) Selec- tive cut mask in red (resp. green) realizes EOL only for red (resp. green) segments, and is transparent to green (resp. red) segments. (b) Non-selective LELE cuts realize EOL for both colors. 20 Figure 2.7: Shapes and block candidates for Shape 2. 23 Figure 2.8: Illustration of a U-shape block mask rule violation. 25 Figure 2.9: Cut and block mask co-optimization: (a) block candidates; (b) cut candi- dates; and (c) a possible final layout. 26 0 Figure 2.10: Illustration of binary variable e : cut candidate c1,1 and block candidate v1,3 are selected. 29 Figure 2.11: Gate delay vs. net capacitance for a specific gate instance. 30 Figure 2.12: Comparison of timing results from Tempus (Golden) and our estimation (Estimated). (a) Path delay and (b) stage delay comparisons. The maximum errors are -4ps and -23ps for stage delay and path delay, respectively. 32 Figure 2.13: Illustration of conflict list enumeration for minimum spacing constraint, showing horizontally and vertically conflicting pairs. 33 Figure 2.14: Distributed optimization: (a) - (d) respectively illustrate the first, second, third and fourth iteration in our approach. Since target clips (yellow) for an iteration do not share their boundaries with each other, each target is independently optimizable. 33 Figure 2.15: Overall optimization flow. 34 viii Figure 2.16: Sensitivity study results: sensitivity of dummy removal rate to (a) block candidate length and (b) clip size. ...................... 39 Figure 2.17: Layouts of M4 layer before and after dummy fill removal: (a) initial lay- out with dummy fill; (b) layout covered by the selective block mask (red); (c) layout covered by the selective block mask (blue); and (d) layout after timing-aware dummy fill removal with optimized selective block masks. 42 Figure 2.18: Illustration of inverter cell layout in N10 node. 44 Figure 2.19: (a) Examples of minimum implant width violations [209]. (b) The design rule for OD jogs. 45 Figure 2.20: (a) Drain-drain abutment violation with an example standard cell layout. (b) Use of dummy poly gates in the library design style can avoid DDA violation in a correct-by-construction manner. 45 Figure 2.21: (a) Inter-row variable mrq for IW1. (b) Intra-row variable hrq for IW2. The color (gray and white) of regions indicates Vth................ 51 Figure 2.22: Overall flow of detailed placement legalization. 54 Figure 2.23: Partitioning of layout for parallel global optimization. 56 Figure 2.24: Remaining violations vs. runtime. Each dot indicates an iteration; after the third iteration, local optimization is performed. The diamond-shaped markers represent third-iteration points. 60 Figure 2.25: (a) Layout with DRVs before optimization. (b) Layout without DRVs after optimization. 61 Figure 2.26: Example showing multi-pin nets and the routing solution. 67 Figure 2.27: Via shape. (a) 2 × 2 square via. (b) 2 × 1 bar via. 68 Figure 2.28: (a) SADP-specific design rules and (b) example showing that via location does not provide enough information to distinguish the upper and lower cases, i.e., to check SADP-aware rules. 69 Figure 2.29: An example of a routing graph. (a) The p variable of a vertex vi is deter- mined by flow variables of edges with vertex vi’s neighbor vertices vt, vb, k vl, vr. (b) Wire segment geometries that respectively result when pr,i = 1 k and pl,i = 1.................................. 70 Figure 2.30: (a) A wire segment, of which the EOL is located at vertex vi with the wire coming from the right side. (b) Forbidden via locations for other wire seg- ments with pl,j = 1. (c) Forbidden via locations for other wire segments with pr,j = 1.................................. 72 Figure 2.31: Overall flow of BEOL rule evaluation. 73 Figure 2.32: Routing clips from (a) N28-12T, (b) N28-9T and (c) N7-9T. Standard cell boundaries and power/ground rail are highlighted with white lines and yel- low dashed lines, respectively..
Load more

Recommended publications
  • A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design
    2118 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 10, OCTOBER 2018 A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design Zhengyu Chen , Student Member, IEEE, Huanyu Wang, Student Member, IEEE, Geng Xie, Student Member, IEEE,andJieGu , Member, IEEE Abstract— In order to fulfill different demands between challenges due to the conflicting requirements between low ultralow energy consumption and high performance, integrated power consumption and high performance. To achieve low circuits are being designed to operate across a large range of power consumption, supply voltage V is typically reduced to supply voltages, in which resiliency to timing violation is the DD key requirement. Unfortunately, traditional timing analysis which near-threshold voltages, e.g., around 0.5 V. At such a voltage, focuses on setup timing tolerance for higher performance cannot stochastic variation associated with transistor threshold volt- model the hold violation efficiently across different voltages. ages becomes a major factor in determining logic timing which In this paper, we proposed a complete flow of computationally makes timing analysis extremely time consuming [1]. Conven- efficient methodology for guaranteeing hold margin, which is tional solution which introduces extra timing margin to avoid particularly important for low-power devices, e.g., Internet-of- Things devices. Leveraging both the conventional static timing timing violation at low-voltage region leads to performance analysis and a most probable point (MPP) theory, we develop a degradation at high-voltage region. In addition, the inefficiency new hold-timing closure methodology across voltages eliminating of conventional static timing analysis (STA) cannot meet the expensive Monte Carlo simulation.
    [Show full text]
  • Overcoming the Challenges in Very Deep Submicron for Area Reduction, Power Reduction and Faster Design Closure
    Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By K. RAKESH Roll No: 20507010 Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007 Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By K. RAKESH Roll No: 20507010 Under the Guidance of Prof. K. K. MAHAPATRA Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007 National Institute of Technology Rourkela CERTIFICATE This is to certify that the thesis entitled, “Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure” submitted by Mr. Koyyalamudi Rakesh (20507010) in partial fulfillment of the requirements for the award of Master of Technology Degree in Electronics & Communication Engineering with specialization in “VLSI Design & Embedded System” at the National Institute of Technology, Rourkela (Deemed University) is an authentic work carried out by him under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma. Prof. K.K. Mahapatra Dept. of Electronics & Communication Engg. Date: National Institute of Technology Rourkela-769008 ACKNOWLEDGEMENTS This project is by far the most significant accomplishment in my life and it would be impossible without people who supported me and believed in me.
    [Show full text]
  • Design Closure: Power Constraints, Best Practices for an Accurate Report Power Estimation
    Design Closure: Power Constraints, best practices for an accurate Report Power estimation Feb 2021 © Copyright 2021 Xilinx Design Closure Sessions Session 1 Methodology, tips, and tricks for achieving better Quality-of-Results Session 2 Using Timing Closure Assistance tools to address tough timing issues Session 3 Power Constraints, best practices for an accurate Report Power estimation 2 © Copyright 2021 Xilinx Agenda Power impact and Time to Market Design Closure an efficient approach Understanding design power Design Power Constraints Vivado Commands 3 © Copyright 2021 Xilinx Power impact and Time to Market © Copyright 2021 Xilinx Why is Power Closure so important? Board Design is Fixed Power and Thermal Issues take a long time to correct Design Changes (Typically Weeks) Re-Run P&R HDL Changes Reducing design specifications Hardware changes (Typically Months) Board Re-spin Power Delivery Changes Thermal Solution Changes 5 © Copyright 2021 Xilinx Power / Thermal / Board Design Methodology Power Estimation Thermal Design Define Power Delivery If power cannot be reduced, Thermal and Define / Simulate PDN Board Design needs to be redone Define Board / Sch Checklist (very time consuming) Constrain Vivado Modify Run report_power Design DISSECTION No Designed within • What went well? Budget? • Lessons learned? Yes Converge and ensure all original assumption/ design constraints are met SUCCESS 6 © Copyright 2021 Xilinx Design Closure an efficient approach © Copyright 2021 Xilinx Design closure – combining Timing and Power More efficient,
    [Show full text]
  • NOT for Printing
    New York City Transit ADC60 Waste Management and Resource Efficiency in Transportation SUMMER CONFERENCE IN NEW YORK CITY JULY 13—JULY 15, 2009 2 Broadway, New York Monday July 13, 2009 Tuesday July 14, 2009 Wednesday July 15, 2009 8:30AM – Registration and Breakfast 8:30AM Registration and Breakfast 8:30AM Registration and Breakfast 9:00AM – Welcome/Opening Session 8:45AM Hazardous Materials Investigation/Remediation – 8:45AM Environmental Focus 1 PDH, .1 CM Thomas Abdallah, PE, LEED AP, NYCT Panel Discussion 1 PDH, .1 CM 1. US EPA EPA Region 2 Transportation and Construction Initia- Ernest Tollerson, MTA 1. The Triad Approach: Theory, Practice, and Expectations, Joel tive, Charles Harewood, EPA Collette Ericsson, PE, LEED AP, MTA Regional Bus S. Hayworth, PhD, PE, Hayworth Engineering 2. Hot LEED Topics, Lauren Yarmuth, LEED AP, YRG Ed Wallingford, Committee Chair TRB ADC-60 2. A TRIAD investigation combining Electrical Resistivity Imaging 3. Storm water Retrofitting to Restore Ecosystems, Ted Brown, 9:30AM Sustainability Initiatives 1PDH, .1 CM (ERI), Soil Conductivity/Membrane Interface Probe (SC/MIP), P.E., LEED AP 1. Assessing Green Building Performance, Thomas Burke, PE, Todd R. Kincaid, Ph.D., Kevin Day, P.G., Roger Lamb, P.G., 4. Western Railyards Air Quality, Helen Ginzburg &Tammy Pet- LEED AP, U.S. GSA H2H Associates sios, PB 2. Climate Change and the Port Authority, Chris Zeppie, Chrstine 3. Geologic Framework Modeling for Large Construction Projects, 10:15AM Environmental Engineering Around the World Wedig, PANYNJ Christine Vilardi, PG, CGWP, STV, Inc. 1PDH, .1 CM 3. The High-Line: Conversion of an Abandoned Railway to an Additional Panel Members 1.
    [Show full text]
  • SEMICONDUCTOR COLLABORATIVE DESIGN PROCESS Enable Collaborative Design for Complex Semiconductor Projects
    HIGH PERFORMANCE SEMICONDUCTOR INDUSTRY SOLUTION EXPERIENCE SEMICONDUCTOR DESIGN DATA MANAGEMENT HIGH PERFORMANCE SEMICONDUCTOR INDUSTRY SOLUTION EXPERIENCE Achieve higher efficiency and zero re-spins in developing IoT-ready systems-on-chip Project & Portfolio Requirement, Issue, Defect & Management Traceability & Change Advancements in integrated circuit (IC) density and competition for market leadership drive demand for more complex devices from semiconductor Test Management manufacturers. To compete successfully, manufacturers must use teams of diverse design specialists and complex project workflows to maximize device differentiation and team productivity. As a result, IC projects carry increasing business risk. Dassault Systèmes' High Performance Semiconductor Industry Solution Experience powered by the 3DEXPERIENCE® platform provides a portfolio of IC design and engineering performance enhancements that help mitigate project risk, shorten time-to-market, and increase product quality and yield. High Performance Semiconductor provides these benefits through: IP Management Design Data Verification Management & Validation • Efficient intellectual property (IP) management and reuse • Graphical analytics to manage design closure • Instant access to the latest design data for all design teams • End-to-end traceability, from requirements to verification and validation • Packaging reliability simulation and testing • Enhanced product variation and defect management Manufacturing Packaging Manufacturing With this solution portfolio, semiconductor
    [Show full text]
  • Design for Manufacturing (Dfm) in Submicron Vlsi Design
    DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY August 2007 Major Subject: Computer Engineering DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Jiang Hu Committee Members, Weiping Shi Duncan Walker Vivek Sarin Head of Department, Costas N. Georghiades August 2007 Major Subject: Computer Engineering iii ABSTRACT Design for Manufacturing (DFM) in Submicron VLSI Design. (August 2007) Ke Cao, B.S., University of Science and Technology of China; M.S., University of Minnesota Chair of Advisory Committee: Dr. Jiang Hu As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII file to the foundry and expect very good man- ufacturing and parametric yield. This is largely due to the enormous challenges in the manufacturing stage as the feature size continues to shrink. Thus, the idea of DFM (Design for Manufacturing) is getting very popular. Even though there is no universally accepted definition of DFM, in my opinion, one of the major parts of DFM is to bring manufacturing information into the design stage in a way that is understood by designers. Consequently, designers can act on the information to improve both manufacturing and parametric yield.
    [Show full text]
  • Designing a Chip Challenges, Trends, and Latin America Opportunity
    Designing a chip Challenges, Trends, and Latin America Opportunity Victor Grimblatt R&D Group Director © Synopsys 2012 1 SASE 2012 Agenda Introduction The Evolution of Synthesis SoC IC Design Methodology New Techniques and Challenges IP Market, an opportunity for Latin America © Synopsys 2012 2 Introduction © Synopsys 2012 3 Interesting Facts from Cisco • Last year’s mobile data traffic eight times the size of the entire global Internet in 2000 • Global mobile data traffic grew 2.3-fold in 2011, more than doubling for 4th year in a row • Mobile video traffic exceeded 50% for the first time in 2011 • Average smartphone usage nearly tripled in 2011 • In 2011, a 4th generation (4G) connection generated 28x more traffic on average than non-4G connection Source: Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2011–2016, Feb 14, 2012 © Synopsys 2012 4 Drives Exploding Need for Bandwidth and Storage Bandwidth Increase A Decade of Digital Universe Growth 7.910 Zettabytes 8000 7000 6000 5000 4000 3000 1.2 2000 Zettabytes 130 1000 Exabytes 0 2005 2010 2015 © Synopsys 2012 5 • One zettabyte = stacks of books from Earth to Pluto 20 times (72 billion miles) • If an 11 oz. cup of coffee equals 1 gigabtye, then 1 zettabyte would have the same volume of the Great Wall of China Source: IBS and Cisco © Synopsys 2012 6 Tomorrow’s World Reality Augmented Reality Blended Reality Search Agents Info That Finds You (and networks that know you) 2D 3D Immersive Video Holographics Medical Mobile Medical Personal Medical Person
    [Show full text]
  • Physical Design of a 3D-Stacked Heterogeneous Multi-Core Processor
    Physical Design of a 3D-Stacked Heterogeneous Multi-Core Processor Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul Franzon Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC, USA frhwidial, rbasuro, zzhang18, jcledfo3, slipa, ericro, wdavis, [email protected] Abstract—With the end of Dennard scaling, three dimensional TSV (I/O pads) stacking has emerged as a promising integration technique to Bulk improve microprocessor performance. In this paper we present Active First metal layer a 3D-SIC physical design methodology for a multi-core processor using commercial off-the-shelf tools. We explain the various Metal High-performance core flows involved and present the lessons learned during the design Last metal layer process. The logic dies were fabricated with GlobalFoundries Face-to-face micro-bumps 130 nm process and were stacked using the Ziptronix face-to- Metal Low-power core face (F2F) bonding technology. We also present a comparative analysis which highlights the benefits of 3D integration. Results indicate an order of magnitude decrease in wirelengths for critical Active inter-core components in the 3D implementation compared to 2D Bulk implementations. I. INTRODUCTION Fig. 1. Cross-section of the face-to-face bonded 3D-IC stack. As performance benefits from technology scaling slows The primary advantage of 3D-stacking comes from reduced down, computer architects are looking at various architectural wirelengths leading to an improvement in routability and signal techniques to maintain the trend of performance improvement, delays. On the other hand, going 3D also increases design while meeting the power budget.
    [Show full text]
  • A Semi-Custom Design Flow in High-Performance Microprocessor Design Gregory A
    A Semi-custom Design Flow in High-performance Microprocessor Design Gregory A. Northrop Pong-Fei Lu IBM Research IBM Research Yorktown Heights, NY 10598 Yorktown Heights, NY 10598 [email protected] [email protected] ABSTRACT RISC-like micro-architecture. In this paper we present techniques shown to significantly The physical design of these processors makes extensive use of enhance the custom circuit design process typical of high- hierarchy, partitioning the chip into functional units (instruction, performance microprocessors. This methodology combines FXU, FPU…) and units into macros. There are typically ~6 units flexible custom circuit design with automated tuning and and ~200 distinct macros (about 600 total instances), and a physical design tools to provide new opportunities to optimized macro can have anywhere from 1K to 100K or more transistors. design throughout the development cycle. The macro serves as the primary partitioning unit for logic entry (HDL), and a common macro connectivity description is used for Keywords both functional models for verification and for circuit design. Standard cell, circuit tuning, custom design, methodology. Boolean verification is used to ensure functional equivalence between macro HDL and a schematic representation, which is verified against the physical design. All macros and units are 1. INTRODUCTION fully floorplanned objects, and the global wiring (chip and unit) The development of high performance microprocessors requires is done hierarchically, using a wiring contract methodology. concurrent design at many levels (logical, circuit, physical) with Macros are all characterized for timing, noise, etc., and large teams and tightly interlocked schedules. Often the best represented by models at the global level.
    [Show full text]
  • LAMDA: Learning-Assisted Multi-Stage Autotuning for FPGA Design Closure
    LAMDA: Learning-Assisted Multi-Stage Autotuning for FPGA Design Closure Ecenur Ustun∗, Shaojie Xiang, Jinny Gui, Cunxi Yu∗, and Zhiru Zhang∗ School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA feu49, cunxi.yu, [email protected] 12.5 12.30 Abstract—A primary barrier to rapid hardware specialization Default Timing with FPGAs stems from weak guarantees of existing CAD 12.0 11.66 tools on achieving design closure. Current methodologies require 11.5 11.29 extensive manual efforts to configure a large set of options 11.16 11.13 across multiple stages of the toolflow, intended to achieve high 11.0 quality-of-results. Due to the size and complexity of the design 10.5 space spanned by these options, coupled with the time-consuming 10.0 9.93 9.91 9.86 9.68 evaluation of each design point, exploration for reconfigurable 9.50 9.5 computing has become remarkably challenging. To tackle this Critical Path (ns) challenge, we present a learning-assisted autotuning framework 9.0 8.76 called LAMDA, which accelerates FPGA design closure by 8.66 8.5 8.52 8.37 utilizing design-specific features extracted from early stages of the 8.22 8.0 design flow to guide the tuning process with significant runtime 8.8 8.9 9.0 9.1 9.2 9.3 9.4 savings. LAMDA automatically configures logic synthesis, tech- Timing Target (ns) nology mapping, placement, and routing to achieve design closure Fig. 1. Timing distribution of bfly for various tool settings and timing efficiently. Compared with a state-of-the-art FPGA-targeted auto- constraints – x-axis represents target clock period (ns), and y-axis represents tuning system, LAMDA realizes faster timing closure on various critical path delay (ns).
    [Show full text]
  • Ultrafast Design Methodology Guide for the Vivado Design Suite
    See all versions of this document UltraFast Design Methodology Guide for the Vivado Design Suite UG949 (v2019.2) December 6, 2019 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 12/06/2019 Version 2019.2 Thermal Solution Considerations Added new section. Performance/Power Trade-Off for Block RAMs Updated examples. Using the CLOCK_LOW_FANOUT Constraint Updated examples. Using Incremental Implementation Flows Added information about automatic incremental implementation mode. Incremental Directives and Target WNS Added new section. Compile Time Considerations Added new section. Assessing the Maximum Frequency of the Design Added new section. Reducing Clock Delay in UltraScale and UltraScale+ Devices Added new section. Disable LUT Combining Updated example. ML Strategies Added new section. Using Incremental Implementation Added information about automatic incremental implementation mode. Using VIO Cores Added new section. 06/26/2019 Version 2019.1 About the UltraFast Design Methodology Added reference to UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292). SLR Utilization Considerations Updated example. Auto-Pipelining Considerations Added new section. Using Auto-Pipelining on Custom Interfaces Updated to show the hierarchy recommendation and USER_SLR_ASSIGNMENT constraints. Synchronous CDC Added note about safe timing between BUFGCE_DIV clocks. Incremental Synthesis Flows Added new section. Using Incremental Implementation Flows Added information on automatic incremental implementation. Optimization Analysis Added -debug_log option. Methodology DRCs with Impact on Timing Closure Added Severity column and TIMING-44 and TIMING-45 checks. Methodology DRCs with Impact on Signoff Quality Added Severity column and TIMING-46 check. Optimizing Paths with Dedicated Blocks and Macro Added optimization options. Primitives Interconnect Congestion Level in the Device Window Added enhanced reporting information.
    [Show full text]
  • Constraint Driven I/O Planning and Placement for Chip-Package Co-Design ∗
    Constraint Driven I/O Planning and Placement for Chip-package Co-design ∗ Jinjun Xiong1 Yiu-Chung Wong2 Egino Sarto2 Lei He1 EE Department, University of California at Los Angeles1, CA 90095, USA Rio Design Automation, Inc.2, Santa Clara, CA 95054, USA ABSTRACT support chip-package co-design. Moreover, I/O placement System-on-chip and system-in-package result in increased also needs to address many issues on timing closure, signal number of I/O cells and complicated constraints for both integrity (SI) and power integrity for chip-package co-design. chip designs and package designs. This renders the tradi- To tackle these problems, complicated design constraints are tional manually tuned and chip-centered I/O designs subop- generated in practice to guide the I/O placement. However, timal in terms of both turn around time and design quality. to the best of our knowledge, there is no study on I/O place- In this paper we formally introduce a set of design con- ment in the literature that has formally considered these straints suitable for chip-package co-design. We formulate a real design constraints [2, 3, 6, 7] except [8], where only I/O constraint-driven I/O planning and placement problem, and standard compatibility constraints are considered for FPGA solve it by a multi-step algorithm based upon integer linear I/O placement. By making use of FPGA restricted but well- programming. Experiment results using real industry de- defined regular structures, [8] proposed to solve it via integer signs show that the proposed algorithm can effectively find linear programming.
    [Show full text]