DOCSLIB.ORG

Intel Quartus Prime Pro Edition User Guide: Design Recommendations Send Feedback

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Intel Quartus Prime Pro Edition User Guide: Design Recommendations Send Feedback Intel® Quartus® Prime Pro Edition User Guide Design Recommendations Updated for Intel® Quartus® Prime Design Suite: 19.1 Subscribe UG-20131 | 2019.04.01 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Recommended HDL Coding Styles .................................................................................. 4 1.1. Using Provided HDL Templates................................................................................ 4 1.1.1. Inserting HDL Code from a Provided Template............................................... 4 1.2. Instantiating IP Cores in HDL.................................................................................. 5 1.3. Inferring Multipliers and DSP Functions.....................................................................6 1.3.1. Inferring Multipliers....................................................................................6 1.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions........................... 7 1.4. Inferring Memory Functions from HDL Code ............................................................. 8 1.4.1. Inferring RAM functions from HDL Code........................................................ 9 1.4.2. Inferring ROM Functions from HDL Code..................................................... 26 1.4.3. Inferring Shift Registers in HDL Code..........................................................28 1.5. Register and Latch Coding Guidelines..................................................................... 31 1.5.1. Register Power-Up Values..........................................................................31 1.5.2. Secondary Register Control Signals Such as Clear and Clock Enable................33 1.5.3. Latches ..................................................................................................34 1.6. General Coding Guidelines.................................................................................... 37 1.6.1. Tri-State Signals ..................................................................................... 38 1.6.2. Clock Multiplexing.................................................................................... 38 1.6.3. Adder Trees ............................................................................................40 1.6.4. State Machine HDL Guidelines................................................................... 41 1.6.5. Multiplexer HDL Guidelines ....................................................................... 47 1.6.6. Cyclic Redundancy Check Functions ...........................................................50 1.6.7. Comparator HDL Guidelines.......................................................................52 1.6.8. Counter HDL Guidelines............................................................................ 53 1.7. Designing with Low-Level Primitives....................................................................... 53 1.8. Recommended HDL Coding Styles Revision History...................................................54 2. Recommended Design Practices................................................................................... 57 2.1. Following Synchronous FPGA Design Practices..........................................................57 2.1.1. Implementing Synchronous Designs........................................................... 57 2.1.2. Asynchronous Design Hazards................................................................... 58 2.2. HDL Design Guidelines..........................................................................................59 2.2.1. Considerations for the Intel Hyperflex™ FPGA Architecture............................. 59 2.2.2. Optimizing Combinational Logic................................................................. 59 2.2.3. Optimizing Clocking Schemes.................................................................... 62 2.2.4. Optimizing Physical Implementation and Timing Closure................................67 2.2.5. Optimizing Power Consumption..................................................................70 2.2.6. Managing Design Metastability...................................................................70 2.3. Design Rule Checking with Design Assistant ........................................................... 70 2.3.1. Cross-Probing from Design Assistant.......................................................... 71 2.3.2. Running Design Assistant During Compilation.............................................. 75 2.3.3. Running Design Assistant in Analysis Mode..................................................77 2.3.4. Changing Design Assistant Rule Scope or Number ....................................... 82 2.3.5. Design Assistant Rules..............................................................................82 2.4. Use Clock and Register-Control Architectural Features.............................................119 2.4.1. Use Global Reset Resources..................................................................... 119 2.4.2. Use Global Clock Network Resources.........................................................128 Intel Quartus Prime Pro Edition User Guide: Design Recommendations Send Feedback 2 Contents 2.4.3. Use Clock Region Assignments to Optimize Clock Constraints....................... 129 2.4.4. Avoid Asynchronous Register Control Signals............................................. 131 2.5. Implementing Embedded RAM............................................................................. 131 2.6. Recommended Design Practices Revision History.................................................... 132 3. Managing Metastability with the Intel Quartus Prime Software.................................. 134 3.1. Metastability Analysis in the Intel Quartus Prime Software....................................... 135 3.1.1. Synchronization Register Chains...............................................................135 3.1.2. Identify Synchronizers for Metastability Analysis.........................................136 3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis..............................................................................136 3.2. Metastability and MTBF Reporting.........................................................................137 3.2.1. Metastability Reports.............................................................................. 138 3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation.....................................140 3.3. MTBF Optimization............................................................................................. 140 3.3.1. Synchronization Register Chain Length......................................................141 3.4. Reducing Metastability Effects..............................................................................142 3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer... 142 3.4.2. Force the Identification of Synchronization Registers................................... 142 3.4.3. Set the Synchronizer Data Toggle Rate......................................................143 3.4.4. Optimize Metastability During Fitting.........................................................143 3.4.5. Increase the Length of Synchronizers to Protect and Optimize...................... 143 3.4.6. Increase the Number of Stages Used in Synchronizers................................ 143 3.4.7. Select a Faster Speed Grade Device..........................................................144 3.5. Scripting Support............................................................................................... 144 3.5.1. Identifying Synchronizers for Metastability Analysis.................................... 144 3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation.....................................145 3.5.3. report_metastability and Tcl Command......................................................145 3.5.4. MTBF Optimization................................................................................. 145 3.5.5. Synchronization Register Chain Length......................................................146 3.6. Managing Metastability....................................................................................... 146 3.7. Managing Metastability with the Intel Quartus Prime Software Revision History...........146 A. Intel Quartus Prime Pro Edition User Guides.............................................................. 148 Send Feedback Intel Quartus Prime Pro Edition User Guide: Design Recommendations 3 UG-20131 | 2019.04.01 Send Feedback 1. Recommended HDL Coding Styles This chapter provides Hardware Description Language (HDL) coding style recommendations to ensure optimal synthesis results when targeting Intel FPGA devices. HDL coding styles have a significant effect on the quality of results for programmable logic designs. Synthesis tools optimize HDL code for both logic utilization and performance; however, synthesis tools cannot interpret the intent of your design. Therefore, the most effective optimizations require conformance to recommended coding styles. Note: For style recommendations, options, or HDL attributes specific to your synthesis tool (including other Quartus software products and other EDA tools), refer to the synthesis tool vendor’s documentation. Related Information • Advanced Synthesis Cookbook • Design Examples • Reference Designs 1.1. Using Provided HDL Templates The Intel® Quartus® Prime software provides templates
Load more

Recommended publications
  • A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design
    2118 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 10, OCTOBER 2018 A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design Zhengyu Chen , Student Member, IEEE, Huanyu Wang, Student Member, IEEE, Geng Xie, Student Member, IEEE,andJieGu , Member, IEEE Abstract— In order to fulfill different demands between challenges due to the conflicting requirements between low ultralow energy consumption and high performance, integrated power consumption and high performance. To achieve low circuits are being designed to operate across a large range of power consumption, supply voltage V is typically reduced to supply voltages, in which resiliency to timing violation is the DD key requirement. Unfortunately, traditional timing analysis which near-threshold voltages, e.g., around 0.5 V. At such a voltage, focuses on setup timing tolerance for higher performance cannot stochastic variation associated with transistor threshold volt- model the hold violation efficiently across different voltages. ages becomes a major factor in determining logic timing which In this paper, we proposed a complete flow of computationally makes timing analysis extremely time consuming [1]. Conven- efficient methodology for guaranteeing hold margin, which is tional solution which introduces extra timing margin to avoid particularly important for low-power devices, e.g., Internet-of- Things devices. Leveraging both the conventional static timing timing violation at low-voltage region leads to performance analysis and a most probable point (MPP) theory, we develop a degradation at high-voltage region. In addition, the inefficiency new hold-timing closure methodology across voltages eliminating of conventional static timing analysis (STA) cannot meet the expensive Monte Carlo simulation.
    [Show full text]
  • Overcoming the Challenges in Very Deep Submicron for Area Reduction, Power Reduction and Faster Design Closure
    Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By K. RAKESH Roll No: 20507010 Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007 Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By K. RAKESH Roll No: 20507010 Under the Guidance of Prof. K. K. MAHAPATRA Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007 National Institute of Technology Rourkela CERTIFICATE This is to certify that the thesis entitled, “Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure” submitted by Mr. Koyyalamudi Rakesh (20507010) in partial fulfillment of the requirements for the award of Master of Technology Degree in Electronics & Communication Engineering with specialization in “VLSI Design & Embedded System” at the National Institute of Technology, Rourkela (Deemed University) is an authentic work carried out by him under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma. Prof. K.K. Mahapatra Dept. of Electronics & Communication Engg. Date: National Institute of Technology Rourkela-769008 ACKNOWLEDGEMENTS This project is by far the most significant accomplishment in my life and it would be impossible without people who supported me and believed in me.
    [Show full text]
  • Nios II Custom Instruction User Guide
    Nios II Custom Instruction User Guide Subscribe UG-20286 | 2020.04.27 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Nios II Custom Instruction Overview..............................................................................4 1.1. Custom Instruction Implementation......................................................................... 4 1.1.1. Custom Instruction Hardware Implementation............................................... 5 1.1.2. Custom Instruction Software Implementation................................................ 6 2. Custom Instruction Hardware Interface......................................................................... 7 2.1. Custom Instruction Types....................................................................................... 7 2.1.1. Combinational Custom Instructions.............................................................. 8 2.1.2. Multicycle Custom Instructions...................................................................10 2.1.3. Extended Custom Instructions................................................................... 11 2.1.4. Internal Register File Custom Instructions................................................... 13 2.1.5. External Interface Custom Instructions....................................................... 15 3. Custom Instruction Software Interface.........................................................................16 3.1. Custom Instruction Software Examples................................................................... 16
    [Show full text]
  • Intel Quartus Prime Pro Edition User Guide: Programmer Send Feedback
    Intel® Quartus® Prime Pro Edition User Guide Programmer Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-20134 | 2021.07.21 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Intel® Quartus® Prime Programmer User Guide..............................................................4 1.1. Generating Primary Device Programming Files........................................................... 5 1.2. Generating Secondary Programming Files................................................................. 6 1.2.1. Generating Secondary Programming Files (Programming File Generator)........... 7 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box)............................................................................................. 11 1.3. Enabling Bitstream Security for Intel Stratix 10 Devices............................................ 18 1.3.1. Enabling Bitstream Authentication (Programming File Generator)................... 19 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator).............................................................................................. 21 1.3.3. Enabling Bitstream Encryption (Programming File Generator).........................22 1.4. Enabling Bitstream Encryption or Compression for Intel Arria 10 and Intel Cyclone 10 GX Devices.................................................................................................. 23 1.5. Generating Programming Files for Partial Reconfiguration.........................................
    [Show full text]
  • Introduction to Intel® FPGA IP Cores
    Introduction to Intel® FPGA IP Cores Updated for Intel® Quartus® Prime Design Suite: 20.3 Subscribe UG-01056 | 2020.11.09 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® FPGA IP Cores..............................................................................3 1.1. IP Catalog and Parameter Editor.............................................................................. 4 1.1.1. The Parameter Editor................................................................................. 5 1.2. Installing and Licensing Intel FPGA IP Cores.............................................................. 5 1.2.1. Intel FPGA IP Evaluation Mode.....................................................................6 1.2.2. Checking the IP License Status.................................................................... 8 1.2.3. Intel FPGA IP Versioning............................................................................. 9 1.2.4. Adding IP to IP Catalog...............................................................................9 1.3. Best Practices for Intel FPGA IP..............................................................................10 1.4. IP General Settings.............................................................................................. 11 1.5. Generating IP Cores (Intel Quartus Prime Pro Edition)...............................................12 1.5.1. IP Core Generation Output (Intel Quartus Prime Pro Edition)..........................13 1.5.2. Scripting IP Core Generation....................................................................
    [Show full text]
  • Design Closure: Power Constraints, Best Practices for an Accurate Report Power Estimation
    Design Closure: Power Constraints, best practices for an accurate Report Power estimation Feb 2021 © Copyright 2021 Xilinx Design Closure Sessions Session 1 Methodology, tips, and tricks for achieving better Quality-of-Results Session 2 Using Timing Closure Assistance tools to address tough timing issues Session 3 Power Constraints, best practices for an accurate Report Power estimation 2 © Copyright 2021 Xilinx Agenda Power impact and Time to Market Design Closure an efficient approach Understanding design power Design Power Constraints Vivado Commands 3 © Copyright 2021 Xilinx Power impact and Time to Market © Copyright 2021 Xilinx Why is Power Closure so important? Board Design is Fixed Power and Thermal Issues take a long time to correct Design Changes (Typically Weeks) Re-Run P&R HDL Changes Reducing design specifications Hardware changes (Typically Months) Board Re-spin Power Delivery Changes Thermal Solution Changes 5 © Copyright 2021 Xilinx Power / Thermal / Board Design Methodology Power Estimation Thermal Design Define Power Delivery If power cannot be reduced, Thermal and Define / Simulate PDN Board Design needs to be redone Define Board / Sch Checklist (very time consuming) Constrain Vivado Modify Run report_power Design DISSECTION No Designed within • What went well? Budget? • Lessons learned? Yes Converge and ensure all original assumption/ design constraints are met SUCCESS 6 © Copyright 2021 Xilinx Design Closure an efficient approach © Copyright 2021 Xilinx Design closure – combining Timing and Power More efficient,
    [Show full text]
  • Intel® Arria® 10 Device Overview
    Intel® Arria® 10 Device Overview Subscribe A10-OVERVIEW | 2020.10.20 Send Feedback Latest document on the web: PDF | HTML Contents Contents Intel® Arria® 10 Device Overview....................................................................................... 3 Key Advantages of Intel Arria 10 Devices........................................................................ 4 Summary of Intel Arria 10 Features................................................................................4 Intel Arria 10 Device Variants and Packages.....................................................................7 Intel Arria 10 GX.................................................................................................7 Intel Arria 10 GT............................................................................................... 11 Intel Arria 10 SX............................................................................................... 14 I/O Vertical Migration for Intel Arria 10 Devices.............................................................. 17 Adaptive Logic Module................................................................................................ 17 Variable-Precision DSP Block........................................................................................18 Embedded Memory Blocks........................................................................................... 20 Types of Embedded Memory............................................................................... 21 Embedded Memory Capacity in
    [Show full text]
  • NOT for Printing
    New York City Transit ADC60 Waste Management and Resource Efficiency in Transportation SUMMER CONFERENCE IN NEW YORK CITY JULY 13—JULY 15, 2009 2 Broadway, New York Monday July 13, 2009 Tuesday July 14, 2009 Wednesday July 15, 2009 8:30AM – Registration and Breakfast 8:30AM Registration and Breakfast 8:30AM Registration and Breakfast 9:00AM – Welcome/Opening Session 8:45AM Hazardous Materials Investigation/Remediation – 8:45AM Environmental Focus 1 PDH, .1 CM Thomas Abdallah, PE, LEED AP, NYCT Panel Discussion 1 PDH, .1 CM 1. US EPA EPA Region 2 Transportation and Construction Initia- Ernest Tollerson, MTA 1. The Triad Approach: Theory, Practice, and Expectations, Joel tive, Charles Harewood, EPA Collette Ericsson, PE, LEED AP, MTA Regional Bus S. Hayworth, PhD, PE, Hayworth Engineering 2. Hot LEED Topics, Lauren Yarmuth, LEED AP, YRG Ed Wallingford, Committee Chair TRB ADC-60 2. A TRIAD investigation combining Electrical Resistivity Imaging 3. Storm water Retrofitting to Restore Ecosystems, Ted Brown, 9:30AM Sustainability Initiatives 1PDH, .1 CM (ERI), Soil Conductivity/Membrane Interface Probe (SC/MIP), P.E., LEED AP 1. Assessing Green Building Performance, Thomas Burke, PE, Todd R. Kincaid, Ph.D., Kevin Day, P.G., Roger Lamb, P.G., 4. Western Railyards Air Quality, Helen Ginzburg &Tammy Pet- LEED AP, U.S. GSA H2H Associates sios, PB 2. Climate Change and the Port Authority, Chris Zeppie, Chrstine 3. Geologic Framework Modeling for Large Construction Projects, 10:15AM Environmental Engineering Around the World Wedig, PANYNJ Christine Vilardi, PG, CGWP, STV, Inc. 1PDH, .1 CM 3. The High-Line: Conversion of an Abandoned Railway to an Additional Panel Members 1.
    [Show full text]
  • SEMICONDUCTOR COLLABORATIVE DESIGN PROCESS Enable Collaborative Design for Complex Semiconductor Projects
    HIGH PERFORMANCE SEMICONDUCTOR INDUSTRY SOLUTION EXPERIENCE SEMICONDUCTOR DESIGN DATA MANAGEMENT HIGH PERFORMANCE SEMICONDUCTOR INDUSTRY SOLUTION EXPERIENCE Achieve higher efficiency and zero re-spins in developing IoT-ready systems-on-chip Project & Portfolio Requirement, Issue, Defect & Management Traceability & Change Advancements in integrated circuit (IC) density and competition for market leadership drive demand for more complex devices from semiconductor Test Management manufacturers. To compete successfully, manufacturers must use teams of diverse design specialists and complex project workflows to maximize device differentiation and team productivity. As a result, IC projects carry increasing business risk. Dassault Systèmes' High Performance Semiconductor Industry Solution Experience powered by the 3DEXPERIENCE® platform provides a portfolio of IC design and engineering performance enhancements that help mitigate project risk, shorten time-to-market, and increase product quality and yield. High Performance Semiconductor provides these benefits through: IP Management Design Data Verification Management & Validation • Efficient intellectual property (IP) management and reuse • Graphical analytics to manage design closure • Instant access to the latest design data for all design teams • End-to-end traceability, from requirements to verification and validation • Packaging reliability simulation and testing • Enhanced product variation and defect management Manufacturing Packaging Manufacturing With this solution portfolio, semiconductor
    [Show full text]
  • Design for Manufacturing (Dfm) in Submicron Vlsi Design
    DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY August 2007 Major Subject: Computer Engineering DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Jiang Hu Committee Members, Weiping Shi Duncan Walker Vivek Sarin Head of Department, Costas N. Georghiades August 2007 Major Subject: Computer Engineering iii ABSTRACT Design for Manufacturing (DFM) in Submicron VLSI Design. (August 2007) Ke Cao, B.S., University of Science and Technology of China; M.S., University of Minnesota Chair of Advisory Committee: Dr. Jiang Hu As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII file to the foundry and expect very good man- ufacturing and parametric yield. This is largely due to the enormous challenges in the manufacturing stage as the feature size continues to shrink. Thus, the idea of DFM (Design for Manufacturing) is getting very popular. Even though there is no universally accepted definition of DFM, in my opinion, one of the major parts of DFM is to bring manufacturing information into the design stage in a way that is understood by designers. Consequently, designers can act on the information to improve both manufacturing and parametric yield.
    [Show full text]
  • Intel FPGA Product Catalog Devices: 10 Nm Device Portfolio Intel Agilex FPGA and Soc Overview
    • Cover TBD INTEL® FPGA PRODUCT CATALOG Version 19.3 CONTENTS Overview Acceleration Platforms and Solutions Intel® FPGA Solutions Portfolio 1 Intel FPGA Programmable Acceleration Overview 61 Devices Intel Acceleration Stack for Intel Xeon® CPU with FPGAs 62 Intel FPGA Programmable Acceleration Cards 63 10 nm Device Portfolio - Intel AgilexTM - Intel Programmable Acceleration Card with 63 FPGA and SoC Overview 2 Intel Arria 10 GX FPGA - Intel Agilex FPGA Features 4 - Intel FPGA Programmable Acceleration Card D5005 64 Generation 10 Device Portfolio - Intel FPGA Programmable Acceleration Card N3000 65 - Generation 10 FPGAs and SoCs 6 - Intel FPGA Programmable Acceleration Card 66 - Intel Stratix® 10 FPGA and SoC Overview 7 Comparison - Intel Stratix 10 FPGA Features 9 Accelerated Workload Solutions 67 - Intel Stratix 10 SoC Features 11 - Intel Stratix 10 TX Features 13 - Intel Stratix 10 MX Features 15 Design Tools, OS Support, and Processors - Intel Stratix 10 DX Features 17 Intel Quartus® Prime Software 68 - Intel Arria® 10 FPGA and SoC Overview 20 DSP Builder for Intel FPGAs 71 - Intel Arria 10 FPGA Features 21 Intel FPGA SDK for OpenCL™ 72 - Intel Arria 10 SoC Features 23 - Intel Cyclone® 10 FPGA Overview 25 Intel SoC FPGA Embedded Development Suite 73 - Intel Cyclone 10 GX FPGA Features 26 SoC Operating System Support 74 - Intel Cyclone 10 LP FPGA Features 27 Nios® II Processor 75 - Intel MAX® 10 FPGA Overview 29 - Intel MAX 10 FPGA Features 30 Nios II Processor Embedded Design Suite 76 Nios II Processor Operating System Support 28
    [Show full text]
  • Intel FPGA SDK for Opencl Pro Edition: Programming Guide Send Feedback
    Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-OCL002 | 2021.06.23 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Intel® FPGA SDK for OpenCL™ Overview......................................................................... 7 1.1. Intel FPGA SDK for OpenCL Pro Edition Programming Guide Prerequisites......................7 1.2. Intel FPGA SDK for OpenCL FPGA Programming Flow..................................................8 2. Intel FPGA SDK for OpenCL Offline Compiler Kernel Compilation Flows........................ 10 2.1. One-Step Compilation for Simple Kernels................................................................ 11 2.2. Multistep Intel FPGA SDK for OpenCL Pro Edition Design Flow.................................... 12 3. Obtaining General Information on Software, Compiler, and Custom Platform...............16 3.1. Displaying the Software Version (version)............................................................... 16 3.2. Displaying the Compiler Version (-version).............................................................. 16 3.3. Listing the Intel FPGA SDK for OpenCL Utility Command Options (help).......................17 3.3.1. Displaying Information on an Intel FPGA SDK for OpenCL Utility Command Option (help <command_option>)............................................................. 17 3.4. Listing the Intel FPGA SDK for OpenCL Offline Compiler Command Options (no argument, -help, or -h)......................................................................................17
    [Show full text]