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AN 821: Interface Planning for Intel® Stratix® 10 Fpgas

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AN 821: Interface Planning for Intel® Stratix® 10 Fpgas AN 821: Interface Planning for Intel® Stratix® 10 FPGAs Updated for Intel® Quartus® Prime Design Suite: 17.1 Subscribe AN-821 | 2017.12.15 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Interface Planning for Intel® Stratix® 10 FPGAs............................................................. 3 1.1. FPGA_TOP Design Example Overview....................................................................... 3 1.2. Design Example Files............................................................................................. 5 1.3. Design Example Walkthrough.................................................................................. 6 1.3.1. Step 1: Project Setup.................................................................................6 1.3.2. Step 2: Initialize Interface Planner............................................................... 7 1.3.3. Step 3: Update Plan with Project Assignments............................................... 8 1.3.4. Step 4: Plan Periphery Placement................................................................ 8 1.3.5. Step 5: Report Placement Data.................................................................. 14 1.3.6. Step 6: Validate and Export Plan Constraints............................................... 15 1.3.7. Step 7: Apply Plan Constraints...................................................................16 1.4. Modifying the FPGA_TOP Design Example................................................................17 1.4.1. Modifying the VHDL Generics.....................................................................17 1.4.2. Changing the Target FPGA.........................................................................19 1.5. Document Revision History....................................................................................21 ® ® AN 821: Interface Planning for Intel Stratix 10 FPGAs Send Feedback 2 AN-821 | 2017.12.15 Send Feedback 1. Interface Planning for Intel® Stratix® 10 FPGAs This application note demonstrates Intel® Stratix® 10 interface pin planning with the Intel Quartus® Prime Pro Edition Interface Planner. The Interface Planner is a graphical planning tool that allows you to visualize and rapidly define a legal device floorplan before creating the final pinout for PCB manufacture. This application note walks you through Interface Planner pin planning for a transceiver based design that also includes an external memory interface (EMIF). Figure 1. Intel Quartus Prime Pro Edition Interface Planner Design Elements Chip View Flow Control Related Information • Interface Planning, Intel Quartus Prime Pro Edition Handbook • Interface Planning Online Training 1.1. FPGA_TOP Design Example Overview This application note uses the FPGA_TOP Intel Stratix 10 design example to illustrate pin planning with Interface Planner. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. Interface Planning for Intel® Stratix® 10 FPGAs AN-821 | 2017.12.15 Figure 2. FPGA_TOP Design Example Block Diagram FPGA_TOP FPGA_CORE_BLK FPGA_EMIF_BLK FPGA_IO_BLK FPGA_IP_BLK FPGA_GX_BLK FPGA_TOP is a transceiver and EMIF based design that comprises a hierarchy of six main VHDL blocks. By default, the design targets an Intel Stratix 10 1SG280HU1F50E1VG device. This device provides 96 transceivers, 4 x PCIe* Hard IP blocks, and 4 x 100G MAC that the design requires. The FPGA_TOP design example is ready to use with this application note, or you can optionally modify this the design example to suit your system requirements, as Modifying the FPGA_TOP Design Example on page 17 describes. Figure 3. FPGA_GX_BLK Transceiver Based System tx_analogreset User-Coded tx_digitalreset Transceiver PHY Instance Reset rx_analogreset Controller Transmitter clock rx_digitalreset Transmitter PCS PMA tx_cal_busy rx_cal_busy Receiver rx_is_lockedtoref Receiver PCS PMA rx_is_lockedtodata pll_locked pll_cal_busy pll_powerdown You can logical OR the pll_cal_busy and tx_cal_busy signals. Transmit PLL FPGA_GX_BLK does not support every combination of a transceiver based design. More complex bonding schemes, such as schemes that require a mixture of TX PLLs, require more adaptations of this design example. Refer to the Intel Stratix 10 GX/SX Device Overview for the quantity and type of resources in Intel Stratix 10 devices. The remainder of this document describes the design example blocks, and provides a walkthrough of pin planning with Interface Planner. Related Information Intel Stratix 10 GX/SX Device Overview ® ® AN 821: Interface Planning for Intel Stratix 10 FPGAs Send Feedback 4 1. Interface Planning for Intel® Stratix® 10 FPGAs AN-821 | 2017.12.15 1.2. Design Example Files Follow these steps to use the design example files this application note describes: 1. Download the FPGA_TOP design example project archive file at: https://www.altera.com/content/dam/altera-www/global/en_US/others/ literature/tt/s10_interface_planner_example.qar 2. Launch the Intel Quartus Prime Pro Edition software. 3. Click Project ➤ Restore Archived Project. 4. Select the s10_interface_planner_example.qar Archive name, and then click OK. The following project files restore into the Destination folder (by default, the s10_interface_planner_example_restored directory). Figure 4. FGPA_TOP Intel Stratix 10 Design Example Directories s10_interface_planner_example_restored FPGA_CORE FPGA_EMIF_BLK FPGA_GX_BLK FPGA_IO FPGA_IP_BLK FPGA_TOP Table 1. FPGA_TOP Design Example Files File Name Description FPGA_TOP.vhd Contains the top level of the example design. This is the only file you modify for this application note. You can specify the IP variant you require, and the number of channels if instantiating the IP more than once. You can also control whether channels are on only the left, right, or on both sides of the device. FPGA_CORE_BLK.vhd Contains RTL logic that creates reset circuitry inside the FPGA for use when targeting hardware. FPGA_EMIF_BLK.vhd Contains one instance of DDR4 External Memory Interface (EMIF) Intel FPGA IP in x72 bit mode. This is a common configuration. If you require more than one instance of DDR4 memory, copy and instantiate in the FPGA_TOP.vhd file. FPGA_IO_BLK.vhd Contains the following common Intel FPGA IP that connect to general purpose I/O pins: • ALTLVDS_RX (DPA, non-DPA, and soft-cdr modes) • ALTLVDS_TX • PHY Lite FPGA_IP_BLK.vhd Contains the following common Intel FPGA IP: • PCIe (Gen 1/2/3) x1, x4 x8 configurations (scalable by instance) • Multi-Rate Ethernet (scalable using single channel) • 10G Base-KR (scalable using single channel) • SerialLite III (scalable using single channel) • LL 40G (scalable by instance) • Interlaken* 100G (scalable by instance) • JESD204B (scalable using single channel) ® ® Send Feedback AN 821: Interface Planning for Intel Stratix 10 FPGAs 5 1. Interface Planning for Intel® Stratix® 10 FPGAs AN-821 | 2017.12.15 1.3. Design Example Walkthrough This walkthrough covers the following pin planning steps using the FPGA_TOP example design: • Step 1: Project Setup on page 6 • Step 2: Initialize Interface Planner on page 7 • Step 3: Update Plan with Project Assignments on page 8 • Step 4: Plan Periphery Placement on page 8 • Step 5: Report Placement Data on page 14 • Step 6: Validate and Export Plan Constraints on page 15 • Step 7: Apply Plan Constraints on page 16 1.3.1. Step 1: Project Setup The FPGA_TOP project is ready to use with this application note. However, in a real design scenario, you must perform some initial project setup before using Interface Planner. Interface Planner requires at least a partially complete, synthesized Intel Quartus Prime Pro Edition project as input. You can also use Interface Planner to place a fully complete design project. Before planning in Interface Planner, you must typically prepare the project in the following ways. These steps are already complete for the FPGA_TOP project. • Fully define known device periphery interfaces. • Instantiate all known interface IP cores. • Declare all general purpose I/Os. • Define the I/O standard, voltage, drive strength, and slew rate for all general purpose I/Os. • Define the core clocking (optional, but recommended). • Connect all interfaces of the periphery IP to virtual pins or test logic. This technique creates loop backs on any interfaces in the shell design, helping to ensure that periphery interfaces persist after synthesis optimization. Follow these steps to open and synthesize the FPGA_TOP example design: 1. In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project and open the FPGA_TOP.qpf project file. Note: You can optionally change the target device to match a different PCB or your
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