AN 821: Interface Planning for Intel® Stratix® 10 Fpgas

AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

Updated for Intel® Quartus® Prime Design Suite: 17.1

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Contents

1. Interface Planning for Intel® Stratix® 10 FPGAs...... 3 1.1. FPGA_TOP Design Example Overview...... 3 1.2. Design Example Files...... 5 1.3. Design Example Walkthrough...... 6 1.3.1. Step 1: Project Setup...... 6 1.3.2. Step 2: Initialize Interface Planner...... 7 1.3.3. Step 3: Update Plan with Project Assignments...... 8 1.3.4. Step 4: Plan Periphery Placement...... 8 1.3.5. Step 5: Report Placement Data...... 14 1.3.6. Step 6: Validate and Export Plan Constraints...... 15 1.3.7. Step 7: Apply Plan Constraints...... 16 1.4. Modifying the FPGA_TOP Design Example...... 17 1.4.1. Modifying the VHDL Generics...... 17 1.4.2. Changing the Target FPGA...... 19 1.5. Document Revision History...... 21

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1. Interface Planning for Intel® Stratix® 10 FPGAs

This application note demonstrates Intel® Stratix® 10 interface pin planning with the Intel Quartus® Prime Pro Edition Interface Planner.

The Interface Planner is a graphical planning tool that allows you to visualize and rapidly define a legal device floorplan before creating the final pinout for PCB manufacture. This application note walks you through Interface Planner pin planning for a transceiver based design that also includes an external memory interface (EMIF).

Figure 1. Intel Quartus Prime Pro Edition Interface Planner

Design Elements

Chip View

Flow Control

Related Information • Interface Planning, Intel Quartus Prime Pro Edition Handbook • Interface Planning Online Training

1.1. FPGA_TOP Design Example Overview

This application note uses the FPGA_TOP Intel Stratix 10 design example to illustrate pin planning with Interface Planner.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. Interface Planning for Intel® Stratix® 10 FPGAs AN-821 | 2017.12.15

Figure 2. FPGA_TOP Design Example Block Diagram

FPGA_TOP

FPGA_CORE_BLK

FPGA_EMIF_BLK FPGA_IO_BLK FPGA_IP_BLK FPGA_GX_BLK

FPGA_TOP is a transceiver and EMIF based design that comprises a hierarchy of six main VHDL blocks. By default, the design targets an Intel Stratix 10 1SG280HU1F50E1VG device. This device provides 96 transceivers, 4 x PCIe* Hard IP blocks, and 4 x 100G MAC that the design requires. The FPGA_TOP design example is ready to use with this application note, or you can optionally modify this the design example to suit your system requirements, as Modifying the FPGA_TOP Design Example on page 17 describes.

Figure 3. FPGA_GX_BLK Transceiver Based System tx_analogreset User-Coded tx_digitalreset Transceiver PHY Instance Reset rx_analogreset Controller Transmitter clock rx_digitalreset Transmitter PCS PMA tx_cal_busy rx_cal_busy Receiver rx_is_lockedtoref Receiver PCS PMA rx_is_lockedtodata pll_locked pll_cal_busy pll_powerdown You can logical OR the pll_cal_busy and tx_cal_busy signals. Transmit PLL

FPGA_GX_BLK does not support every combination of a transceiver based design. More complex bonding schemes, such as schemes that require a mixture of TX PLLs, require more adaptations of this design example. Refer to the Intel Stratix 10 GX/SX Device Overview for the quantity and type of resources in Intel Stratix 10 devices.

The remainder of this document describes the design example blocks, and provides a walkthrough of pin planning with Interface Planner.

Related Information Intel Stratix 10 GX/SX Device Overview

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1.2. Design Example Files

Follow these steps to use the design example files this application note describes:

1. Download the FPGA_TOP design example project archive file at: https://www.altera.com/content/dam/altera-www/global/en_US/others/ literature/tt/s10_interface_planner_example.qar 2. Launch the Intel Quartus Prime Pro Edition software. 3. Click Project ➤ Restore Archived Project. 4. Select the s10_interface_planner_example.qar Archive name, and then click OK. The following project files restore into the Destination folder (by default, the s10_interface_planner_example_restored directory).

Figure 4. FGPA_TOP Intel Stratix 10 Design Example Directories

s10_interface_planner_example_restored FPGA_CORE

FPGA_EMIF_BLK FPGA_GX_BLK FPGA_IO

FPGA_IP_BLK FPGA_TOP

Table 1. FPGA_TOP Design Example Files

File Name Description

FPGA_TOP.vhd Contains the top level of the example design. This is the only file you modify for this application note. You can specify the IP variant you require, and the number of channels if instantiating the IP more than once. You can also control whether channels are on only the left, right, or on both sides of the device.

FPGA_CORE_BLK.vhd Contains RTL logic that creates reset circuitry inside the FPGA for use when targeting hardware.

FPGA_EMIF_BLK.vhd Contains one instance of DDR4 External Memory Interface (EMIF) Intel FPGA IP in x72 bit mode. This is a common configuration. If you require more than one instance of DDR4 memory, copy and instantiate in the FPGA_TOP.vhd file.

FPGA_IO_BLK.vhd Contains the following common Intel FPGA IP that connect to general purpose I/O pins: • ALTLVDS_RX (DPA, non-DPA, and soft-cdr modes) • ALTLVDS_TX • PHY Lite

FPGA_IP_BLK.vhd Contains the following common Intel FPGA IP: • PCIe (Gen 1/2/3) x1, x4 x8 configurations (scalable by instance) • Multi-Rate Ethernet (scalable using single channel) • 10G Base-KR (scalable using single channel) • SerialLite III (scalable using single channel) • LL 40G (scalable by instance) • Interlaken* 100G (scalable by instance) • JESD204B (scalable using single channel)

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1.3. Design Example Walkthrough

This walkthrough covers the following pin planning steps using the FPGA_TOP example design: • Step 1: Project Setup on page 6 • Step 2: Initialize Interface Planner on page 7 • Step 3: Update Plan with Project Assignments on page 8 • Step 4: Plan Periphery Placement on page 8 • Step 5: Report Placement Data on page 14 • Step 6: Validate and Export Plan Constraints on page 15 • Step 7: Apply Plan Constraints on page 16

1.3.1. Step 1: Project Setup

The FPGA_TOP project is ready to use with this application note. However, in a real design scenario, you must perform some initial project setup before using Interface Planner.

Interface Planner requires at least a partially complete, synthesized Intel Quartus Prime Pro Edition project as input. You can also use Interface Planner to place a fully complete design project. Before planning in Interface Planner, you must typically prepare the project in the following ways. These steps are already complete for the FPGA_TOP project. • Fully define known device periphery interfaces. • Instantiate all known interface IP cores. • Declare all general purpose I/Os. • Define the I/O standard, voltage, drive strength, and slew rate for all general purpose I/Os. • Define the core clocking (optional, but recommended). • Connect all interfaces of the periphery IP to virtual pins or test logic. This technique creates loop backs on any interfaces in the shell design, helping to ensure that periphery interfaces persist after synthesis optimization.

Follow these steps to open and synthesize the FPGA_TOP example design: 1. In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project and open the FPGA_TOP.qpf project file. Note: You can optionally change the target device to match a different PCB or your own design requirements, as Modifying the FPGA_TOP Design Example on page 17 describes. 2. To run synthesis and apply the interface plan, click Analysis & Synthesis on the Compilation Dashboard.

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Figure 5. Interface Planner Button and Compilation Dashboard

Interface Planner Button

1.3.2. Step 2: Initialize Interface Planner

After synthesis is complete you can launch Interface Planner and initialize with synthesis results. Follow these steps to open the project in Interface Planner: 1. Click Tools ➤ Interface Planner (or click the Interface Planner button). The Interface Planner launches and displays a Welcome page and the Home tab. 2. On the Flow control, click Initialize Interface Planner. This command starts background Fitter validation of your planning, and imports any existing assignments from the project. After initialization is complete, the Fitter dynamically validates your interface plan as you make changes in Interface Planner.

Figure 6. Initialize Interface Planner

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1.3.3. Step 3: Update Plan with Project Assignments

Before planning the device periphery, you must reconcile any project assignments that Interface Planner imports, and run Update Plan to update the plan with these assignments. 1. On the Flow control, click View Assignments (or click the Assignments tab). The Assignments tab displays the imported project assignments and notes any conflicts. At any time, click Plan ➤ Reset Plan to reenable all project assignments.

Figure 7. Interface Planner Assignments Tab

2. The Assignments tab displays the fixed pin locations for the transceiver reference clock pins on the left and right-hand side of the device. In a real planning session, you resolve any conflicts between assignments. You can easily filter the list by assignment name or status to enable or disable conflicting assignments. 3. After resolving any assignment conflicts, click Update Plan on the Flow control. Interface Planner indicates when application of project assignments is complete.

1.3.4. Step 4: Plan Periphery Placement

The Interface Planner helps you to quickly plan device periphery placement. You can directly place elements onto a graphical representation of the device floorplan, while simultaneously validating the placement legality for final implementation. While you place design elements onto the Chip or Package view, the Fitter dynamically guides you to make only legal placements. Interface Planner validates your plan against any existing location assignments that you import from the project. The following sections describe planning for each periphery block.

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Follow these steps to setup Interface Planner for periphery placement: 1. To interactively place IP cores and other design elements in legal locations in the device periphery, click Plan Design on the Flow control. The Plan tab displays a list of your project's design elements, alongside a graphical abstraction of the target device architecture.

Figure 8. Intel Quartus Prime Pro Edition Interface Planner

Design Elements

Chip View

Flow Control

2. On the Plan tab, click Package View and select Package Bottom. These options display a view that shows the pin placement on the left side of the device. This view is similar to the Intel Quartus Prime Pro Edition Pin Planner that you use to compare the final results.

Figure 9. Package Bottom in Package View

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1.3.4.1. Plan the External Memory Interface

Follow these steps to plan the pinout of the EMIF interface by identifying legal and available placement locations. 1. In the Interface Planner Plan tab, click the IP filter button. This filter automatically shows only the IP in the design example. 2. In the Design Elements list, expand the EMIF_TOP_I0 block, and then select the emif_s10_0 design element. 3. Click the >> button next to the emif_s10_0 design element name to display the Legal Locations for placement.

Figure 10. Locations List Button Click to List Legal Locations

4. Select any legal location in the list to highlight that floorplan location. For example, click EMIF_L12_X53_Y325_Y400 in the Locations list. The location you select highlights in the floorplan.

Figure 11. Location Selected

5. Double-click EMIF_L12_X53_Y325_Y400 in the Legal Locations list to place the entity at the location.

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Figure 12. EMIF Fixed Locations

EMIF

1.3.4.2. Plan the PCIe Interface

The Interface Planner helps you to locate available locations and pin placement for the Intel FPGA IP for PCIe and the SerialLite III Intel FPGA IP interfaces. The following sections describe planning for these IP.

Follow these steps to plan the PCIe interface: 1. In Interface Planner, click the IP filter button. 2. In the Design Elements list, expand the IP_TOP_I0 block to select the PCIe dut design element. The design example FPGA_TOP.vhd file specifies to only use the left side of the device. 3. Click the >> button next to dut to display Legal Locations for placement. Interface Planner shows one legal location for the left side of the device.

Figure 13. Legal Locations Button

4. Double-click the HSSI_DUPLUX_CHANNEL_CLUSTER_24 to place the elements in the floorplan. This placement then assigns this PCIe IP to this fixed location.

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Figure 14. PCIe Fixed Placement

PCIe

1.3.4.3. Plan the SerialLite III Interface

Follow these steps to plan the SerialLite III interface: 1. In the Design Element list, select the SerialLite III sl3_0 design entity under IP_TOP_IO. The design example FPGA_TOP.vhd file specifies to only use the right side of the device.

Figure 15. SerialLite III Locations Button

2. Click the >> button next to the sl3_0 design element to display Legal Locations. Interface Planner shows 10 legal locations for the right side of the device.

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Figure 16. SerialLite III Legal Location

3. Double-click the HSSI_DUPLUX_CHANNEL_CLUSTER_95 legal location to place the elements in the floorplan. This placement then assigns this SerialLite III IP to this fixed location.

1.3.4.4. Plan the Transceiver PHY Interface

Follow these steps to identify legal locations and place FPGA_GX_BLK. 1. In the Design Elements list, expand the TXCVR_TOP_I0 block to find the xcvr_native_s10_htile_0 transceiver PHY design element. The design example FPGA_TOP.vhd file specifies to use the left and right sides of the device. 2. Click the >> button next to the xcvr_native_s10_htile_0 design element to display Legal Locations. Interface Planner shows more than 10 legal locations for the left and right sides of the device. 3. To automatically place the elements in a legal location, right-click the xcvr_native_s10_htile_0 and click Autoplace Selected. This placement then assigns this GX_BLK to a fixed location on the left and right sides of the device.

Figure 17. Transceiver Native PHY Fixed Placement

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1.3.4.5. Complete and Save the Floorplan

The following figure shows the complete pin allocation for the IP in FPGA_TOP.vhd. You can now save this plan for use in subsequent Interface Planner sessions. Interface Planner saves your plan in Interface Planner Floorplan Format (.plan). You can then load a .plan file in Interface Planner to use the floorplan.

Figure 18. Complete Design Floorplan

1. To save the floorplan, click Save Floorplan in Interface Planner. 2. In the Save As dialog box, specify a descriptive name for the .plan file, and then click Save.

1.3.5. Step 5: Report Placement Data

You can generate Interface Planner placement and connectivity reports to help locate cells and make the best decisions about placement for the interfaces and elements in your design.

Follow these steps to access the placement reports 1. Click the Reports tab. This tab displays a range of reports. 2. In the Tasks list, click any report name to generate that report. The reports are interactive, allowing you select and Place, Unplace, or Report detailed data about the selected element. 3. In the Flow control, click View Summary Report. The Interface Planner Summary lists details about IP block and periphery cell placement.

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Figure 19. Interface Planner Summary Report

4. In the Tasks list, click Report All Placed Pins. The Placed Pins report shows that all IP have pin assignments.

Figure 20. Report All Placed Pins

1.3.6. Step 6: Validate and Export Plan Constraints

You must validate your interface plan before exporting the plan constraints to your project. Validation must confirm that the Fitter can place all remaining unplaced design elements. After validating the interface plan, you can export the constraints and apply the interface plan to an Intel Quartus Prime Pro Edition project. When you export the constraints, Interface Planner generates and output Tcl script that you use to apply the constraints to a project.

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Follow these steps to validate and export the plan constraints: 1. On the Flow control, click Validate Plan. The Fitter confirms placement of all remaining unplaced design elements. You must correct any errors before you can export constraints. Interface Planner reports a “success” message when validation is complete. 2. On the Flow control, click Export Constraints, make any changes to Output file name or Section to export, and then click OK. A message indicates when export is successful.

Figure 21. Export Constraints

3. Close Interface Planner and return to your project in the Intel Quartus Prime Pro Edition software. You can now add these constraints to a project by sourcing the Tcl script from the command prompt, as the following step describes.

1.3.7. Step 7: Apply Plan Constraints

Follow these steps to apply the Interface Planner constraints to the FPGA_TOP project: 1. In the Intel Quartus Prime Pro Edition software, close the FPGA_TOP project. 2. Open a command shell and type the following command in the FGPA_TOP project directory. The Intel Quartus Prime Pro Edition executable must be in your PATH to run this command.

quartus_sh -t FPGA_TOP.pdp_assignments.tcl

3. Reopen the FPGA_TOP project in the Intel Quartus Prime Pro Edition software. The project now contains the constraints that pdp_assignments.tcl defines. 4. To run synthesis and apply the interface plan, click Analysis & Synthesis on the Compilation Dashboard. 5. To run full compilation, click Compile Design on the Compilation Dashboard. 6. Following compilation, click Assignments ➤ Pin Planner to view placement results and complete the design floorplan.

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Figure 22. Full Design Floorplan in Pin Planner

By following the guidelines this application note describes, you can modify the FPGA_TOP design example to create a pinout that suits your systems and requirements.

Related Information • External Memory Interface Handbook • SerialLite III Streaming IP Core User Guide • Intel Stratix 10 Avalon -MM Interface for PCIe Solutions User Guide • Intel Stratix 10 Avalon -ST and Single Root I/O Virtualization (SR-IOV) Interface for PCIe Solutions User Guide • Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide

1.4. Modifying the FPGA_TOP Design Example

You can modify the FPGA_TOP design example to more closely match your application or requirements. For example, you can modify the VHDL generics to activate IP in the system, or you can change the target device to meet your resource or PCB requirements. The following sections describe making these modifications to the design example files or project settings.

1.4.1. Modifying the VHDL Generics

The FPGA_TOP.vhd file uses VHDL generics to pass parameters that scale the channels and activate which IP you require in the system. You can modify these generics to match your design requirements, as the following examples show.

FPGA_TOP has a simple clocking scheme that clocks all transceiver channels with the same transmit PLL. You can select whether the design example uses the CMU, ATX, or FPLL to clock the transceivers. Select the CMU, ATX, or FPLL within sixpack configuration. Select xN (ATX or FPLL) for outside sixpack configuration. Use of the CMU is not an option for outside sixpack configurations. You can also modify the design to implement a more complex clocking scheme. The REFCLK pins for the standard and enhanced pcs transceivers and their IP protocols are at fixed pin locations on the left and right-hand side of the device to make the pin planning easier.

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Example 1. Modifying PCS Channels of a Transceiver in FPGA_TOP.vhd

The following example shows activating the standard PCS transceiver channels by setting the Boolean expression to true, and setting the number of channels to 2:

ACTIVATE_TXCVR_STD_L : boolean:= true; TXCVR_STD_NUM_CHANNELS_L : integer:= 2;

Conversely, the following example deactivates the enhanced PCS transceiver channels by setting the Boolean expression to false and setting the number of channels to 1:

ACTIVATE_TXCVR_ENH_L : boolean:= false; TXCVR_ENH_NUM_CHANNELS_L : integer:= 1;

Example 2. Modifying Transceiver PLL Type and Clock Line in FPGA_TOP.vhd

The following example shows changing the Transceiver PLL type and clock line by modifying the TX_PLL_TYPE strings in FPGA_TOP.vhd:

-- LEFT HAND SIDE TX PLL SELECTION -- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_STD_L : string:= "ATX_xN";

-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_ENH_L : string:= "ATX_xN";

-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_IP_PCIE_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_TSE_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_XAUI_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_ONEG_TENG_BASE_KR_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_SLIII_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_LL_40G_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_ILKN_100G_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_JESD204B_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_SDI_TRIPLERATE_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_DISPLAYPORT_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_HDMI_L : string:= "ATX_xN"; TX_PLL_TYPE_IP_MULTIRATE_ETH_L : string:= "ATX_xN";

Example 3. Complete Modification Example

The following example shows changes to FPGA_TOP.vhd to implement the following design requirement specifications:

FPGA Left Side Specifications • 2 x transceiver channel using standard PCS • 1 x PCIe Gen 3 x 8 • ATX with PLL with xN line clocking

ACTIVATE_TXCVR_STD_L : boolean:= true; TXCVR_STD_NUM_CHANNELS_L : integer:= 2;

ACTIVATE_PCIe_g3x8_L : boolean:= true; PCIe_g3x8_NUM_INSTANCES_L : integer:= 1;

-- LEFT HAND SIDE TX PLL SELECTION -- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_STD_L : string:= "ATX_xN";

-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_ENH_L : string:= "ATX_xN";

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FPGA Right Side Specifications • 2 x transceiver channel using enhanced PCS • 1 x SerialLite III IP • ATX with PLL with xN line clocking

ACTIVATE_TXCVR_ENH_R : boolean:= true; TXCVR_ENH_NUM_CHANNELS_R : integer:= 2;

ACTIVATE_SLIII_R : boolean:= true; SLIII_NUM_CHANNELS_R : integer:= 1;

-- RIGHT HAND SIDE TX PLL SELECTION -- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_STD_R : string := "ATX_xN";

-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_ENH_R : string := "ATX_xN";

-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN" TX_PLL_TYPE_IP_PCIE_R : string := "ATX_xN"; TX_PLL_TYPE_IP_TSE_R : string := "ATX_xN"; TX_PLL_TYPE_IP_XAUI_R : string := "ATX_xN"; TX_PLL_TYPE_IP_ONEG_TENG_BASE_KR_R : string := "ATX_xN"; TX_PLL_TYPE_IP_SLIII_R : string := "ATX_xN"; TX_PLL_TYPE_IP_LL_40G_R : string := "ATX_xN"; TX_PLL_TYPE_IP_ILKN_100G_R : string := "ATX_xN"; TX_PLL_TYPE_IP_JESD204B_R : string := "ATX_xN"; TX_PLL_TYPE_IP_SDI_TRIPLERATE_R : string := "ATX_xN"; TX_PLL_TYPE_IP_DISPLAYPORT_R : string := "ATX_xN"; TX_PLL_TYPE_IP_HDMI_R : string := "ATX_xN"; TX_PLL_TYPE_IP_MULTIRATE_ETH_R : string := "ATX_xN";

1.4.2. Changing the Target FPGA

By default the FPGA _TOP design example targets the 1SG280HU1F50E1VG Intel Stratix 10 device. You can change the target device to match your resource or performance requirements. When you change the target device, you must allow the Compiler to remove all fixed location assignments, and automatically regenerate any IP for the new device.

Follow these steps to change the target device for the design example: 1. In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project and open the FPGA_TOP.qpf project file. 2. Click Assignments ➤ Device.

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Figure 23. Target Device Selection

3. In the Available Devices list, select an Intel Stratix 10 device that meets your design and PCB requirements. Click Yes when a message confirms that changing the device removes any existing location assignments. 4. If the Intel Quartus Prime Pro Edition software indicates that one or more Intel FPGA IP core is now outdated, follow these steps to upgrade the IP: a. Click Assignments ➤ Settings ➤ IP Settings, and enable Always regenerate design files for IP cores. This option ensures that all IP is the latest version following compilation.

Figure 24. IP Settings Dialog Box

b. Click OK. 5. When ready, compile the design for the new target device.

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1.5. Document Revision History

Table 2. Document Revision History

Document Version Software Version Changes

2017.12.10 17.1.0 Initial release of the document.

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