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Intel® Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization

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Intel® Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization Intel® Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization Updated for Intel® Quartus® Prime Design Suite: 17.1 Subscribe QPS5V2 | 2017.11.06 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1 Constraining Designs..................................................................................................... 11 1.1 Constraining Designs with Intel Quartus Prime Tools.................................................. 11 1.1.1 Global Constraints and Assignments............................................................ 11 1.1.2 Node, Entity, and Instance-Level Constraints................................................ 12 1.1.3 Probing Between Components of the Intel Quartus Prime GUI......................... 14 1.1.4 Specifying Individual Timing Constraints...................................................... 14 1.2 Constraining Designs with Tcl Scripts....................................................................... 16 1.2.1 Generating Intel Quartus Prime Settings Files............................................... 16 1.2.2 Timing Analysis with .sdc Files and Tcl Scripts............................................... 18 1.2.3 Using Tcl-only Script Flows......................................................................... 19 1.3 A Fully Iterative Scripted Flow................................................................................ 22 1.4 Document Revision History.....................................................................................22 2 Managing Device I/O Pins............................................................................................. 24 2.1 I/O Planning Overview...........................................................................................25 2.1.1 Basic I/O Planning Flow............................................................................. 25 2.1.2 Integrating PCB Design Tools......................................................................26 2.1.3 Intel Device Terms.................................................................................... 27 2.2 Assigning I/O Pins.................................................................................................27 2.2.1 Assigning to Exclusive Pin Groups............................................................... 28 2.2.2 Assigning Slew Rate and Drive Strength.......................................................28 2.2.3 Assigning Differential Pins.......................................................................... 28 2.2.4 Entering Pin Assignments with Tcl Commands............................................... 30 2.2.5 Entering Pin Assignments in HDL Code.........................................................30 2.3 Importing and Exporting I/O Pin Assignments...........................................................32 2.3.1 Importing and Exporting for PCB Tools......................................................... 32 2.3.2 Migrating Assignments to Another Target Device........................................... 33 2.4 Validating Pin Assignments.....................................................................................34 2.4.1 I/O Assignment Validation Rules................................................................. 34 2.4.2 Checking I/O Pin Assignments in Real-Time.................................................. 35 2.4.3 Running I/O Assignment Analysis................................................................36 2.4.4 Understanding I/O Analysis Reports.............................................................40 2.5 Verifying I/O Timing.............................................................................................. 40 2.5.1 Running Advanced I/O Timing.....................................................................41 2.5.2 Adjusting I/O Timing and Power with Capacitive Loading................................ 45 2.6 Viewing Routing and Timing Delays......................................................................... 45 2.7 Analyzing Simultaneous Switching Noise.................................................................. 45 2.8 Scripting API........................................................................................................ 45 2.8.1 Generate Mapped Netlist............................................................................45 2.8.2 Reserve Pins............................................................................................ 46 2.8.3 Set Location.............................................................................................46 2.8.4 Exclusive I/O Group.................................................................................. 46 2.8.5 Slew Rate and Current Strength..................................................................46 2.9 Document Revision History.....................................................................................47 3 Simultaneous Switching Noise (SSN) Analysis and Optimizations..................................48 3.1 Simultaneous Switching Noise (SSN) Analysis and Optimizations................................. 48 3.2 Definitions........................................................................................................... 48 Intel® Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization 2 Contents 3.3 Understanding SSN............................................................................................... 49 3.4 SSN Estimation Tools.............................................................................................51 3.5 SSN Analysis Overview.......................................................................................... 52 3.5.1 Performing Early Pin-Out SSN Analysis.........................................................53 3.5.2 Performing Final Pin-Out SSN Analysis......................................................... 54 3.6 Design Factors Affecting SSN Results.......................................................................54 3.7 Optimizing Your Design for SSN Analysis.................................................................. 54 3.7.1 Optimizing Pin Placements for Signal Integrity.............................................. 55 3.7.2 Specifying Board Trace Model Settings......................................................... 56 3.7.3 Defining PCB Layers and PCB Layer Thickness...............................................57 3.7.4 Specifying Signal Breakout Layers............................................................... 59 3.7.5 Creating I/O Assignments.......................................................................... 60 3.7.6 Decreasing Pessimism in SSN Analysis.........................................................60 3.7.7 Excluding Pins as Aggressor Signals.............................................................61 3.8 Performing SSN Analysis and Viewing Results........................................................... 61 3.8.1 Understanding the SSN Reports.................................................................. 61 3.8.2 Viewing SSN Analysis Results in the Pin Planner............................................ 62 3.9 Decreasing Processing Time for SSN Analysis........................................................... 63 3.10 Scripting Support................................................................................................ 63 3.10.1 Optimizing Pin Placements for Signal Integrity............................................ 64 3.10.2 Defining PCB Layers and PCB Layer Thickness............................................. 64 3.10.3 Specifying Signal Breakout Layers............................................................. 65 3.10.4 Decreasing Pessimism in SSN Analysis....................................................... 65 3.10.5 Performing SSN Analysis.......................................................................... 65 3.11 Document Revision History...................................................................................66 4 Command Line Scripting............................................................................................... 67 4.1 Benefits of Command-Line Executables....................................................................67 4.2 Introductory Example............................................................................................67 4.3 Command-Line Scripting Help.................................................................................68 4.4 Project Settings with Command-Line Options............................................................69 4.4.1 Option Precedence.................................................................................... 69 4.5 Compilation with quartus_sh --flow......................................................................... 71 4.6 Text-Based Report Files......................................................................................... 72 4.7 Using Command-Line Executables in Scripts............................................................. 73 4.8 Common Scripting Examples................................................................................. 74 4.8.1 Create a Project and Apply Constraints........................................................ 74 4.8.2 Check Design File Syntax........................................................................... 75 4.8.3 Create a Project and Synthesize a Netlist Using Netlist Optimizations............... 75 4.8.4 Archive and Restore Projects.....................................................................
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