Intel® Quartus® Prime Pro Edition User Guide Design Recommendations Updated for Intel® Quartus® Prime Design Suite: 19.1 Subscribe UG-20131 | 2019.04.01 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Recommended HDL Coding Styles .................................................................................. 4 1.1. Using Provided HDL Templates................................................................................ 4 1.1.1. Inserting HDL Code from a Provided Template............................................... 4 1.2. Instantiating IP Cores in HDL.................................................................................. 5 1.3. Inferring Multipliers and DSP Functions.....................................................................6 1.3.1. Inferring Multipliers....................................................................................6 1.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions........................... 7 1.4. Inferring Memory Functions from HDL Code ............................................................. 8 1.4.1. Inferring RAM functions from HDL Code........................................................ 9 1.4.2. Inferring ROM Functions from HDL Code..................................................... 26 1.4.3. Inferring Shift Registers in HDL Code..........................................................28 1.5. Register and Latch Coding Guidelines..................................................................... 31 1.5.1. Register Power-Up Values..........................................................................31 1.5.2. Secondary Register Control Signals Such as Clear and Clock Enable................33 1.5.3. Latches ..................................................................................................34 1.6. General Coding Guidelines.................................................................................... 37 1.6.1. Tri-State Signals ..................................................................................... 38 1.6.2. Clock Multiplexing.................................................................................... 38 1.6.3. Adder Trees ............................................................................................40 1.6.4. State Machine HDL Guidelines................................................................... 41 1.6.5. Multiplexer HDL Guidelines ....................................................................... 47 1.6.6. Cyclic Redundancy Check Functions ...........................................................50 1.6.7. Comparator HDL Guidelines.......................................................................52 1.6.8. Counter HDL Guidelines............................................................................ 53 1.7. Designing with Low-Level Primitives....................................................................... 53 1.8. Recommended HDL Coding Styles Revision History...................................................54 2. Recommended Design Practices................................................................................... 57 2.1. Following Synchronous FPGA Design Practices..........................................................57 2.1.1. Implementing Synchronous Designs........................................................... 57 2.1.2. Asynchronous Design Hazards................................................................... 58 2.2. HDL Design Guidelines..........................................................................................59 2.2.1. Considerations for the Intel Hyperflex™ FPGA Architecture............................. 59 2.2.2. Optimizing Combinational Logic................................................................. 59 2.2.3. Optimizing Clocking Schemes.................................................................... 62 2.2.4. Optimizing Physical Implementation and Timing Closure................................67 2.2.5. Optimizing Power Consumption..................................................................70 2.2.6. Managing Design Metastability...................................................................70 2.3. Design Rule Checking with Design Assistant ........................................................... 70 2.3.1. Cross-Probing from Design Assistant.......................................................... 71 2.3.2. Running Design Assistant During Compilation.............................................. 75 2.3.3. Running Design Assistant in Analysis Mode..................................................77 2.3.4. Changing Design Assistant Rule Scope or Number ....................................... 82 2.3.5. Design Assistant Rules..............................................................................82 2.4. Use Clock and Register-Control Architectural Features.............................................119 2.4.1. Use Global Reset Resources..................................................................... 119 2.4.2. Use Global Clock Network Resources.........................................................128 Intel Quartus Prime Pro Edition User Guide: Design Recommendations Send Feedback 2 Contents 2.4.3. Use Clock Region Assignments to Optimize Clock Constraints....................... 129 2.4.4. Avoid Asynchronous Register Control Signals............................................. 131 2.5. Implementing Embedded RAM............................................................................. 131 2.6. Recommended Design Practices Revision History.................................................... 132 3. Managing Metastability with the Intel Quartus Prime Software.................................. 134 3.1. Metastability Analysis in the Intel Quartus Prime Software....................................... 135 3.1.1. Synchronization Register Chains...............................................................135 3.1.2. Identify Synchronizers for Metastability Analysis.........................................136 3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis..............................................................................136 3.2. Metastability and MTBF Reporting.........................................................................137 3.2.1. Metastability Reports.............................................................................. 138 3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation.....................................140 3.3. MTBF Optimization............................................................................................. 140 3.3.1. Synchronization Register Chain Length......................................................141 3.4. Reducing Metastability Effects..............................................................................142 3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer... 142 3.4.2. Force the Identification of Synchronization Registers................................... 142 3.4.3. Set the Synchronizer Data Toggle Rate......................................................143 3.4.4. Optimize Metastability During Fitting.........................................................143 3.4.5. Increase the Length of Synchronizers to Protect and Optimize...................... 143 3.4.6. Increase the Number of Stages Used in Synchronizers................................ 143 3.4.7. Select a Faster Speed Grade Device..........................................................144 3.5. Scripting Support............................................................................................... 144 3.5.1. Identifying Synchronizers for Metastability Analysis.................................... 144 3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation.....................................145 3.5.3. report_metastability and Tcl Command......................................................145 3.5.4. MTBF Optimization................................................................................. 145 3.5.5. Synchronization Register Chain Length......................................................146 3.6. Managing Metastability....................................................................................... 146 3.7. Managing Metastability with the Intel Quartus Prime Software Revision History...........146 A. Intel Quartus Prime Pro Edition User Guides.............................................................. 148 Send Feedback Intel Quartus Prime Pro Edition User Guide: Design Recommendations 3 UG-20131 | 2019.04.01 Send Feedback 1. Recommended HDL Coding Styles This chapter provides Hardware Description Language (HDL) coding style recommendations to ensure optimal synthesis results when targeting Intel FPGA devices. HDL coding styles have a significant effect on the quality of results for programmable logic designs. Synthesis tools optimize HDL code for both logic utilization and performance; however, synthesis tools cannot interpret the intent of your design. Therefore, the most effective optimizations require conformance to recommended coding styles. Note: For style recommendations, options, or HDL attributes specific to your synthesis tool (including other Quartus software products and other EDA tools), refer to the synthesis tool vendor’s documentation. Related Information • Advanced Synthesis Cookbook • Design Examples • Reference Designs 1.1. Using Provided HDL Templates The Intel® Quartus® Prime software provides templates