Open RFIC Design Platform Integrates Highly-Capable Design Tools
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High Frequency Products From March 2006 High Frequency Electronics Copyright © 2006 Summit Technical Media RFIC DESIGN SUITE Open RFIC Design Platform Integrates Highly-Capable Design Tools By Thomas T. Quan Applied Wave Research, Inc. he Analog Office The newest version of this design suite is a RFIC and high-speed ana- Tpowerful design log IC design tool includes system that is specifically advanced features for architected and opti- design accuracy and mized from the ground up user productivity for next-generation ana- log and radio-frequency integrated circuit (RFIC) designs. Much more than a point tool, the Analog Office integrated solution boasts an industry-leading, concur- rent interconnect-driven and RF-aware design methodology that delivers unprecedented Figure 1 · The Analog Office 2006 open ease-of-use, interactivity, and openness. design platform integrates best-in-class High-frequency circuit impairments in tools, including four circuit simulators and today’s complex analog and RFICs, such as five electromagnetic simulators. compression, noise, distortion, and phase noise, as well as the physical parasitics like interconnect impedance, coupling and packag- into existing digital and mixed signal IC ing effects, need complete “RF closure” design flows from Cadence and Synopsys, and between the RFIC’s system and circuit, elec- enables analog and RFIC design engineers to trical and physical, and design and test activ- significantly shorten their development cycles ities before commitment to costly IC imple- and speed wireless products to market. mentation. Analog Office 2006 design platform fea- The Analog Office design system provides tures the second generation of the AWR an new approach that achieves optimum RF Intelligent Net™ (iNet) technology, which design closure through a unified data model powers “on-the-fly” interconnect extraction and design environment encompassing all of through an advanced interconnect-based the design domains. The data model is high- design methodology. In this latest release, frequency aware, permitting accurate extrac- AWR continues its commitment to provide the tion and modeling of all design elements, industry with an easy-to-use, open RF design including active and passive devices, as well platform that is fully integrated with five as interconnects, at high-frequency. The solu- best-in-class electromagnetic (EM) tools, as tion is built on AWR’s open high-frequency well as four circuit simulators (see Figure 1). design platform, enabling easy integration of Analog Office 2006 software offers a proven the most capable tools to capture, synthesize, design flow and validated process design kits simulate, optimize, layout, extract, and verify (PDKs), which enable multiple tape-outs, designs from system to final tape-out. The including several to the Jazz Semiconductor Analog Office design suite is fully integrated silicon germanium (SiGe) process. 26 High Frequency Electronics High Frequency Products RFIC DESIGN SUITE Figure 2 · Analog Office 2006 iNet2 technology fea- tures “on-the-fly” extraction of interconnect parasitics. Figure 3 · iNet2 technology helps model and simulate Feature Descriptions critical nets in this broadband operational amplifier Integral to the Analog Office design suite is an inter- while the layout is in progress. The opamp is designed connect-driven/RF-aware design methodology built in a Jazz SiGe60 process. around AWR’s iNet technology. Similar to a timing-driven or wire-driven digital design methodology, the iNet methodology focuses on accurate RF interconnect model- International. The design can then be simulated with the ing and analysis throughout the entire RFIC design pro- parasitics of selective nets. (e.g., critical signal paths). cess to reduce or eliminate design iterations, shorten the Other systems cannot do partial extraction, requiring the design cycle, and ensure first-time design success. Unlike layout to be completed and fully synchronized with the existing net constructs built on a “digital-centric” data schematic (on a separate data base) via LVS before the model, the Analog Office iNet technology is based on an layout parasitics can be considered. At that point prob- RF-accurate net model with multiple levels of abstrac- lems can be hard to identify because correlation between tion. Models for short-circuit, lumped, resistance-induc- the layout and schematic can be confusing. And when tance-capacitance (RLC), distributed RLCK (including problems are identified, major rework is usually required. coupling inductance), fully-distributed transmission line, Within Analog Office software, the schematic and layout or full 3D EM elements use a single environment and are in one database, and thus are always in sync, main- data model. iNet technology provides concurrent and real- taining constant “connectivity-on-the-fly.” Critical nets time physical modeling of RF interconnects while the lay- can be routed, modeled, and refined concurrently with the out is in progress, eliminating the need for a serial post- electrical design process. In this concurrent process, layout connectivity extraction step. Simulation and anal- designers can more easily adjust the design or layout to ysis can be invoked immediately to verify the perfor- correct any problems as they go. The full layout can then mance of the design as soon as the critical nets are laid be completed (or a partially finished layout handed off to out, without waiting for the rest of the circuit to be com- a layout specialist for completion), with assurance that pleted (see Figure 2). major rework will not be necessary (see Figure 3). iNet2, the second-generation of this iNet technology, and its associated data model have been dramatically Higher Capacity, Faster Layout Capabilities improved to deal with more complex, higher density RF Analog Office design suite provides IC designers with layouts. Nets can now be created in segments which are a complete physical design system to fully implement then connected in a hierarchical fashion. This greatly their analog and RF IC designs within a single environ- simplifies the routing of the power supply and ground ment, eliminating the need for switching between multi- interconnects. Net creation and modification has been ple environments and databases. made much more flexible. Switching layers is effortless The package offers a completely interactive custom and via connections are automatically sized and inserted layout tool with integrated device-level, placement, and between metal layers and on device pins. Even if the lay- routing features to speed up the creation of analog and out is not completed, at any time during layout creation, RF circuit blocks and chips. An integrated design rule the user can extract all or part of the implemented inter- check (DRC) capability and interface to industry’s leading connect using NET-AN, the very accurate, embedded RLC DRC tools ensure the physical layout being created and coupled C/L 3D multi-net net extractor from OEA always meets the process design rules, resulting in a cor- 28 High Frequency Electronics High Frequency Products RFIC DESIGN SUITE Figure 4 · A 3D view of the opamp layout in 0.13 µm RF Figure 5 · A detailed 3D view of a 5.8 GHz voltage- CMOS process. allowing visualization of the layers. controlled oscillator designed in Analog Office 2006 reveals a complex interconnect structure and device layout in the Jazz SiGe60 process. rect-by-design, error-free layout. The layout editor is directly connected to the EM socket, providing on-the-fly EM extraction and modeling of arbitrary layout struc- connectivity can be associated with different nets. This tures and complex spiral inductors. At every step during feature is extremely useful when routing differential nets the physical design process, the iNet technology continu- or “electrically-equivalent” nets, very common in analog ously updates in real time the underlying interconnect and RFIC layout, where certain nets have to be matched data model, and after each interconnect is “implemented” electrically. or laid out, concurrent simulation and analysis can be A new double buffering feature provides a fully ren- immediately invoked on the schematic or layout to verify dered and dynamically displayed graphic view of the edit- the performance of the overall design without waiting for ed layout objects, speeding up editing tasks. An updated the final layout of the whole design to be completed (see layout configuration dialog enables the user to easily Figure 4). switch layout viewing and editing configurations, and a The Analog Office 2006 release features dramatic new layer dialog box simplifies the task of setting up lay- improvement in layout editing capacity and performance. ers, turning them on and off, and hiding certain layers. Speed in common layout operations, such as opening The pin data model in layout cells now adopts the designs, redrawing, and general editing, have been accel- OpenAccess pin data model, offering more flexible con- erated up to 100 times over the previous version. Physical nectivity within the cell and between the cell pins and layouts of hundreds of thousands of devices can be opened external nets. Routes can now go through cells. In addi- and viewed in a matter of seconds rather than minutes. tion, ports in the design can now have artwork cells asso- iNet2 technology now powers the manual routing of ciated with them, providing more flexibility in layout. interconnects in a manner that is faster and more natu- Along with feature enhancements and improvements ral to IC designers. An iNet is a collection of wire seg- in speed and capacity, the Analog Office layout editor now ments connecting device and port pins. As the net is rout- features full color editing animation and is rendered ed, connected pins are highlighted to assist the routing using the industry-standard OpenGL, which utilizes task. When a net is routed over a pin, a connection is high-performance 3G graphics acceleration hardware automatically created and proper contacts or vias are found in most modern design workstations and high-end inserted to complete the connection.