Cadence First Encounter Exploration and Prototyping A flexible, signoff-driven environment for fast implementation of giga-scale

Cadence® First Encounter® Design Exploration and Prototyping offers a comprehensive flat and hierarchical design planning, analysis, and debug environment for complex designs. Its GigaFlex technology adapts to growing capacity requirements while still retaining the relevant timing, placement, and congestion information to accurately plan and implement 100M+ instance designs. The latest advanced node and low-power capabilities make hierarchical implementation of high-speed and advanced node designs faster and easier, and produce designs that consume lower power. In addition, with unique partitioning and budgeting capabilities, First Encounter technology ensures convergence and provides a predictable path to design closure.

First Encounter Technology Benefits • Provides a unified flow for partitioning, pin assignment, macro Accommodating today’s chip design Predictability and convergence placement, feed-through insertion, requirements within narrow market • Enables early design exploration and pipeline registers, clock planning, windows has led to a predictability accurate chip feasibility analysis and time budgeting crisis. How can engineers determine design feasibility for larger, higher- • Performs automated floorplan • Delivers intuitive and visual global performance, power-hungry chips synthesis and ranking for a flexible, timing, power, and clock debug and with an incomplete netlist, library, and predictable path to design closure diagnostics features constraints? And how can they quickly Ease of use assess floorplans for congestion, Productivity and faster time timing, and power without having to to market • Integrates design flows and go into real implementation? • FlexModels and FlexILM abstraction common engines from the front-end, implementation, and First Encounter technology addresses technology adapts to the flow, packaging domains these challenges and more. It spans providing the right mix of capacity silicon virtual prototyping, automatic and accuracy, enabling to • Delivers a ready-to-use prototyping floorplanning, physical synthesis, achieve up to 20x improvements in foundation flow with design hierarchical controls for partitioning capacity and turnaround time exploration to get to an implemen- and budgeting, legal macro and • Partition-in-partition technology tation-ready floorplan standard cell placement, complete natively manages multi- Product differentiation and power-grid design and optimization, hierarchical designs and hierarchical clock synthesis for lower cost • Supports hierarchical methodologies high-performance, complex 100M+ • Supports concurrent chip/package such as bottom-up block-based instance designs. With such compre- design and optimization hensive capabilities, First Encounter flows, top-down black-box flows, technology helps customers meet their and hybrid flows for 100M+ • Supports integrated automatic area time-to-market requirements confi- instance designs and peripheral I/O placement and dently, and with significant perfor- optimization mance and productivity gains. • Supports flip-chip RDL routing capabilities Cadence First Encounter Design Exploration and Prototyping

Features

Early design exploration

Today’s physical design teams start physical implementation and design planning very early in the design cycle— with multiple versions of the design netlist—to determine design feasibility. Plan Rank Among their questions: Can the design be implemented in the required area? Can the design operate at the desired speed? Does it meet power requirements?

First Encounter technology addresses all of these issues and more:

• Production-proven automated floorplan Figure 1: Floorplan synthesis and ranking using multi-CPU floorplanning synthesis closes the gap between • Hierarchical support helps physical and implementation by designers assess how best to partition enabling timing-, power-, area-, and Silicon virtual prototyping and the logical hierarchy into physical congestion-aware placement coupled hierarchical capabilities modules by analyzing the optimal with fast global routing and in-place pin assignments; enabling quick time optimization First Encounter technology supports all implementation styles—from flat budgeting; accurately predicting the • Concurrent standard cell and macro or hierarchical to single or multi-VDD. clock distribution networks; analyzing placement helps designers generate Capabilities for fast power-grid design the power grids; and eventually implementation-quality floorplans for and optimization, global routing, generating complete timing and both flat and hierarchical designs in-place optimization, and global timing physical constraints for each of the physical modules • Built-in flexibility and editing debug provide a robust infrastructure to implement any methodology. capabilities such as Relative Floorplan Fast and easy debug and analysis (specifying relationships for pre-routes, • Full-chip flat prototyping delivers The ability to debug and diagnose inter- resizable objects, multiple relations, complete physical, timing, clock, and dependent design closure issues is critical. datapath stacking, and integrated power data, thereby eliminating the The challenges often come late in the analysis tools) and Resize Floorplan guesswork associated with traditional design cycle, along the critical path to enable you to quickly and accurately block-based approaches final tapeout. First Encounter capabilities reach an optimal final floorplan for timing, power, and clock debug and • The floorplan ranking system automat- diagnostics enable you to quickly pinpoint ically generates multiple floorplan and visualize interdependent timing, scenarios in parallel and analyzes them based on pre-defined quality-of-results criteria; you can explore as much of the physical solution as possible and Cadence InCyte Chip Estimator make the most informed tradeoffs for Estimation, Architectural and Low-Power Planning design feasibility

• GigaFlex abstraction modeling Estimation Results Project Tracking Golden Design enables very early and fast design • Architectural floorplan • Implementation results Final results planning for giga-scale designs; it • Verilog Structure • ECO results (Derivative design allows netlist compression up to 90% • Constraints (SDC) (Track progress through what-if analysis Q409) • Power plan (CPF) implementation Q409) while maintaining relevant timing and • IP data (IP-XACT) congestion information, resulting in • Scripts faster turnaround time and one-pass implementation handoff Encounter Digital Implementation System To bring physical predictability into your Synthesis, Prototyping, Floorplaning, P&R, Verification, Signoff estimations, you can link into the First

Encounter environment from the Cadence Figure 2: Fast and accurate chip estimation results drive implementation Chip Planning System.

www.cadence.com 2 Cadence First Encounter Design Exploration and Prototyping

Global Timing Debug Global Clock Debug Global Power Debug Platforms

• Failed path/constraint • Instance and path finding • Only complete power • lnx86: Linux (x86 and x86_64) checking and optimization • Cross-probing with physical debug system available 32/64-bit • Detailed path analysis • Tracing in schematic view • Diagnose top power • Cross-probing with consuming nets, power • sol86: Solaris (x86_64) 64-bit • Visually check/debug clock consumption by hierarchy, physical view specifications – reconverge domain, instance, clocks… • sun4v: Solaris (ultraSparc) 64-bit • Expand/collapse clks for • What-if analysis and opt hierarchical viewing • Uses signoff engines • ibmrs: AIX (power) 64-bit

Cadence Services and Support

• Cadence application engineers can answer your technical questions by telephone, email, or Internet—they can also provide technical assistance and custom training Figure 3: Comprehensive schematic debug environment • Cadence certified instructors teach clock, and power issues, and then quickly Concurrent chip/package design and more than 70 courses and bring resolve them using powerful “what-if” flip-chip support their real-world experience into the analysis techniques. You can implement First Encounter flip-chip floorplanning classroom the results immediately in the physical technology enables the concurrent design. • More than 25 Internet Learning design of chip and package by including Series (iLS) online courses allow you Low-power design package constraints and parasitic effects the flexibility of training at your own while designing the IC. With support for Advanced low-power design techniques computer via the Internet multiple I/O methodologies, concurrent such as power gating (MTCMOS) and optimization of I/O and core instances, • Cadence Online Support gives you dynamic voltage and frequency scaling automatic RDL routing (including 24x7 online access to a knowledge (DVFS) use multiple power domains. 45-degree support), and accounting for base of the latest solutions, technical The underlying First Encounter infra- RDL routing during signal/power routing, documentation, software downloads, structure facilitates the implementation First Encounter flip-chip technology elimi- and more of low-power designs because it compre- nates the manual steps in I/O placement hends multiple power domain structures and optimization. This mature technology across the flow. This capability enables has been proven through multiple automatic placement of level shifters, customer tapeouts. with all power connections completed automatically. First Encounter technology also supports Common Power Format (CPF) and IEEE 1801 to specify advanced power-reduction techniques, from design and verification through final implemen- tation and signoff.

Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com

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