Digital Integrated Circuits Design Flow

Victor Grimblatt R&D Group Director August 2013

• Introduction • CMOS Technology • ASIC Design Flow • Best Practices

1943 1946 1947 1949 “I think there is Early electronic First transistor “Computers in a world market computers used developed at the future may for maybe five glass valves Bell Labs weigh no more computers.” (vacuum tubes) than 1.5 tons.”

1954 1958 1971 1975 First fully First Integrated First Micro- “Chip transistorized Circuit (IC) processor complexity will computer double every 1.5 years” 1977 1983 1998 2002 “There is no Apple Pentium II Pentium 4 reason anyone Introduces the “Our customers would want a first “user- need to be 10X computer in friendly” more productive their home.” computer every 6 years.”

How can you put 100 million switchesMake them on reallya chip small! the size of your fingernail?

steps

Grow a giant crystal of sand (silicon)

Slice it up into round wafers & polish them

Coat a wafer with a photographic chemical that hardens when exposed to light

Make a stencil for a pattern to embed in the silicon

Shrink the stencil and shine a light through it

Dip the wafer in acid to etch away the soft parts

Repeat steps 3 - 6 many times, producing layers of patterns etched into the wafer

(cool term: Photolithography)

Cut up the wafer into many square chips

Glue the chip into a protective package

Connect the chip to the pins of the package with tiny gold wires

Put the chip on a tester machine and run a test

Throw away the chips that fail the test!

Assemble different kinds of chips onto a board

Install the board into a phone, computer...

Digital Circuit Implementation Approaches

Custom Semicustom

Cell - based Array - based

Standar Cells Macro Cells Pre - diffused Pre - wired Compiled cells (Gate Arrays) (FPGA)

Intel 4004

Courtesy Intel

Intel 4004 (‘71) Intel 8080 Intel 8085

Intel 8286 Intel 8486 Courtesy Intel

• ASIC (Application Specific Integrated Circuit) • General Purpose Integrated Circuits

• A chip designed to perform a particular operation • Generally not software programmable to perform different tasks • Often has an embedded CPU • May be implemented in FPGA

• Video processor to decode or encode MPEG-2 digital TV signals • Encryption processor for security • Many examples of graphical chips • Network processor for managing packets, traffic flow, etc.

• Every cell and transistor is designed by hand from scratch • Only way to design analog portions of ASICs • Highest performance but longest design time • Full set of masks required for fabrication

• Designer uses predesigned logic cells (e.g. AND, NAND) • Designers save time, money, and reduce risk • Standards cells can be optimized individually • Standard cells library is designed using full custom • Some standar cells, such as RAM and ROM, and some datapath cells (e.g. multiplier) are tiled together to create macrocells

• Transistors are predefined in the silicon wafer • Predefined pattern of transistors is called “base array” • Smallest element is called “base cell” • Base cell layout is the same for each logic cell • Only interconnection between cells and inside the cell is customized • Slower than cell based designs but implementation time is faster (less time in factory)

• Complementary Metal Oxide Semiconductor • Consists of NMOS and PMOS transistors • MOS (Metal Oxide Semiconductor) Field Effect transistor

• Basic element in the design • Voltage controlled device • It is formed by layers – Semiconductor layer – Silicon dioxide layer – Metal layer • Consists in three regions – Source – Drain – Gate

• Source and drain are quite similar • Source is the node which acts as the source of charge carriers • Charge carriers leave the source and travel to the drain • Source is the more negative terminal in N channel MOS, it is the more positive terminal in P channel MOS • Area under the gate is called the “channel”

• Needs some kind of voltage initially for the channel to form • When the channel is not yet formed, the transistor is in the “cut off region” • Threshold Voltage: voltage at which the transistor stars conducting (channel begin to form) • Transistor in “linear region” at threshold voltage • When no more charge carriers go from the source to the drain, the transistor is into the “saturation region”

• Made up of both NMOS and CMOS transistors • CMOS logic devices are the most common devices used today in IC design – High density – Low power – High operating clock speed – Ease of implementation at the transistor level • Only one driver but gates can drive as many gates as possible • Gates output always drives another CMOS gate input

• Requires one PMOS and one NMOS transistors • NMOS provides the switch connection to ground when the input is logic high  Output load is discharged and output is driven to logic “0” • PMOS transistor provides the connection to power

supply (VDD) when the input is logic low  Output load is charged and output is driven to logic “1”

• “Holes” are the charge carriers for PMOS transistors • Electrons are the charge carriers for NMOS transistors • Mobility of electrons is 2 times than that of “holes” • Output rise and fall time is different between PMOS and NMOS transistors • To adjust time PMOS W/L ratio is about twice NMOS W/L ratio

• L is always constant in a standard cell library • W changes to have different drive strengths • Resistance is proportional to L/W  increasing the width decreases resistance

• Big percentage is due to the charging and discharging of capacitors • Low power design are techniques used to reduce power dissipation

• Dynamic Switching Power: Due to charge and discharge of capacitances – Low to high output transition draws energy from the power supply – High to low transition dissipates energy stored in CMOS transistor 2 – Total power drawn = load capacitance*VDD *f • Short Circuit Current: Occurs when the rise/fall time at the input of the gate is larger than the output rise/fall time

• Leakage Current Power: Caused by 2 reasons – Reverse-Bias diode leakage on transistor drains. It happens when one transistor is off, and the active one charges up/down the drain using the bulk potential of the other transistor – Sub-Threshold leakage through the channel to an “OFF” transistor/device

• Consists of a PMOS transistor connected in parallel to a NMOS transistor • Transmits the value at the input to the output • PMOS transmits a strong 1 • NMOS transmits a strong 0 • Advantages – Better characteristics than a switch – Resistance of the circuit is reduced (transistors in parallel)

• Stores a logic value by having a feedback loop • There are two types – Latches – Flip Flops

• Asynchronous element • When G is high, transmission gate is switched on and input D passes to the output • When G is low, transmission gate is off an inverters hold the value

D Q

• Synchronous element • FFs are constructed with 2 latches in series • First latch is called Master, the second one is called Slave • Inverted clock is fed to the slave latch transmission gate

• Speed • Area • Power • Time to market

Today’s chips have hundreds of thousands of gates

Designing a chip is the task of EDA=Electronicfiguring out how to Design make the Automation chip do what you want it to do

Without automation, this task would be impossible

Blah blah blah yadaBlah yada blah blah Blah blahyada blah yada yidie yadieBlah blah blah Blah blahyada blah yada So on andyidie so yadieforth on andBlah on blah blah So on andyidie so yadieforth Jibber jabberon and jibber on just jawingSo on and so forth Jibber jabberon and jibber on …the steps you take to design a chip! Yackety yack Specification just jawing Ya'll comJibber back jabber jibber Yacketyjust yack jawing System Ya'll com back Yackety yack Ya'll com back Technology Analysis Module Compiler Process System Studio Select Saber Architecture Scripts

TestbenchBlah blah blah InitialBlah blah blah constraints yadaBlah yada blah blah yadaBlah yada blah blah Blah blahyada blah yada Blah blahyada blah yada yidie yadieBlah blah blah yidie yadieBlah blah blah VERA Blah blahyada blah yada Blah blahyada blah yada So on andyidie so yadieforth So on andyidie so yadieforth on andBlah on blah blah on andBlah on blah blah So on andyidie so yadieforth So on andyidie so yadieforth Jibber jabberon and jibber on Jibber jabberon and jibber on Library Compiler just jawingSo on and so forth just jawingSo on and so forth Jibber jabberon and jibber on Jibber jabberon and jibber on Yackety yack Yackety yack Jibberjust jawing jabber jibber Jibberjust jawing jabber jibber Ya'll comYackety back yack RTL Ya'll comYackety back yack just jawing Gates just jawing Models / IP DesignWare IP Ya'll comYackety back yack Ya'll comYackety back yack Ya'll com back Ya'll com back

Design Compiler RTL Verification Power Compiler Synthesis VCS-MX DFT Compiler Links-to- JupiterXT Design Planning Layout VCS-MX Magellan Design Formality Gate-level ATPG Constraints PrimeTime netlist PrimePower TetraMAX Gate-level verification IC Compiler Physical Compiler Mask Writer Post-Route Astro Place & Route CATS Verification Blah blah blah yadaBlah yada blah blah Blah blah blah Proteus yadaBlah yada blah blah yidieBlah yadie blah blah So on and soyada forth yada PrimeTime yidieBlah yadie blah blah Soon onand and on so forth Jibber jabberyidie jibber yadie Soon onand and on so forth Physical Design Physical Data Jibberjust jawing jabber jibber STAR-RCXT Yackety yackon and on NanoSim Jibberjust jawing jabber jibber GDSII Ya'll com back Yacketyjust yack jawing Creation Ya'll comYackety back yack HSPICE Hercules Checks Ya'll com back

© Synopsys 2013 54 Blah blah blah yadaBlah yada blah blah Blah blah blah yadaBlah yada blah blah yidieBlah yadie blah blah So on and soyada forth yada yidieBlah yadie blah blah Soon onand and on so forth Jibber jabberyidie jibber yadie Soon onand and on so forth Jibberjust jawing jabber jibber Yackety yackon and on Specification just jawing Ya'll comJibber back jabber jibber Yacketyjust yack jawing System Ya'll com back DesignYackety yack Implementation: Ya'll com back Technology Analysis Module Compiler Process System Studio Select Saber ArchitectureLogical Scripts

Design Compiler RTL Verification Power Compiler Synthesis VCS-MX DFT Compiler Verification Links-to- JupiterXT Design Planning Layout VCS-MX Magellan Design Formality Gate-level ATPG Constraints PrimeTime netlist PrimePower TetraMAX Gate-level verification IC Compiler Design Implementation:Physical Compiler Mask Writer Post-Route Astro Place & Route CATS Verification Blah blah blah yadaBlah yada blah blah Physical Blah blahyada blah yada Proteus Blah blah blah yidieBlah yadie blah blah So on and soyada forth yada PrimeTime yidieBlah yadie blah blah Soon onand and on so forth Jibber jabberyidie jibber yadie Soon onand and on so forth Physical Design Physical Data Jibberjust jawing jabber jibber STAR-RCXT Yackety yackon and on NanoSim Jibberjust jawing jabber jibber GDSII Ya'll com back Yacketyjust yack jawing Creation Ya'll comYackety back yack HSPICE Hercules DesignChecks for Manufacturing Ya'll com back

• A collection of EDA tools that work together well • Not to be confused with a compute platform or platform-based design! Confirma, DesignWare Innovator, Systems Synplify DSP System-Level Libraries Saber, System Studio

Synplicity Galaxy DesignWare Discovery

Design Custom Synplify DesignWare VCS Premier Compiler Designer SE Cores IC Custom

Synplify VMM Identify Compiler Designer LE DesignWare HSPICE CustomSim Pro ICPrimeTime Validator / Star-RCXT Libraries

Proteus Manufacturing Sentaurus CATS

Transaction-Level Prototyping & Systems DSP Synthesis Models Validation

FPGA Implementation Implementation IP Verification

Verification Physical RTL Schematic RTL

Cores Synthesis Synthesis Editor Verification Place & Layout

Logic Signoff Route Editor Libraries FastSPICE

Synthesis Methodology Circuit Simulation Circuit RTL Source Debug Source RTL Physical Verification & Extraction

Optical Proximity Correction Manufacturing DFM TCAD Mask Data Prep

Idea

Physical implementation Specification

GDSII

RTL

Chip Gate level netlist

1. “Spec” your chip Design 2. Generate the gates Implementation: Logic 3. Make the chip testable

4. Ensure the gates will work Verification

5. Layout your chip Design Implementation: 6. Double-check your layout Physical Design for Manufacturing 7. Turn your design into silicon

• Describe what you want your chip to do • Write a “spec” - use a language like SystemVerilog or VHDL

A spec for a cell phone ringer might look like this:

if incoming_call AND line_is_available then RING;

Today’s complex chip designs can have a million lines of specification created by a team of 100 people working for 6 months

• You can buy a ready-made spec – example: DesignWare Library • Give the spec to the computer to begin automation – example: (V)HDL Compiler

• Goals and constraints of the design • Functionality (what the chip will do) • Performance (e.g speed and power) • Technology constraints (e.g. size and space) • Fabrication technology

• Decide the circuit architecture (structure) – RISC/CISC – ALU – Pipelining – Etc. • Breaks the system into several sub systems • Functionality of sub systems should match the specification • Sub systems need to be implemented through logic representation (boolean expressions), FSM, combinational logic, sequential logic, schematics, etc.  Logic Design

• Describes the several sub systems • Should match the functional description • Verilog or VHDL (Hardware description Language – HDL) • HDlL: Language used to describe a digital system • Verification is performed at this stage to ensure that RTL matches the idea

• Figure out the detailed logic gates • Use a computer program (EDA tool) • Synthesis - example: Design Compiler, Physical Compiler, IC Compiler • Save the logic gates to use in a future design - example: DesignWare Library

• Help the manufacturer to find defects on the chip • Add special gates that send information out of the chip • Use EDA tools! Test Synthesis - example: DFT Compiler, DFT MAX

• Generated from the conversion of RTL into an optimized gate level netlist • Done by synthesis tools • Synthesis tool takes an RTL description and a standard cell library and produces a gate level netlist • Considers constraints such as timing, area, testability, and power • The result is a completely structural description with only standard cells at the leaves of the design • This level is also verified by simulation or formal verification

Verify that the logic gates will do what you want, when you want them to, with EDA tools – Simulation, Timing Analysis, Testbench Generation

- example: VCS-MX, PrimeTime, VERA 0 1 0 1 1

Put statements in the design description – Assertion-based verification = “Smart Verification” Assertion assert property (@(posedge clk) $rose(req)|-> ##[1:3] $rose(ack));

always @(posedge req) begin 0 1 2 3 4 5 repeat (1) @(posedge clk); fork: pos_pos req begin @(posedge ack) $display("Assertion Success",$time); disable pos_pos; ack end Intended behavior begin repeat (2) @(posedge clk); $display("Assertion Failure",$time); Old way disable pos_pos; end join end // always

• Create a test program • For manufacturer to throw out defective chips • Need millions of combinations of electrical stimuli • Use EDA tools! Automatic Test Program Generation – example: TetraMAX

apply electricity measure response

+ +

expected response check against expectations

• Tweak the whole thing to make it better – Faster (speed), smaller (area), less battery (power) – Use EDA tools! Optimization - example: Design Compiler, Power Compiler, Physical Compiler

Make sure it’s still the same design - Formal Verification

- example: Formality

• Gate level netlist is converted into geometeric representation • It corresponds to the layout of the design • Layout is designed according to design rules specified in the library • Consists in three sub steps – Floor planning – Placement – Routing • Produces a GDSII file

• Design planning: create a “floorplan” so the gates will go where you want • Place the gates on a “blueprint” and route them together (also called “layout ”) • Show where the gates will be connected with wires

Floorplan

- example: Jupiter-XT, Physical Compiler, IC Compiler, Astro

• Length of the connecting wires will change how fast the chip will run • Simulate it again - Post-route (post-layout) verification – example: VCS-MX, NanoSim, HSPICE

• Make sure “what you see is what you get” – Compare what you designed to what’s in your layout – Layout versus Schematic (LVS) • Follow the manufacturer’s rules • Perform Design Rule Checks (DRC)

- example: Star-RCXT, Hercules

• File used by the foundry to fabricate the ASIC • Physical verification is performed to verify if the layout is designed according the rules

• Produce the layout data: GDSII - example: IC Compiler

STRNAME EXAMPLE 02000200 60000201 1C000300 02000600 ...... `.... 000000 BOUNDARY 01000E00 02000200 60002500 01000E00 .....%.`...... 000010 LAYER 42494C45 4C504D41 58450602 12002500 .%....EXAMPLELIB 000020 1 413E0503 14000300 02220600 59524152 RARY.."...... >A 000030 DATATYPE 1C00545A 9BA02FB8 4439EFA7 C64B3789 .7K...9D./..ZT.. 00004 0 60000000 01000E00 02000200 60000205 ...`...... ` 000050 FilesXY are usually58450606 20 0C001100 to 3001000E00 gigabytes 02000200 ...... EX 000060in size,-10000 but after you0100020D correct 06000008 04000045 the 4C504D41 image, AMPLE...... 000070the 10000 OR, 0000F0D8 FFFF0310 2C000000 020E0600 ...... ,...... 000080 size20000 can reach FFFF204Ea 150 00001027 gigabytes 0000204E 00001027 '...N - ..'...Nthat’s .. 000090 10000 0000F0D8 FFFFF0D8 FFFFF0D8 FFFFF0D8 ...... 0000A0 15020000 billion bytes00000004 or 04000007 over 04000011 a trillion04001027 '...... bits! 0000B0 -10000 00000000 00000000 00000000 00000000 ...... 0000C0 -10000 -10000 -10000 10000 ENDEL ENDSTR

Correct the image – example: Proteus, Progen, IC Workbench, SiVL/LRC, iN- Phase, CATS

10 Above Wavelength SubWavelength

3.0mm 2.0mm

1.0mm 1.0 0.6mm 436nm 365nm 248nm 0.35mm 193nm 0.25mm 157nm 0.18mm 0.1 0.13mm Silicon Feature Size 90nm 65nm Lithography Wavelength 45nm

1980 1985 1990 1995 2000 2005 2010

250nm 180nm 90nm and Below

Design OPC PSM

Mask 0° 180° 0° OPC 180°

Wafer

OPC = Optical Proximity Correction PSM = Phase Shift Mask

Take a deep breath and “sign off”! Your semiconductor vendor will: . Rerun your design . Generate a database for manufacturing . Perform photolithography . Put your chip into a package . Run your test program . Deliver your finished chips

Put the chips together on a board and into your phone, computer… Better yet, have someone else do it for you Now you’re ready to go to market!

Layout engineers CAD engineers Semiconductor manufacturers who are the players?

#1 Libraries #6 Methodology Know Your Attributes One or Two Flows

#2 Setup #7 Optimization Correlation and Runtime Adjust Accordingly

#3 Scripts #8 Signoff Impacts Your Design Review Your Environment

#4 Constraints #9 Performance Watch Your Constraints Leverage Your EDA Partner

#5 Analyze #10 Low Power Analyze-Fix-Proceed Architecture Drives Power

Why is my design larger in area? Why is it taking so long to run?

After Optimization

Original Area New Area Watch for dont_use, dont_touch, and size_only usage in your libraries and scripts

• Attributes are user-controlled to guide optimization • Restricting optimization may lead to problems

• A properly designed set of library Example: Cell Sensitivity To Load Uncertainty cells give optimization engines more choice – Avoid cells sensitive to minor change Cell A

in load, impedes convergence Delay – Footprint-equivalent cells are useful for final-stage optimization w/ minimal Cell B perturbation to other design metrics D B – Std. cell pins should be on grid - * (especially complex cells with small A drive strength: higher pin density) – Multiple variants for each flop (drive strengths, delays, setup times, .. )

Cload • Library quality enabler for targeted C* performance

Netlist v1.0 Netlist v1.1 SDC v1.0 SDC v1.1 What happened??? • Compile • Compile • 3.2M • 6.8M instances instances??

• Found issues after days of engineering work • Size_only on 3.7M cells • SDC with all cells set with set_disable_clock_gating on

DC Utility • Detect design issues and dirty constraints styles that can lead to Checker bad runtime/memory and QoR

ICC Utility • Detect readiness of physical design before going into various Checker implementation stages

PT Utility • Detects application variables, settings and design issues causing Checker runtime or memory increase

When someone tells you “Tool A” is X times faster than “Tool B”

Incomplete Complete Need to put things in perspective … • First Step: review your script – How was the script migrated to “Tool A”? – Did you also update the script to leverage the latest technologies? • Early stage of your design, think fast mode • Final stage of your design, think QoR

• Today’s design requires completeness • Synopsys tools are tailored for performance, but they also have a mode to run fast

• Recommendations – The typical complaint is long runtime, choose your goal setting accordingly – Make sure your script is up to date for your end goal and to take advantage of the latest features

Symptoms of over-constraining: long runtime, excessive buffering and huge violations

• Over-constraining could guide the Original Clock period tool to focus on artificial critical paths

• Over-constraining happens with • Unrealistic input and/or output Input Delay Output Delay delays Time Available • Tightening the clock period for logic • Specifying large clock uncertainty

Synopsys tools are designed to work towards meeting design goals… but don’t expect miracles!

CLKA wns = -0.300 CLKA wns = -0.280 CLKB wns = -0.100 CLKB wns = -0.150

Circuit A Circuit B

Cost = ∑ pi * wi Default Weights Delay Cost Before Delay Cost After Total cost increased CLKA weight = 1 0.30 0.28 Transformation rejected CLKB weight = 1 0.10 0.15 Total WNS Cost 0.40 < 0.43 Worst WNS = -0.300

Adjusted Weights Delay Cost Before Delay Cost After Total cost reduced CLKA weight = 10 3.00 2.80 Transformation accepted CLKB weight = 1 0.10 0.15 Total WNS Cost 3.10 > 2.95 Worst WNS = -0.280 √

Push Button Flow does not exists Know your circuit to guide the tool

compile_ultra -spg DC Graphical insert_dft compile_ultra –spg -incr

place_opt -spg clock_opt IC Compiler route_opt signoff_opt

Analyze results between Signoff extraction StarRC design PrimeTimeSI Signoff STA stages

Design specifications and constraints changes constantly during the design cycle

Implementation One flow Exploration flow flow for both target for for final exploration & early specs design Implementation & constraints realization

180 nanometers (2000) 45 nanometers (2010) 2 225K gates, 11 RAMs 96mm , ~ 300M transistors 150 MHz 7-9W

DC Explorer • Early RTL Exploration Exploration Implementation – Accelerates Design Schedules

RTL Design Compiler • Look-ahead & Physical Guidance – Creates a better starting point RTL RTL Exploration Synthesis IC Compiler

• Design Exploration Design Design – Creates initial floorplan Exploration Planning • Block Feasibility – Determines physical feasibility Block Block Feasibility Implementation Galaxy Constraint Analyzer • Continuous improvement Physical

Adjust your constraints to model effects of downstream design steps

An Illustration

Design Compiler

• Account for clock trees • No hold-timing fixing • Be careful with critical range • Do not over-constrain

• Synthesis and placement Timing Closure Profile – Do not over-constrain during 1,100 synthesis 1,050 1029

– Use DC SPG flow 1,000 Timing Closure 971 – Account for max_transition and clock 950 uncertainty MHz 900 Profile 913 – Specify pre-CTS estimated 850 constraints 800 Do Not over Synthesis Place Clock Route • CTS Complicate your flow – Remove pre-CTS estimated Addnl. Customization For High-Performance constraints Tuned For Hi-Performance/Low Power

RM (Baseline) • Route – Remove/adjust pre-route constraints – Adjust crosstalk thresholds

Runtime (CPU Hrs) Memory Usage (GB) 172 GB 60 128

50 112 96 40 80 30 64

20 48 32 10 16 0 0 1.1 1.2 5.5 37.0 50+ 1.1 1.2 5.5 37.0 50+ Instances (Million) Instances (Million) Designs run at customer site using revised PrimeTime scripts and latest release version

• Environment and setup – Use latest release and ensure adequate hardware resources

• Reading parasitics – Use binary parasitics when possible

• Multiple timing updates – Eliminate redundant/legacy update_timing steps PrimeTime Design Utility Checker • Inefficient TCL scripting and can help with some of these tasks reporting

• Starting Point • Reduce time-to-results – Built on Synopsys RM – Automated methodology to – Understand the new achieve 90% of target quickly technologies and features – Additional advanced – Easy to use techniques to reach final goal – Minimize number of iterations or “trial and errors” – Reduce ECO efforts

Synthesis P&R Iterations Signoff + ECO

Typical Flow

HSLP Flow Design Schedule

High Performance, Low Power (HSLP) Flow Requires Customization

Typical Flow on Typical Flow on Regular designs High Performance designs Targets

100% 90% Typical Flow

75%

With HSLP HSLP Flow Implementation Best Practices

Design-specific Reduces time-to-results customization

Time

L IN IN OUT RR OUT S OUT IN ISO AO EN Gate Gate Gate VSS VSS VSS VSS Power Level Isolation Retention Always- DESIGN TECHNIQUES Switches Shifters Cells Registers on Logic (MTCMOS)

0.9V Multiple Voltage (MV) Domains  0.7V 0.9V

OFF Multi-Supply with

0.9V shutdown No State Retention   0.9V 0.9V

OFF

0.9V Multi-Voltage with shutdown    0.7V 0.9V

OFF Multi-voltage with SR 0.9V shutdown & State      Retention 0.7V 0.9V