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Lecture 4 © 2008 A EE382V: Embedded System Design and Modeling Lecture 4 – System Design Flow and Methodology Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin [email protected] Lecture 4: Outline • SpecC system design methodology • From specification to implementation – Specification – System design – Processor design • Models and transformations – Specification model – Computation model – Communication model – Implementation model EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 2 System Design µProcessor Control Pipeline IF FSM IP Netlist IP Memory RAM Comp. State PC Interface Interface IR Bus Control Datapath IF FSM Memory Interface Interface Mem RF Processors Registers State State IPs ALUs/FUs Memories Memory Memories ALU Busses Gates Custom HW Specification System architecture Processor Implementation + constraints + estimates + results • Specification to architecture to implementation • Behavior to structure 1. System level: system specification to system architecture 2. Processor level: component behavior to component microarchitecture EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 3 System Design Needs • Design models • Representation for validation and analysis • Specification for further implementation/synthesis • Design languages • Specification down to implementation – Models of Computation (MoC) • System-level design languages (SLDL) – C-based, event-driven SLDLs [SpecC, SystemC] Well-defined, rigorous system-level semantics Unambiguous, explicit abstractions, models – Objects and composition rules Systematic flow from specification to implementation – Transformations and refinements Modeling flow Design automation for synthesis and verification EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 4 Flow System Design Process • Abstraction based on level of detail (structure/timing) • Computation and communication System design flow Path from model A to model F Cycle- timed D F A. System specification model B. Component model C. Bus-arbitration model Approximate- C E D. Bus-functional model timed E. Cycle-accurate computation model F. RTL/ISS Implementation model Communication Un- timed A B Un- Approximate- Cycle- Computation timed timed timed Source: Lukai Cai, D. Gajski. “Transaction level modeling: An overview”, ISSS 2003 Design methodology Set of models and transformations between models EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 5 Top-Down Design Flow requirements constraints Product planning pure functional Specification untimed System design bus functional Architecture timing accurate Processor design RTL / IS Implementation cycle accurate Logic design gates gate delays Structure Timing © 2008 A. Gerstlauer 6 Top-Down Design Flow requirements constraints Product planning pure functional Specification model untimed Computation design transaction level Computation model estimated timing Communication design bus functional Communication model timing accurate Processor design RTL / IS Implementation model cycle accurate Structure Logic design Timing © 2008 A. Gerstlauer 7 Top-Down Design Flow Product planning requirements constraints Capture Algor. IP pure functional Specification model untimed Computation refinement Comp. IP transaction level Computation model estimated timing Communication refinement Proto. IP bus functional Communication model timing accurate RTL Hardware Interface Software RTOS IP synthesis synthesis synthesis IP RTL / IS Implementation model cycle accurate Structure Logic design Timing EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 8 Design Methodology System design Validation flow Capture Algor. IP Compilation Simulation model Specification model Validation Analysis Estimation Computation refinement Comp. IP Compilation Simulation model Computation model Validation Analysis Estimation Communication refinement Proto. IP Compilation Simulation model Communication model Validation Analysis Estimation Hardware Interface Software RTL synthesis synthesis compilation RTOS IP IP Compilation Simulation model Implementation model Validation Analysis Backend Estimation EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 9 Specification Model • High-level, abstract model Specification model • Pure system functionality • Algorithmic behavior Computation refinement • No implementation details Computation model • No implicit structure / architecture Communication refinement • Behavioral hierarchy • Untimed Communication model • Executes in zero (logical) time Processor refinement • Causal ordering Implementation model • Events only for synchronization EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 10 Specification Model Example B1 B1 v1 B2v2 B3 e2 • Simple, typical specification model • Hierarchical parallel-serial composition • Communication through ports and variables, events EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 11 Specification Level Communication B2v2 B3 • Message-passing e2 • Abstract communication and synchronization • Encapsulate in channel B2 B3 c2 EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 12 Clean Specification Model Example B1 B1 v1 B2 B3 c2 • Synthesizable specification model • Hierarchical parallel-serial composition • Communication through variables and standard channels EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 13 Computation Refinement • PE allocation / selection Specification model Computation refinement • Behavior partitioning Computation model • Variable partitioning Communication refinement Communication model • Scheduling Processor refinement Implementation model EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 14 PE Allocation, Behavior Partitioning B1B1 PE1 • Allocate PEs v1 PE2 • Partition behaviors B2 B3 c2 • Globalize communication Additional level of hierarchy to model PE structure EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 15 Model after Behavior Partitioning PE1 PE2 B1B1 v1 B13snd cb13 B13rcv B2 B3 c2 B34rcv cb34 B34snd Synchronization to preserve execution order/semantics EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 16 Variable Partitioning Shared memory vs. message passing implementation • Map global variables to local memories • Communicate data over message-passing channels PE1 PE2 B1B1 v1 v1 v1 B13snd cb13 B13rcv B2 B3 c2 B34rcv cb34 B34snd EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 17 Model after Variable Partitioning PE1 PE2 B1B1 v1 B13snd cb13 B13rcv v1 B2 B3 c2 B34rcv cb34 B34snd Keep local variable copies in sync • Communicate updated values at synchronization points • Transfer control & data over message-passing channel EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 18 Timed Computation • Execution time of behaviors • Estimated target delay / timing budget • Granularity • Behavior / function / basic-block level Annotate behaviors 1 behavior B2( in int v1, ISend c2 ) { • Simulation feedback void main( void ) { … 5 waitfor ( delay1 ); • Synthesis constraints waitfor(( B2_DELAY1B2_DELAY1 );); c2.send( … ); … waitfor 10 waitfor(( B2_DELAY2B2_DELAY2 );); } }; EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 19 Scheduling Serialize behavior execution on components B1 PE1 B1 • Static scheduling – Fixed behavior execution order – Flattened behavior hierarchy B13snd • Dynamic scheduling B2 – Pool of tasks – Scheduler, abstracted OS B34rcv EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 20 Computation Model Example PE1 PE2 B1B1 v1 B13snd cb13 B13rcv v1 B2 B3 c2 B34rcv cb34 B34snd EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 21 Computation Model • Component structure/architecture Specification model • Top level of behavior hierarchy Computation refinement • Behavioral/functional component view • Behaviors grouped under top-level Computation model component behaviors Communication refinement • Sequential behavior execution Communication model • Timed Processor refinement • Estimated execution delays Implementation model EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 22 Communication Refinement • Network allocation / protocol selection Specification model Computation refinement • Channel partitioning Computation model • Protocol stack insertion Communication refinement Communication model • Inlining Processor refinement Implementation model EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 23 Network Allocation / Channel Partitioning PE1 PE2 B1B1 Bus1 • Allocate busses v1 B13snd cb13 B13rcv • Partition channels v1 B2 B3 • Update c2 communication B34rcv cb34 B34snd Additional level of hierarchy to model bus structure EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 24 Model after Channel Partitioning PE1 PE2 B1B1 Bus1 v1 cb13 B13rcv B13snd c2 v1 cb34 B2 B3 B34rcv B34snd EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 25 Protocol Insertion Bus1 Bus1 cb13 Network Protocol c2 Layer cb34 Layers • Insert protocol layer • Bus protocol channel from database • Create network layers • Implement message-passing over bus protocol • Replace bus channel • Hierarchical combination of complete protocol stack EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 26 Model after Protocol Insertion Master
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