Lecture 4 © 2008 A

EE382V: EmbeddedSystemDesignandModeling

Lecture4– SystemDesignFlowandMethodology

Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin [email protected] Lecture4:Outline

• SpecC systemdesignmethodology • From specification to implementation – Specification – System design – Processor design • Models and transformations – Specification model – Computation model – Communication model – Implementation model

Processor Control Pipeline IFFSM IPNetlist IP Memory RAM Comp. State PC Interface Interface IR

Bus Control Datapath IFFSM Memory Interface Interface Mem RF Processors Registers State State IPs ALUs/FUs Memories Memory Memories ALU Busses Gates CustomHW Specification Systemarchitecture ProcessorImplementation +constraints +estimates +results

• Specificationtoarchitecturetoimplementation • Behaviortostructure 1. System level: system specification to system architecture 2. Processor level: component behavior to component microarchitecture

• Designmodels • Representation for validation and analysis • Specification for further implementation/synthesis • Designlanguages • Specification down to implementation – Models of Computation (MoC) • System-level design languages (SLDL) – C-based, event-driven SLDLs [SpecC, SystemC] Welldefined,rigoroussystemlevelsemantics Unambiguous, explicit abstractions, models – Objects and composition rules Systematic flow from specification to implementation – Transformations and refinements Modelingflow Design automation for synthesis and verification

• Abstractionbasedonlevelofdetail(structure/timing) • Computation and communication Systemdesignflow Path from model A to model F

Cycle- timed D F

A. System specification model B. Component model C. Bus-arbitration model Approximate- C E D. Bus-functional model timed E. Cycle-accurate computation model F. RTL/ISS Implementation model Communication

Un- timed A B Un- Approximate- Cycle- Computation timed timed timed Source: Lukai Cai, D. Gajski. “Transaction level modeling: An overview”, ISSS 2003 Designmethodology Set of models and transformations between models EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 5 TopDownDesignFlow

requirements constraints Productplanning

pure functional Specification untimed

Systemdesign

bus functional Architecture timing accurate

Processordesign

RTL / IS Implementation cycle accurate

Logicdesign gates gate delays

Structure Timing

requirements constraints Productplanning

pure functional Specification model untimed

Computationdesign

transaction level Computation model estimated timing

Communicationdesign

bus functional Communication model timing accurate

Processordesign

RTL / IS Implementation model cycle accurate

Structure Logicdesign Timing

Product planning requirements constraints

Capture Algor. IP

pure functional Specification model untimed

Computation refinement Comp. IP

transaction level Computation model estimated timing

Communication refinement Proto. IP

bus functional Communication model timing accurate

RTL Hardware Interface Software RTOS IP synthesis synthesis synthesis IP

RTL / IS Implementation model cycle accurate

Structure Logicdesign Timing

Systemdesign Validationflow

Capture Algor. IP Compilation Simulation model Specification model Validation Analysis Estimation Computation refinement Comp. IP

Compilation Simulation model Computation model Validation Analysis Estimation Communication refinement Proto. IP

Compilation Simulation model Communication model Validation Analysis Estimation

Hardware Interface Software RTL synthesis synthesis compilation RTOS IP IP

Compilation Simulation model Implementation model Validation Analysis Backend Estimation

• Highlevel,abstractmodel Specificationmodel • Pure system functionality • Algorithmic behavior Computation refinement • No implementation details Computation model • Noimplicitstructure/architecture Communication refinement • Behavioral hierarchy • Untimed Communication model

• Executes in zero (logical) time Processor refinement • Causal ordering Implementation model • Events only for synchronization

B1 B1

B2v2 B3

• Simple,typicalspecificationmodel • Hierarchical parallel-serial composition • Communication through ports and variables, events

B2v2 B3 • Messagepassing e2

• Abstract communication and synchronization

• Encapsulate in channel

B2 B3 c2

B1 B1

B2 B3 c2

• Synthesizablespecificationmodel • Hierarchical parallel-serial composition • Communication through variables and standard channels

• PEallocation/selection Specification model

Computationrefinement • Behaviorpartitioning Computation model

• Variablepartitioning Communication refinement

Communication model • Scheduling Processor refinement

Implementation model

B1B1 PE1 • Allocate PEs

v1 PE2 • Partition behaviors

B2 B3 c2 • Globalize communication

AdditionallevelofhierarchytomodelPEstructure

PE1 PE2 B1B1

B13snd cb13 B13rcv

B2 B3 c2

B34rcv cb34 B34snd

Synchronizationtopreserveexecutionorder/semantics

Sharedmemoryvs.messagepassingimplementation • Map global variables to local memories • Communicate data over message-passing channels

PE1 PE2 B1B1

v1 v1 v1

B13snd cb13 B13rcv

B2 B3 c2

B34rcv cb34 B34snd

PE1 PE2 B1B1

B13snd cb13 B13rcv

B2 B3 c2

B34rcv cb34 B34snd

Keeplocalvariablecopiesinsync • Communicate updated values at synchronization points • Transfer control & data over message-passing channel

• Executiontimeofbehaviors • Estimated target delay / timing budget • Granularity • Behavior / function / basic-block level

Annotatebehaviors 1 behavior B2( in int v1, ISend c2 ) { • Simulation feedback void main( void ) { … 5 waitfor ( delay1 ); • Synthesis constraints waitfor(( B2_DELAY1B2_DELAY1 );); c2.send( … ); …

waitfor 10 waitfor(( B2_DELAY2B2_DELAY2 );); } };

Serializebehaviorexecutiononcomponents

B1 PE1 B1 • Static scheduling – Fixed behavior execution order – Flattened behavior hierarchy B13snd • Dynamic scheduling B2 – Pool of tasks – Scheduler, abstracted OS

B34rcv

PE1 PE2

B1B1

B13snd cb13 B13rcv

v1 B2 B3 c2

B34rcv cb34 B34snd

• Componentstructure/architecture Specification model • Top level of behavior hierarchy Computation refinement • Behavioral/functionalcomponentview • Behaviors grouped under top-level Computationmodel

component behaviors Communication refinement • Sequential behavior execution Communication model • Timed Processor refinement • Estimated execution delays Implementation model

• Networkallocation/protocolselection Specification model

Computation refinement • Channelpartitioning Computation model

• Protocolstackinsertion Communicationrefinement

Communication model • Inlining Processor refinement

Implementation model

PE1 PE2

B1B1

Bus1 • Allocate busses

B13snd cb13 B13rcv • Partition channels

v1 B2 B3 • Update c2 communication

B34rcv cb34 B34snd

Additionallevelofhierarchytomodelbusstructure

PE1 PE2

B1B1

Bus1 v1 cb13 B13rcv B13snd c2 v1 cb34 B2 B3

B34rcv B34snd

Bus1 Bus1

cb13 Network Protocol c2 Layer cb34 Layers

• Insertprotocollayer • Bus protocol channel from database • Createnetworklayers • Implement message-passing over bus protocol • Replacebuschannel • Hierarchical combination of complete protocol stack

Master Slave

PE1 PE2

B1B1 Bus1

BusProtocol v1 address[15:0] B13rcv data[31:0] B13snd ready v1 IProtocolSlave IProtocolMaster IBusSlave IBusMaster B2 B3

B34rcv B34snd

PE1 Bus1 PE2

BusProtocol address[15:0] data[31:0] control IProtocolSlave IProtocolMaster IBusSlave IBusMaster

• Create bus interfaces and drivers PE1 • Refine PE2 PE1Bus communication PE2Bus

address[15:0]

data[31:0]

ready IProtocolSlave IProtocolMaster PE1Protocol PE2Protocol IBusSlave IBusMaster

PE1 PE2

B1B1

address[15:0] v1 B13rcv data[31:0] B13snd v1 control B2 B3

B34rcv B34snd

Specification model • Component&busstructure/architecture • Top level of hierarchy Computation refinement

• Busfunctionalcomponentmodels Computation model • Timing-accurate bus protocols Communication refinement • Behavioral component description Communicationmodel • Timed • Estimated component delays Processor refinement

Implementation model

Specification model

• CycleaccurateimplementationofPEs Computation refinement • Hardware synthesis down to RTL Computation model • Software synthesis down to IS Communication refinement • Interface synthesis down to RTL/IS Communication model

Processorrefinement

Implementation model

PE2 B13rcv PE2_CLK v1 PE2_CLK B3 Clock boundaries

PE2_CLK

B34snd

• Scheduleoperationsintoclockcycles • Define clock boundaries in leaf behavior C code • Create FSMD model from scheduled C code

PE1

B1B1 Ff2 MOVE r0, r1

v1 SHL r3 ADD r2, r3, r4 INC r2 B13snd

PUSH r1 B2 CALL Ff3 POP r0

B34rcv

• Implementbehavioronprocessorinstructionset • Code generation • Compilation

S0 PE1Bus PE2Bus

S1 addr[15:0] addr[15:0] S2 data[31:0] data[31:0] DRV ready ready IProtocolSlave IProtocolMaster ack ack PE1Protocol PE2Protocol S3 IBusSlave IBusMaster

• Implementcommunicationoncomponents • Hardware bus interface logic • Software bus drivers

Softwareprocessor Customhardware

PE1 PE2

OBJ

S0 PORTA address[15:0]

Instruction S1 PORTB Set data[31:0] Simulator S2 PORTC ready (ISS) S3 INTA ack

PE1_CLK PE2_CLK

• Cycleaccuratesystemdescription Specification model

• RTL description of hardware Architecture exploration – Behavioral/structural FSMD view Architecture model • Object code for processors – Instruction-set co-simulation Communication synthesis

• Clocked bus communication Communication model – Bus interface timing based on PE clock Processor refinement

Implementationmodel

• Designmethodology • Four levels of abstraction – Specification model: untimed, functional – Computation model: estimated, structural – Communication model: timed, bus-functional – Implementation model: cycle-accurate, RTL/IS • Three refinement steps – Computation refinement – Communication refinement – Processor refinement » HW / SW / interface synthesis • Well-defined, formal models & transformations – Automatic, gradual refinement – Executable models, test bench re-use – Simple verification