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Choosing a Mixed Methods Design
04-Creswell (Designing)-45025.qxd 5/16/2006 8:35 PM Page 58 CHAPTER 4 CHOOSING A MIXED METHODS DESIGN esearch designs are procedures for collecting, analyzing, interpreting, and reporting data in research studies. They represent different mod- R els for doing research, and these models have distinct names and procedures associated with them. Rigorous research designs are important because they guide the methods decisions that researchers must make dur- ing their studies and set the logic by which they make interpretations at the end of studies. Once a researcher has selected a mixed methods approach for a study, the next step is to decide on the specific design that best addresses the research problem. What designs are available, and how do researchers decide which one is appropriate for their studies? Mixed methods researchers need to be acquainted with the major types of mixed methods designs and the common variants among these designs. Important considerations when choosing designs are knowing the intent, the procedures, and the strengths and challenges associated with each design. Researchers also need to be familiar with the timing, weighting, and mixing decisions that are made in each of the different mixed methods designs. This chapter will address • The classifications of designs in the literature • The four major types of mixed methods designs, including their intent, key procedures, common variants, and inherent strengths and challenges 58 04-Creswell (Designing)-45025.qxd 5/16/2006 8:35 PM Page 59 Choosing a Mixed Methods Design–●–59 • Factors such as timing, weighting, and mixing, which influence the choice of an appropriate design CLASSIFICATIONS OF MIXED METHODS DESIGNS Researchers benefit from being familiar with the numerous classifications of mixed methods designs found in the literature. -
Introducing New Design Disciplines Into a Traditional Industrial Design Program
NordDesign 2016 August 10 – 12, 2016 Trondheim, Norway Introducing New Design Disciplines Into a Traditional Industrial Design Program Bryan Howell, Camilla Gwendolyn Stark, Tyler James Christiansen, Ryan Hunter Hofstrand, Janae Lois Pettit, Samantha Nieves Van Slooten, Kathryn Joyce Willett Brigham Young University [email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected] Abstract The disciplines of design and design research are rapidly transforming. Sanders and Stappers (2013) illustrate how traditional design disciplines focused on product are being replaced with emerging disciplines focusing on “people in the context of their lives.” As an industry veteran and experienced design educator, I am well versed in the traditional method of effectively making consumer-oriented objects, but in the rapidly evolving world of contemporary design this expertise seemingly becomes less relevant each year. This paper reviews the quiet reframing of our sponsored third year industrial design studio course to explore aspects of emerging design disciplines, sharing five student projects that demonstrate the natural evolution in mindset from product-oriented to context-oriented problem definitions. Finally, it discusses how these emerging disciplines align with the values of the millennial generation and the importance educators include training in new disciplines to remain relevant in the contemporary design world. Keywords: Design -
Provocation Ii
FRIDAY, 25 SEPTEMBER 2020 ● 3.00 PM – 6.30 PM (CEST) THE DIGITAL MULTILOGUE ON FASHION EDUCATION PROVOCATIONS PROVOCATION I PROFESSOR DILYS WILLIAMS [∆] DIRECTOR OF CENTRE FOR SUSTAINABLE FASHION Professor Dilys Williams FRSA is the founder and Director of Centre for Sustainable Fashion, a University of the Arts London Research Centre, based at the London College of Fashion. Dilys’ work explores fashion’s relational ecological, social, economic and cultural elements to contribute to sustainability in and through its artistic, busi- ness and educational practices. Trained at Manchester Metropolitan University and holding a UAL professorship in Fashion Design for Sustainability, Dilys publishes widely on fashion and sustainability in peer-reviewed aca- demic journals and published books. Dilys’ work draws on extensive experience in lead womenswear designer roles for international collections, including at Katharine Hamnett, Liberty and Whistles. This industry expe- rience is complemented by a longstanding internationally recognized teaching and research portfolio centered on the development of sustainability centered design practices, based on principles of holism, participation and transformation design. She is a member of the UNFCCC Global Climate Action in Fashion and sits on advisory committees for Positive Luxury and the Global Fashion Agenda. Her place on the Evening Standard London’s Progress 1000 list in 2015, 2016 and 2017 evidences the public and academic influence of her work alongside regular appearances on broadcast television, radio and magazines including recent appearances on BBC World, Sky News, Radio 4, WWD,The Gentlewoman, Vog ue and Elle magazine. PROVOCATION II ASSISTANT PROFESSOR KIMBERLY JENKINS [∆] RYERSON UNIVERSITY AND FOUNDER OF THE FASHION AND RACE DATABASE Kimberly Jenkins, M.A. -
Introduction to ASIC Design
’14EC770 : ASIC DESIGN’ An Introduction Application - Specific Integrated Circuit Dr.K.Kalyani AP, ECE, TCE. 1 VLSI COMPANIES IN INDIA • Motorola India – IC design center • Texas Instruments – IC design center in Bangalore • VLSI India – ASIC design and FPGA services • VLSI Software – Design of electronic design automation tools • Microchip Technology – Offers VLSI CMOS semiconductor components for embedded systems • Delsoft – Electronic design automation, digital video technology and VLSI design services • Horizon Semiconductors – ASIC, VLSI and IC design training • Bit Mapper – Design, development & training • Calorex Institute of Technology – Courses in VLSI chip design, DSP and Verilog HDL • ControlNet India – VLSI design, network monitoring products and services • E Infochips – ASIC chip design, embedded systems and software development • EDAIndia – Resource on VLSI design centres and tutorials • Cypress Semiconductor – US semiconductor major Cypress has set up a VLSI development center in Bangalore • VDAT 2000 – Info on VLSI design and test workshops 2 VLSI COMPANIES IN INDIA • Sandeepani – VLSI design training courses • Sanyo LSI Technology – Semiconductor design centre of Sanyo Electronics • Semiconductor Complex – Manufacturer of microelectronics equipment like VLSIs & VLSI based systems & sub systems • Sequence Design – Provider of electronic design automation tools • Trident Techlabs – Power systems analysis software and electrical machine design services • VEDA IIT – Offers courses & training in VLSI design & development • Zensonet Technologies – VLSI IC design firm eg3.com – Useful links for the design engineer • Analog Devices India Product Development Center – Designs DSPs in Bangalore • CG-CoreEl Programmable Solutions – Design services in telecommunications, networking and DSP 3 Physical Design, CAD Tools. • SiCore Systems Pvt. Ltd. 161, Greams Road, ... • Silicon Automation Systems (India) Pvt. Ltd. ( SASI) ... • Tata Elxsi Ltd. -
Digital Design Flow Techniques and Circuit Design for Thin-Film Transistors
Printed by Tryckeriet i E-huset, Lund 2020 Printed by Tryckeriet SUMAN BALAJI Digital Design Flow Techniques and Circuit Design for Thin-Film Transistors SUMAN BALAJI MASTER´S THESIS Digital Design Flow Techniques and Circuit Design for Thin-Film Transistors for Thin-Film Design and Circuit Flow Design Techniques Digital DEPARTMENT OF ELECTRICAL AND INFORMATION TECHNOLOGY FACULTY OF ENGINEERING | LTH | LUND UNIVERSITY Series of Master’s theses Department of Electrical and Information Technology LUND 2020 LU/LTH-EIT 2020-770 http://www.eit.lth.se Digital Design Flow Techniques and Circuit Design for Thin-Film Transistors Suman Balaji [email protected] Department of Electrical and Information Technology Lund University Academic Supervisor: Joachim Rodrigues Supervisor: Hikmet Celiker Examiner: Pietro Andreani June 18, 2020 © 2020 Printed in Sweden Tryckeriet i E-huset, Lund Abstract Thin-Film Transistor (TFT) technology refers to process and manufacture tran- sistors, circuits, Integrated circuits (ICs) using thin-film organic or metal-oxide semiconductors on different substrates, such as flexible plastic foils and rigid glass substrates. TFT technology is attractive and used for applications requiring flexible, ultra- thin ICs to enable seamless integration into devices. TFT technology shows great potential to be an enabling technology for Internet of Things (IoT) applications. TFT is currently used and a dominant technology for switching circuits in flat- panel displays and are the main candidates for IoT applications in the near future because of its flexible structure, low cost. It is possible to design different kinds of Application-specific integrated circuits (ASIC) with flexible TFTs. Logic gates are considered as the basic building blocks of a digital circuit. -
The Effects of Globalization on the Fashion Industry– Maísa Benatti
ACKNOLEDGMENTS Thank you my dear parents for raising me in a way that I could travel the world and have experienced different cultures. My main motivation for this dissertation was my curiosity to understand personal and professional connections throughout the world and this curiosity was awakened because of your emotional and financial incentives on letting me live away from home since I was very young. Mae and Ingo, thank you for not measuring efforts for having me in Portugal. I know how hard it was but you´d never said no to anything I needed here. Having you both in my life makes everything so much easier. I love you more than I can ever explain. Pai, your time here in Portugal with me was very important for this masters, thank you so much for showing me that life is not a bed of roses and that I must put a lot of effort on the things to make them happen. I could sew my last collection because of you, your patience and your words saying “if it was easy, it wouldn´t be worth it”. Thank you to my family here in Portugal, Dona Teresinha, Sr. Eurico, Erica, Willian, Felipe, Daniel, Zuleica, Emanuel, Vitória and Artur, for understanding my absences in family gatherings because of the thesis and for always giving me support on anything I need. Dona Teresinha and Sr. Eurico, thank you a million times for helping me so much during this (not easy) year of my life. Thank you for receiving me at your house as if I were your child. -
An Automated Flow for Integrating Hardware IP Into the Automotive Systems Engineering Process
An Automated Flow for Integrating Hardware IP into the Automotive Systems Engineering Process Jan-Hendrik Oetjens Ralph Görgen Joachim Gerlach Wolfgang Nebel Robert Bosch GmbH OFFIS Institute Robert Bosch GmbH Carl v. Ossietzky University AE/EIM3 R&D Division Transportation AE/EIM3 Embedded Hardware-/ Postfach 1342 Escherweg 2 Postfach 1342 Software-Systems 72703 Reutlingen 26121 Oldenburg 72703 Reutlingen 26111 Oldenburg Jan-Hendrik.Oetjens Ralph.Goergen Joachim.Gerlach nebel@informatik. @de.bosch.com @offis.de @de.bosch.com uni-oldenburg.de Abstract during system integration is possible in an earlier stage of the systems engineering process. This contribution shows and discusses the require- Most of the companies’ system development processes ments and constraints that an industrial engineering follow – at least, in their basic principals – the well- process defines for the integration of hardware IP into known V model [1]. In our specific case, there is running the system development flow. It describes the developed an additional boundary through that V model. It partitions strategy for automating the step of making hardware de- the process steps into tasks to be done within our semi- scriptions available in a MATLAB/Simulink based system conductor division and tasks to be done within the corre- modeling and validation environment. It also explains the sponding system divisions (see Figure 1). The prior men- transformation technique on which that strategy is based. tioned acts as a supplier of the hardware parts of the over- An application of the strategy is shown in terms of an all system for the latter. Such boundaries also exist in industrial automotive electronic hardware IP block. -
Design for Manufacturing (Dfm) in Submicron Vlsi Design
DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY August 2007 Major Subject: Computer Engineering DESIGN FOR MANUFACTURING (DFM) IN SUBMICRON VLSI DESIGN A Dissertation by KE CAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Jiang Hu Committee Members, Weiping Shi Duncan Walker Vivek Sarin Head of Department, Costas N. Georghiades August 2007 Major Subject: Computer Engineering iii ABSTRACT Design for Manufacturing (DFM) in Submicron VLSI Design. (August 2007) Ke Cao, B.S., University of Science and Technology of China; M.S., University of Minnesota Chair of Advisory Committee: Dr. Jiang Hu As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII file to the foundry and expect very good man- ufacturing and parametric yield. This is largely due to the enormous challenges in the manufacturing stage as the feature size continues to shrink. Thus, the idea of DFM (Design for Manufacturing) is getting very popular. Even though there is no universally accepted definition of DFM, in my opinion, one of the major parts of DFM is to bring manufacturing information into the design stage in a way that is understood by designers. Consequently, designers can act on the information to improve both manufacturing and parametric yield. -
Changing Cultures of Design Identifying Roles in a Co-Creative Landscape
Changing Cultures of Design Identifying roles in a co-creative landscape Marie Elvik Hagen Department of Product Design Norwegian University of Science and Technology ABSTRACT The landscape of design is expanding and designers today are moving from expert practice to work with users as partners on increasingly complex issues. This article draws up the lines of the emerging co-creative design practice, and discusses the changing roles of the designer, the user as a partner, and design practice itself. Methods and tools will not be considered, as the roles will be discussed in terms of their relations. The co-design approach breaks down hierarchies and seeks equal participation. Research suggests that the designer needs to be responsive or switch tactics in order to take part in a co-creative environment. A case study exploring co-creative roles complements the theory, and finds that the designer role needs to be flexible even when having equal agency as partners and other stakeholders. Sometimes it is necessary to lead and facilitate as long as it is a collaborative decision. Bringing users in as partners in the process changes the design culture, and this article suggests that Metadesign can be the holistic framework that the design community need in order to understand how the different design practices are connected. KEYWORDS: Co-design, Co-creativity, Roles in the Design Process, Participatory Design, Metadesign, Cultures of participation, Design Agenda 1. INTRODUCTION This article seeks to examine how the role of the designer, the role of the user and the role The landscape of design is changing. -
Design for Manufacturability and Reliability in Extreme-Scaling VLSI
SCIENCE CHINA Information Sciences . REVIEW . June 2016, Vol. 59 061406:1–061406:23 Special Focus on Advanced Microelectronics Technology doi: 10.1007/s11432-016-5560-6 Design for manufacturability and reliability in extreme-scaling VLSI Bei YU1,2 , Xiaoqing XU2 , Subhendu ROY2,3 ,YiboLIN2, Jiaojiao OU2 &DavidZ.PAN2 * 1CSE Department, The Chinese University of Hong Kong, NT Hong Kong, China; 2ECE Department, University of Texas at Austin, Austin, TX 78712,USA; 3Cadence Design Systems, Inc., San Jose, CA 95134,USA Received December 14, 2015; accepted January 18, 2016; published online May 6, 2016 Abstract In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore’s law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI. Keywords design for manufacturability, design for reliability, VLSI CAD Citation Yu B, Xu X Q, Roy S, et al. Design for manufacturability and reliability in extreme-scaling VLSI. Sci China Inf Sci, 2016, 59(6): 061406, doi: 10.1007/s11432-016-5560-6 1 Introduction Moore’s law, which is named after Intel co-founder Gordon Moore, predicts that the density of transistor on integrated circuits (ICs) roughly doubles every two years. -
Chapter 8 – Timing Closure VLSI Physical Design
© KLMH Chapter 8 – Timing Closure VLSI Physical Design: From Graph Partitioning to Timing Closure Original Authors: Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 1 Lienig Chapter 8 – Timing Closure © KLMH 8.1 Introduction 8.2 Timing Analysis and Performance Constraints 8.2.1 Static Timing Analysis 8.2.2 Delay Budgeting with the Zero-Slack Algorithm 8.3 Timing-Driven Placement 8.3.1 Net-Based Techniques 8.3.2 Embedding STA into Linear Programs for Placement 8.4 Timing-Driven Routing 8.4.1 The Bounded-Radius, Bounded-Cost Algorithm 8.4.2 Prim-Dijkstra Tradeoff 8.4.3 Minimization of Source-to-Sink Delay 8.5 Physical Synthesis 8.5.1 Gate Sizing 8.5.2 Buffering 8.5.3 Netlist Restructuring 8.6 Performance-Driven Design Flow 8.7 Conclusions VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 2 Lienig 8.1 Introduction © KLMH System Specification Partitioning Architectural Design ENTITY test is port a: in bit; end ENTITY test; Functional Design Chip Planning and Logic Design Circuit Design Placement Physical Design Clock Tree Synthesis Physical Verification DRC and Signoff LVS Signal Routing ERC Fabrication Timing Closure Packaging and Testing Chip VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 3 Lienig 8.1 Introduction © KLMH • IC layout must satisfy geometric constraints and timing constraints − Setup (long-path) constraints − Hold (short-path) constraints • Chip designers must complete timing closure − Optimization process that meets timing constraints − Integrates point optimizations discussed in previous chapters, e.g., placement and routing, with specialized methods to improve circuit performance VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 4 Lienig 8.1 Introduction © KLMH Components of timing closure covered in this lecture: • Timing-driven placement (Sec. -
A Design & Verification Methodology for Networked Embedded Systems
Francesco Stefanni A Design & Verification Methodology for Networked Embedded Systems Ph.D. Thesis April 7, 2011 Università degli Studi di Verona Dipartimento di Informatica Advisor: Prof. Franco Fummi Co-Advisor: Assistant Professor Davide Quaglia Series N◦: TD-04-11 Università di Verona Dipartimento di Informatica Strada le Grazie 15, 37134 Verona Italy Γνωθι˜ σǫαυτoν,´ ǫνˇ o´ιδα oτιˇ oυδ´ ǫν` o´ιδα. Abstract Nowadays, Networked Embedded Systems (NES’s) are a pervasive technology. Their use ranges from communication, to home automation, to safety critical fields. Their increas- ing complexity requires new methodologies for efficient design and verification phases. This work presents a generic design flow for NES’s, supported by the implementation of tools for its application. The design flow exploits the SystemC language, and consid- ers the network as a design space dimension. Some extensions to the base methodology have been performed to consider the presence of a middleware as well as dependabil- ity requirements. Translation tools have been implemented to allow the adoption of the proposed methodology with designs written in other HDL’s. Contents 1 Introduction ................................................... ..... 1 1.1 Thesisstructure ................................. ................ 5 2 Background ................................................... ..... 7 2.1 Networked Embedded Systems . ............ 7 2.1.1 Communicationprotocols ........................ .......... 8 2.2 SystemLevelDesign ............................... ............