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Digital IC Design Flow

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Digital IC Design Flow Graduate Institute of Electronics Engineering, NTU DDigiigittaall IICC DDesesiigngn FFllowow Lecturer: Chihhao Chao Advisor: Prof. An-Yeu Wu Date: 2006.3.8 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU OuOuttlliinene vIntroduction vIC Design Flow vVerilogHistory vHDL concept pp. 2 Graduate Institute of Electronics Engineering, NTU Moore’s Law: Driving Technology Advances v Logic capacity doubles per IC at regular intervals (1965). v Logic capacity doubles per IC every 18 months (1975). pp. 3 Graduate Institute of Electronics Engineering, NTU PPrroocesscess TTecechhnolnolooggyy EEvvoluoluttionion pp. 4 Graduate Institute of Electronics Engineering, NTU CChiphipss SSiizzeses Source: IBM and Dataquest pp. 5 Graduate Institute of Electronics Engineering, NTU SShhrrininkkiningg PPrrooduducctt CCyycclleses v Shrinking product cycles PCS: Personal Communication Services v Shrinking development turnaround times v Need for productivity increase (remember the “design gap”) pp. 6 Graduate Institute of Electronics Engineering, NTU DDesesignign PPrrododuuccttiivviittyy CCrriissisis v Human factors may limit design more than technology. v Keys to solve the productivity crisis: v Design techniques: hierarchical design, SoCdesign (IP reuse, platform-based design), etc. v CAD: algorithms & methodology pp. 7 Graduate Institute of Electronics Engineering, NTU InIncreascreasinging PPrroocesscessinging PPoowwerer v Very high performance circuits in today’s technologies. v Gate delays: ~27ps for a 2-input Nandin 0.13um process v Operating frequencies: up to 500MHz for SoC/Asic, over 1GHz for customdesigns v The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application v Enhanced Design Tools and Techniques v Although not enough to close the “design gap”, tools are essential for the design of today’s high-performance chips pp. 8 Graduate Institute of Electronics Engineering, NTU IPIP--BBaseasedd SSooCsCs v An Evolutionary Path v Early days Ø IP/Cores not really designed for reuse (no standard deliverables) Ø Multiple Interfaces, difficult to integrate v IPsevolved: parameterization, deliverables, verification, synthesizable v On-Chip bus standards began to appear (e.g, IBM, ARM) v ReusableIP + Common on-chip bus architectures v 1998: max number of cores > 30 cores core content between 50% and 95% pp. 9 Graduate Institute of Electronics Engineering, NTU IIPP // CCooresres v Soft IP/Core v Delivered as RTL verilogor VHDL source code with synthesis script (i.e: clock generation logic) v Customers are responsible for synthesis, timing closure, and all front-end processing v Firm IP/Core v Delivered as a netlistto be included in customer’s netlist (with don't touch attribute) v Possibly with placement information v Hard IP/Core v Due to their complexity, they are provided as a blackbox (GL1/GDSII). Ex. Processors, analog cores, PLLs v Usually very tight timing constraints. Internal views not be alterable or visible to the customer pp. 10 Graduate Institute of Electronics Engineering, NTU CChhaangngeses iinn tthhee NaNatuturree ofof IICC DDeesisigngn (IEEE Spectrum Nov,1996) pp. 11 Graduate Institute of Electronics Engineering, NTU CChhasasinging tthhee DDesesignign GGapap pp. 12 Graduate Institute of Electronics Engineering, NTU EEvvoluoluttionion ooff SSiliiliccoonn DDesesignign Source: “Surviving the SoCrevolution – A Guide to Platform-based Design,” Henry Chang et al, KluwerAcademic Publishers, 1999 pp. 13 Graduate Institute of Electronics Engineering, NTU Methodology – Analysis and Verification pp. 14 Graduate Institute of Electronics Engineering, NTU IICC DDesesignign aanndd IImmplplemeemennttaattionion Idea Design pp. 15 Graduate Institute of Electronics Engineering, NTU DDesesignign FlFlowow Back End Cell Placement, Scan Pre-Synthesis Design Specification Chain & Clock Tree Sign-Off Insertion, Cell Routing Synthesize and Map Verify Physical & Design Partition Gate-Level Netlist Electrical Design Rules Design Entry-Verilog Post-Synthesis Extract Parasitics Behavioral Modeling Design Validation Simulation/Functional Post-Synthesis Post-Layout Verification Timing Verification Timing Verification Design Integration & Test Generation & Design Sign-Off Verification Fault Simulation Front End PProduroducctitonion-R-Reaeadydy MaMassksks pp. 16 Graduate Institute of Electronics Engineering, NTU SSysysttemem SSppececiiffiicacattionion From CIC pp. 17 Graduate Institute of Electronics Engineering, NTU AAllgogorriitthhmm MMaappippingng System Level RTL Level From CIC pp. 18 Graduate Institute of Electronics Engineering, NTU GGaattee aandnd CCiircrcuiuitt LLeevveell DDesesiigngn From CIC pp. 19 Graduate Institute of Electronics Engineering, NTU PPhhyyssiiccaall DDesesiigngn From CIC pp. 20 Graduate Institute of Electronics Engineering, NTU BBeehhaavvioiorarall MMododelel System concept Algorithm Increasing Increasing Architecture detailed behavioral realization & abstraction complexity Register Transfer Level Gate Level Transistor Level pp. 21 Graduate Institute of Electronics Engineering, NTU DDesesignign DDoomamainin Behavioral Design Model Domain level of abstraction Abstract Structural Physical Architecture System Synthesis Architecture RTL level Design Synthesis Algorithm Structural Logic level Design Synthesis RTL Verification Logic Design Gate Verification Layout Design Switch Verification pp. 22 Graduate Institute of Electronics Engineering, NTU InInttrroduoduccttiionon ttoo HDLHDL vHDL – Hardware Description Language vWhy use an HDL ? vHardware is becoming very difficult to design directly vHDL is easier and cheaper to explore different design options vReduce time and cost pp. 23 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDLHDL vBrief history of VerilogHDL v1985: Veriloglanguage and related simulator Verilog-XL were developed by Gateway Automation v1989: Cadence Design System purchased Gateway Automation v1990: Cadence released VerilogHDL to public domain v1990: Open VerilogInternational (OVI) formed v1995: IEEE standard 1364 adopted pp. 24 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDLHDL vFeature vHDL has high-level programming language constructs and constructs to describe the connectivity of your circuit. vAbility to mix different levels of abstraction freely vOne language for all aspects of design, test, and verification vFunctionality as well as timing vConcurrency perform vSupport timing simulation pp. 25 Graduate Institute of Electronics Engineering, NTU CCoommpparearedd ttoo VVHDLHDL v Verilog and VHDL are comparable languages v VHDL has a slightly wider scope v System-level modeling v Exposes even more discrete-event machinery v VHDL is better-behaved v Fewer sources of non-determinism (e.g., no shared variables ???) v VHDL is harder to simulate quickly v VHDL has fewer built-in facilities for hardware modeling v VHDL is a much more verbose language v Most examples don’t fit on slides pp. 26 Graduate Institute of Electronics Engineering, NTU ThThee VVereriloilogg LLaangunguaagege v Originally a modeling language for a very efficient event-driven digital logic simulator v Later pushed into use as a specification language for logic synthesis v Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other) v Combines structural and behavioral modeling styles pp. 27 Graduate Institute of Electronics Engineering, NTU DDiiffffereerenntt LLeevveellss ooff AAbbssttracracttiionon v Architectural / Algorithmic v A model that implements a design algorithm in high-level language constructs v Register Transfer Logic (RTL) v A model that describes the flow of data between registers and how a design process these data. v Gate v A model that describe the logic gates and the interconnections between them. v Switch v A model that describes the transistors and the interconnections between them. pp. 28 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDHDLL BBeehhaavvioiorr LLaangunguaagege v Structural and procedural like the C programming language v Used to describe algorithm level and RTL level Verilogmodels v Key features v Procedural constructs for conditional, if-else, case, and looping operations. v Arithmetic, logical, bit-wise, and reduction operations for expressions. v Timing control. pp. 29 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDHDLL SSttrruuccttuurarall LLaanngguuaagege vUsed to describe gate-level and switch-level circuits. vKey features vA complete set set of combinational primitives vSupport primitive gate delay specification vSupport primitive gate output strength specification pp. 30 Graduate Institute of Electronics Engineering, NTU LLaangunguaaggee CCoonnvveennttionsions v Case-sensitivity vVerilog is case-sensitive. v Some simulators are case-insensitive v Advice: -Don’t use case-sensitive feature! v Keywords are lower case v Different names must be used for different items within the same scope v Identifier alphabet: v Upper and lower case alphabeticals: a~zA~Z vDecimal digits: 0~9 vUnderscore: _ pp. 31 Graduate Institute of Electronics Engineering, NTU LLaangunguaaggee CCoonnvveennttionionss ((ccontont’’d)d) v Maximum of 1024 characters in identifier v First character not a digit v Statement terminated by ; v Free format within statement except for within quotes v Comments: v All characters after // in a line are treated as a comment v Multi-line comments begin with /* and end with */ v Compiler directives begin
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