Graduate Institute of Electronics , NTU

DDigiigittaall IICC DDesesiigngn FFllowow

Lecturer: Chihhao Chao Advisor: Prof. An-Yeu Wu Date: 2006.3.8

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU OuOuttlliinene vIntroduction vIC Flow vVerilogHistory vHDL concept

pp. 2 Graduate Institute of Electronics Engineering, NTU

Moore’s Law: Driving Technology Advances v Logic capacity doubles per IC at regular intervals (1965). v Logic capacity doubles per IC every 18 months (1975).

pp. 3 Graduate Institute of Electronics Engineering, NTU PPrroocesscess TTecechhnolnolooggyy EEvvoluoluttionion

pp. 4 Graduate Institute of Electronics Engineering, NTU CChiphipss SSiizzeses

Source: IBM and Dataquest

pp. 5 Graduate Institute of Electronics Engineering, NTU SShhrrininkkiningg PPrrooduducctt CCyycclleses

v Shrinking product cycles PCS: Personal Communication Services v Shrinking development turnaround times v Need for productivity increase (remember the “design gap”)

pp. 6 Graduate Institute of Electronics Engineering, NTU DDesesignign PPrrododuuccttiivviittyy CCrriissisis

v Human factors may limit design more than technology. v Keys to solve the productivity crisis: v Design techniques: hierarchical design, SoCdesign (IP reuse, platform-based design), etc. v CAD: algorithms & methodology

pp. 7 Graduate Institute of Electronics Engineering, NTU InIncreascreasinging PPrroocesscessinging PPoowwerer v Very high performance circuits in today’s technologies. v Gate delays: ~27ps for a 2-input Nandin 0.13um process v Operating frequencies: up to 500MHz for SoC/Asic, over 1GHz for customdesigns v The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application v Enhanced Design Tools and Techniques v Although not enough to close the “design gap”, tools are essential for the design of today’s high-performance chips

pp. 8 Graduate Institute of Electronics Engineering, NTU IPIP--BBaseasedd SSooCsCs v An Evolutionary Path v Early days Ø IP/Cores not really designed for reuse (no standard deliverables) Ø Multiple Interfaces, difficult to integrate v IPsevolved: parameterization, deliverables, verification, synthesizable v On-Chip bus standards began to appear (e.g, IBM, ARM) v ReusableIP + Common on-chip bus v 1998: max number of cores > 30 cores core content between 50% and 95%

pp. 9 Graduate Institute of Electronics Engineering, NTU IIPP // CCooresres v Soft IP/Core v Delivered as RTL verilogor VHDL source code with synthesis script (i.e: clock generation logic) v Customers are responsible for synthesis, , and all front-end processing v Firm IP/Core v Delivered as a netlistto be included in customer’s netlist (with don't touch attribute) v Possibly with placement information v Hard IP/Core v Due to their complexity, they are provided as a blackbox (GL1/GDSII). Ex. Processors, analog cores, PLLs v Usually very tight timing constraints. Internal views not be alterable or visible to the customer

pp. 10 Graduate Institute of Electronics Engineering, NTU

CChhaangngeses iinn tthhee NaNatuturree ofof IICC DDeesisigngn

(IEEE Spectrum Nov,1996)

pp. 11 Graduate Institute of Electronics Engineering, NTU CChhasasinging tthhee DDesesignign GGapap

pp. 12 Graduate Institute of Electronics Engineering, NTU EEvvoluoluttionion ooff SSiliiliccoonn DDesesignign

Source: “Surviving the SoCrevolution – A Guide to Platform-based Design,” Henry Chang et al, KluwerAcademic Publishers, 1999

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Methodology – Analysis and Verification

pp. 14 Graduate Institute of Electronics Engineering, NTU IICC DDesesignign aanndd IImmplplemeemennttaattionion

Idea Design

pp. 15 Graduate Institute of Electronics Engineering, NTU DDesesignign FlFlowow Back End Cell Placement, Scan Pre-Synthesis Design Specification Chain & Clock Tree Sign-Off Insertion, Cell Routing

Synthesize and Map Verify Physical & Design Partition Gate- Netlist Electrical Design Rules

Design Entry-Verilog Post-Synthesis Extract Parasitics Behavioral Modeling Design Validation

Simulation/Functional Post-Synthesis Post-Layout Verification Timing Verification Timing Verification

Design Integration & Test Generation & Design Sign-Off Verification Fault Simulation

Front End PProduroducctitonion-R-Reaeadydy MaMassksks

pp. 16 Graduate Institute of Electronics Engineering, NTU SSysysttemem SSppececiiffiicacattionion

From CIC

pp. 17 Graduate Institute of Electronics Engineering, NTU AAllgogorriitthhmm MMaappippingng

System Level

RTL Level

From CIC

pp. 18 Graduate Institute of Electronics Engineering, NTU GGaattee aandnd CCiircrcuiuitt LLeevveell DDesesiigngn

From CIC

pp. 19 Graduate Institute of Electronics Engineering, NTU PPhhyyssiiccaall DDesesiigngn

From CIC

pp. 20 Graduate Institute of Electronics Engineering, NTU BBeehhaavvioiorarall MMododelel

System concept Algorithm Increasing Increasing detailed behavioral realization & abstraction complexity Register Transfer Level

Gate Level

Transistor Level

pp. 21 Graduate Institute of Electronics Engineering, NTU DDesesignign DDoomamainin

Behavioral Design Model Domain level of abstraction Abstract Structural Physical

Architecture System Synthesis Architecture RTL level Design Synthesis Algorithm Structural Logic level Design Synthesis RTL Verification Logic Design Gate Verification Layout Design Switch Verification

pp. 22 Graduate Institute of Electronics Engineering, NTU InInttrroduoduccttiionon ttoo HDLHDL vHDL – Hardware Description Language vWhy use an HDL ? vHardware is becoming very difficult to design directly vHDL is easier and cheaper to explore different design options vReduce time and cost

pp. 23 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDLHDL vBrief history of VerilogHDL v1985: Veriloglanguage and related simulator Verilog-XL were developed by Gateway Automation v1989: Cadence Design System purchased Gateway Automation v1990: Cadence released VerilogHDL to public domain v1990: Open VerilogInternational (OVI) formed v1995: IEEE standard 1364 adopted

pp. 24 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDLHDL vFeature vHDL has high-level programming language constructs and constructs to describe the connectivity of your circuit. vAbility to mix different levels of abstraction freely vOne language for all aspects of design, test, and verification vFunctionality as well as timing vConcurrency perform vSupport timing simulation

pp. 25 Graduate Institute of Electronics Engineering, NTU CCoommpparearedd ttoo VVHDLHDL v Verilog and VHDL are comparable languages v VHDL has a slightly wider scope v System-level modeling v Exposes even more discrete-event machinery v VHDL is better-behaved v Fewer sources of non-determinism (e.g., no shared variables ???) v VHDL is harder to simulate quickly v VHDL has fewer built-in facilities for hardware modeling v VHDL is a much more verbose language v Most examples don’t fit on slides

pp. 26 Graduate Institute of Electronics Engineering, NTU ThThee VVereriloilogg LLaangunguaagege v Originally a modeling language for a very efficient event-driven digital logic simulator v Later pushed into use as a specification language for v Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other) v Combines structural and behavioral modeling styles

pp. 27 Graduate Institute of Electronics Engineering, NTU DDiiffffereerenntt LLeevveellss ooff AAbbssttracracttiionon v Architectural / Algorithmic v A model that implements a design algorithm in high-level language constructs v Register Transfer Logic (RTL) v A model that describes the flow of data between registers and how a design process these data. v Gate v A model that describe the logic gates and the interconnections between them. v Switch v A model that describes the transistors and the interconnections between them.

pp. 28 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDHDLL BBeehhaavvioiorr LLaangunguaagege v Structural and procedural like the C programming language v Used to describe algorithm level and RTL level Verilogmodels v Key features v Procedural constructs for conditional, if-else, case, and looping operations. v Arithmetic, logical, bit-wise, and reduction operations for expressions. v Timing control.

pp. 29 Graduate Institute of Electronics Engineering, NTU VVererilogilog HDHDLL SSttrruuccttuurarall LLaanngguuaagege vUsed to describe gate-level and switch-level circuits. vKey features vA complete set set of combinational primitives vSupport primitive gate delay specification vSupport primitive gate output strength specification

pp. 30 Graduate Institute of Electronics Engineering, NTU LLaangunguaaggee CCoonnvveennttionsions v Case-sensitivity vVerilog is case-sensitive. v Some simulators are case-insensitive v Advice: -Don’t use case-sensitive feature! v Keywords are lower case v Different names must be used for different items within the same scope v Identifier alphabet: v Upper and lower case alphabeticals: a~zA~Z vDecimal digits: 0~9 vUnderscore: _

pp. 31 Graduate Institute of Electronics Engineering, NTU LLaangunguaaggee CCoonnvveennttionionss ((ccontont’’d)d) v Maximum of 1024 characters in identifier v First character not a digit v Statement terminated by ; v Free format within statement except for within quotes v Comments: v All characters after // in a line are treated as a comment v Multi-line comments begin with /* and end with */ v Compiler directives begin with // synopsysXXX v Built-in system tasks or functions begin with $ v Strings enclosed in double quotes and must be on a single line “Strings”

pp. 32 Graduate Institute of Electronics Engineering, NTU DDesesignign EEnncacappssululaattionion v Encapsulate structural and functional details in a module

module my_design (ports_list);

... // Declarations of ports go here ... // Structural and functional details go here

endmodule v Encapsulation makes the model available for instantiation in other modules

pp. 33 Graduate Institute of Electronics Engineering, NTU PPoorrtt DDececllaraarattiionon vThree port types module vInput port input output Øinput a; regor net net regor net net inout net vOutput port Øoutput b; net

vBi-direction port Port list Øinoutc; module full_add (S, CO, A, B, CI) ;

output S,CO ; Port Declaration input A, B, CI ;

---function description ---

endmodule

pp. 34 Graduate Institute of Electronics Engineering, NTU TTwwoo MMaaiinn DDaattaa TTyyppeses v Nets represent connections between things v Do not hold their value v Take their value from a driver such as a gate or other module v Cannot be assigned in an initial or always block v Regs represent data storage v Behave exactly like memory in a computer v Hold their value until explicitly assigned in an initial or always block v Never connected to something v Can be used to model latches, flip-flops, etc., but do not correspond exactly v Shared variables with all their attendant problems

pp. 35 Graduate Institute of Electronics Engineering, NTU PPrriimmiittiivvee CCeellslls v Primitives are simple modules v Verilogbuild-in primitive gate v not, buf: Ø Variable outputs, single input (last port) v and, or, buf, xor, nand, nor, xnor: Ø Single outputs (first port), variable inputs module full_add (S, CO, A, B, CI) ;

---port Declaration ---

wire net1, net2, net3; xor U0(S,A,B,CI); and U1(net1, A, B); and U2(net2, B, CI); and U3(net3, CI, A); or U4(CO, net1, net2, net3); endmodule

pp. 36 Graduate Institute of Electronics Engineering, NTU HHooww AArere SSiimmuullaattoorsrs UUsesed?d? v Testbench generates stimulus and checks response v Coupled to model of the system v Pair is run simultaneously

Stimulus

Testbench System Model Response Result checker

pp. 37 Graduate Institute of Electronics Engineering, NTU EExamxamplplee:: TTesesttbbeennchch module t_full_add(); wire sum, c_out; rega, b, cin; // Storage containers for stimulus waveforms full_addM1 (sum, c_out, a, b, cin); //UUT initial begin // Time Out #200 $finish; // Stopwatch end initial begin // Stimulus patterns #10 a = 0; b = 0; cin= 0; // Statements execute in sequence #10 a = 0; b = 1; cin= 0; #10 a = 1; b = 0; cin= 0; #10 a = 1; b = 1; cin= 0; #10 a = 0; b = 0; cin= 1; #10 a = 0; b = 1; cin= 1; #10 a = 1; b = 0; cin= 1; #10 a = 1; b = 1; cin= 1; end endmodule

pp. 38 Graduate Institute of Electronics Engineering, NTU VVererilogilog SSiimmululaattoror

pp. 39 Graduate Institute of Electronics Engineering, NTU EEvveentnt--DrDriivveenn SSiimmululaattionion v A change in the value of a signal (variable) during simulation is referred to as an event v Spice-like analog simulation is impractical for VLSI circuits v Event-driven simulators update logic values only when signals change

pp. 40 Graduate Institute of Electronics Engineering, NTU StStyylleses vStructural -instantiation of primitives and modules vRTL/Dataflow -continuous assignments vBehavioral -procedural assignments

pp. 41 Graduate Institute of Electronics Engineering, NTU StStrruuccttuurarall MMododeelingling vWhen Verilog was first developed (1984) most logic simulators operated on netlists vNetlist: list of gates and how they’re connected vA natural representation of a digital logic circuit vNot the most convenient way to express test benches

pp. 42 Graduate Institute of Electronics Engineering, NTU BBeehhaavvioiorarall MMododeelilingng vA much easier way to write testbenches vAlso good for more abstract models of circuits vEasier to write vSimulates faster vMore flexible vProvides sequencing vVerilog succeeded in part because it allowed both the model and the testbench to be described together

pp. 43 Graduate Institute of Electronics Engineering, NTU StStyyllee EExxamamplplee -- StStrruuccttuuralral module full_add (S, CO, A, B, CI) ; module half_add (S, C, X, Y); output S,CO ; output S, C ; input A, B, CI ; input X, Y ; wire N1, N2, N3; xor (S, X, Y) ; and (C, X, Y) ; half_add HA1 (N1, N2, A, B), HA2 (S, N3, N1, CI); endmodule or P1 (CO, N3, N2); endmodule

pp. 44 Graduate Institute of Electronics Engineering, NTU StStyyllee EExxamamplplee –– DDaattaaffllooww//RRTLTL modulefa_rtl (S, CO, A, B, CI) ; output S,CO ; input A, B, CI ; assign S = A ^ B ^ CI; //continuous assignment assign CO = A & B | A & CI | B & CI; //continuous assignment endmodule

pp. 45 Graduate Institute of Electronics Engineering, NTU StStyyllee EExxamamplplee –– BBeehhaavvioiorralal modulefa_bhv (S, CO, A, B, CI) ; output S,CO ; input A, B, CI ; reg S, CO; // required to “hold” values between events. always@(A or B or CI) //; begin S <= A ^ B ^ CI; // procedural assignment CO <= A & B | A & CI | B & CI; // procedural assignment end endmodule

pp. 46 Graduate Institute of Electronics Engineering, NTU HHooww VVereriloilogg IIss UUsedsed v Virtually every ASIC is designed using either Verilog or VHDL (a similar language) v Behavioral modeling with some structural elements v “Synthesis subset” v Can be translated using Synopsys’ Design Compiler or others into a netlist v Design written in Verilog v Simulated to death to check functionality v Synthesized (netlist generated) v to check timing

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