Optimizing IC Design for Manufacturability - 2011 Update

134 Recent Patents on Electrical & Electronic Engineering 2012, 5, 134-154 Optimizing IC Design for Manufacturability - 2011 Update

Artur Balasinski*

Cypress Semiconductor

Received: December 17, 2011; Revised: April 10, 2012; Accepted: April 25, 2012

Abstract: Integrating Circuit Design for Manufacturability (IC DfM) involves various methodologies, techniques, and tools to improve semiconductor reliability and fab yield metrics by optimizing device design or layout. Recent years have seen propagation of IC DfM into the multiple aspects of semiconductor product definition. In addition to the traditional, mainstream DfM related to the corrections of circuit layout by the different types of pattern resolution enhancement techniques, recent DfM disclosures related to stacked die verification, 3D die packaging, floorplanning, and wiring have been proposed to help with the growing number of IC applications. These extended categories of DfM would be useful especially for Systems-on-Chip as well as for the further pursuit of IC shrinkability, e.g. by double patterning. In this work, we discuss nineteen representative IC DfM disclosures filed or published in 2011 and 2012. Similarly, as in the previous review [1], we divided the patents into the ones pertaining to DfM definition, DfM execution, and DfM verification. The focus of the first group of patents (definition) was the correct-by-construction (CBC) architecture, e.g., of layout (active devices, metal routing), die floorplan, or package. The second group (execution) pertained to process proximity correction (mostly OPC), and the third group (verification) concentrated on process model calibration and identifying the sources of process variability. These directions of DfM development, consistent over the recent years, show the validity of the existing DfM approach to solve future design problems. Keywords: DfM, die packaging, floor planning, integrated circuit design, layout, OPC, process compensation.

1. INTRODUCTION hand, delaying new product design in order to comply with DfM principles is undesired. Therefore, implementing good Design for Manufacturability (DfM) has long been con- DfM ideas as early in product definition as possible would sidered a key methodology to improve semiconductor inte- not only help reduce delays but also improve cost efficiency. grated circuit (IC) manufacturing or reliability yield by optimizing its design, or more frequently, layout [1]. Recent Depending on the stage of their introduction in the design patents filed or issued throughout the years 2011-2012 ex- cycle we had proposed before to divide DfM patent portfolio pand the DfM concepts related to layout enhancements and into three groups Definition, Execution, and Verification Fig. add disciplines serving new IC product applications. (1) [1]. At the earliest, Definition stage, DfM precedes IC design rules and guidelines, as correct-by-construction DfM is an art of balance based on the knowledge from (CBC) layout or product architecture, from single cell [2, 3], multiple engineering areas, such as electrical, optical, and to die [4-8] and to package level [9]. At the intermediate, mechanical engineering, striving to accomplish production Execution stage, DfM aligns with design or mask data verifi- goals such as high die yield, attractive product performance, cation for the IC layout, with emphasis on process proximity and zero reliability fallouts at low cost. It is at the discretion correction (OPC, PPC) [10-15]. Finally, at the latest, Verifi- of the design and manufacturing engineering, which of the cation stage, DfM patents improve manufacturing feedback techniques belong or do not belong to DfM. In this work, the to design/layout, [16-21]. Accordingly, the 19 examples of author stipulates that the new inventions in DfM apply not recent patent applications and publications discussed in this only to the layout, manufacturing or device parameters, but paper cover the following subjects: expand into the areas of floorplanning and packaging. For many patents, it may be difficult to quantify the im- A. Definition – CBC (cell to package level): portance of the improvements. Typically, there is no return on investment (RoI) discussed in patent publications, which 1. Dialed – in layout shrinking [2] leaves it to the reader to judge the value of the inventions. 2. Double patterning with hard mask [3] On the one hand, the difference between poor and good DfM 3. Spacer – based devices [4] can translate into schedule shifts of a new product yield ramp, which, when multiplied by multi-million dollar quar- 4. Advanced die floorplanning [5] terly revenues, could justify the cost of DfM development 5. Slotting of wide metal buses [6] including software tool licenses and manpower. On the other 6. Antenna ratio suppression [8]

*Address correspondence to this author at the Cypress Semiconductor, 7. Three-dimensional packaging [9] 12230 World Trade Dr., San Diego, CA 92128, USA; Tel: 858 613 5532; Fax: 858 676 6896; E-mail [email protected]

els of DRC rules. A very robust CBC design needs only a Definition Execution Verification basic, geometric DRC deck of width and space to prevent

printability violations. A layout not adhering to DfM rules Cell CBC End will require a more restrictive rule system to address pattern Level distortions. A fully random layout calls for a restrictive DRC to help with layout matching or fab transferability. These Design Multi-cell PV Start levels of robustness should be considered for the disclosures Intent IP Clean? presented below, related to a dialed – in layout shrink, p-Cell based metal slotting, or suppressing antenna effects. Other Design Drawn Hot Rules Die database Spots new concepts involving CBC such as floorplanning or 3D devices, may require establishing new design rule systems for System-on-Chip (SoC) products. Masks Cost Models reduction 2.1.1. Layout Shrinking by ePatterning

Fab Mfg data One fast path to CBC layout is by applying a shrink to a

known good design IP, to convert a product from the less to the more advanced technology node [2]. Geometric DRC for IP Protection the target process should suffice to ensure that the scaled

down but robust layout would perform out of the box with- Fig. (1). Three domains of DfM and their implementation in design out model redevelopment and resimulations. But the ques- cycle [1]. tion is, how much effort is saved by shrinking the layout vs. designing it from scratch and what opportunities are lost by B. Execution – Validation (cell to die level): skipping the relayout phase which may allow for product 8. Pixel-based OPC [10] optimization. 9. Cluster-based OPC [11] To make sure that the shrunk design is comprehensively checked, the design libraries need to be extended to include 10. Resolving OPC conflicts [12] tables and formulae which the authors call electrical pattern- 11. Auxiliary OPC patterns [13] ing (ePatterning) information. The concept of ePattering re- flects the expected correlation between wafer pattern and 12. A DfM Flowchart [14] device parameters to help with layout corrections. When a 13. Process compensation in IP libraries [15] wafer pattern of a transistor is electrically simulated, the op- tically simulated shapes of gate electrode and active region C. Verification – Feedback to design (die to wafer are simplified to rectangles, from which the electrical pa- level): rameters are determined based on ePatterning tables. 14. Etch process model [16] Figure 2 illustrates the concept of IP migration from a 90 nm to a 65 nm technology node. A hard intellectual property 15. Mismatch evaluation [17] (IP) block after shrinking, gridding, and compaction (anneal- 16. Process Variation on-chip sensor [18] ing), must meet timing and power constraints at the target technology node, i.e., with new lithoprocess, materials, im- 17. Planarity-related hot spots [19] plants etc. SPICE model changes due to different device and 18. Verification of 3D devices [20] process targets need to be implemented, using the ePattern- ing technique Fig. (3). In the process, layout geometries are 19. Table-based DfM [21] divided, matched, and scanned for repetitive blocks, to be extracted and stored into a database or library. Optical and 2. RECENT DFM DISCLOSURES electrical targeting with OPC (scattering bars, serifs, ham- 2.1. DFM Definition: Correct-By-Construction (CBC) merheads) and eOPC (drawn geometry extensions) helps Architectures achieve high resolution according to optical simulation and equivalent electrical properties. Because design verification may take up to 80% of design development effort, one should use a correct – by – con- Next, model-based or rule-based ePatterning corrections struction architectures based on known good design intellec- are applied. First, a maximum rectangle inside the channel tual property (IP) for cost reduction. For CBC layout, one contour of the transistor is defined by overlaying it with gate may first assume that no design rules need to be checked for active contours. Then, the equivalent electrical width of the the 100% product yield. Restricting layout freedom up-front channel proven by electrical simulation (e.g., SPICE), is de- due to CBC should remove the need for corrections, if at the rived. Parametric correlations between the effective geome- expense of the die footprint. However, even for CBC cells, try and parameters in ePatterning equations are saved in the some aspects of layout placement may get overlooked, so ePatterning database. one should still run a design rule check (DRC) with com- This way, when an IC product is to be transferred from plexity depending on the confidence of IP robustness with one manufacturing technology to another, the designer does respect to process and design variations. Three robustness not need to be involved. The semiconductor manufacturer levels can be proposed, depending on the restrictiveness lev- 136 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

sign new products from scratch, based on new models, especially in the analog domain. Keep Block’s In summary, comparing full redesign to algorithm based

Perfor‐ IP reuse, one should note that the footprint is not the only mance trade off. Sometimes, more important is the time to market. Layout translation based on fast but poor verification carries a risk that a lot of effort would be spent on debugging both correction algorithms and the suboptimal design. 2.1.2. Double Patterning with Hard Mask Improving optical resolution of pattern transfer from design to wafer is a fundamental challenge for DfM. Masking Shrink & Optimization elements and methodologies that enable printing layout geometries as small as 50% of the critical dimension of the Fig. (2). The concept of shrinking design IP from larger to smaller technology node. photolithography tool in the fab, are in high demand. The concept of multiple (e.g., double) patterning by exposing elements of the layout with multiple masks has enabled significant enhancements, compared to its single – patterning counterpart. But image distortions for the overlying patterns make double patterning a methodology more difficult from single patterning repeated twice.

In [3], the first pattern is transfered from photoresist to

the hard mask layer, followed by the second photoresist layer patterned over it Fig. (4). A custom photolithography method splits layout geometries between the first and second pattern creates an overlap area where the patterns are projected on a common surface [3]. First pattern is etched into a hard mask and second photoresist layer deposited on the hard mask transfers the pattern of the second mask Fig. (5). The overlap area is then transferred to the wafer. Critical dimensions of both masks are larger than the resolution of a photolithography tool. Figure 6 shows cross-sectional views aligned with process steps of Fig. (5). Figure 7 shows a mask and a wafer image bridging due to the conventional photolithography.

Provide a substrate

Form an etch layer on substrate

Fig. (3). IC layout migration flow using dialed – in shrinking. can independently redesign the IC by shrinking the IP. To Form a hard mask layer on the etch layer make sure that performance of an IP block in the migrated technology node is substantially the same as that of the block in the original technology node, IP migrates in two phases: Form a second photoresist layer on the Phase 1 = DRC clean and Phase 2 = electrically matched. hard mask layer and the etch layer A CBC concept of ePatterning based on optical and electrical simulations, self-adjusting OPC, and data tabulariza- tion has a number of risks. The apparent DfM benefit of the Transfer pattern of the second mask to IP scaling can be undone by months of product debugging on the second photoresist layer by exposure silicon without full simulation. While layout migration may and development become a useful technique for design cost reduction, product design cannot typically be achieved without statistical corner models, for two reasons: Transfer the overlap area to the wafer complexity: the disclosure does not provide sufficient according to the second photoresist layer insight about the practicality of ePatterning equations, and the hard mask layer, by etching lack of experience: a dial-in layout scaling has not been the mainstream design activity. It is still preferred to de- Fig. (4). Flow chart for double - patterning with hard mask.

IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 137

OVERLAP

Fig. (5). Layout overlaps for first and second mask patterns. b)

Fig. (7). a) Bridging of wafer pattern due to single mask approach, b) layout splitting between two masks.

Fig. (6). Cross-sections of wafer pattern after first and second masking process.

c) In summary, the proposed concept of multiple patterning has a chance of becoming the industry workhorse, due to the well defined path of reducing line CD’s below the tool resolution limits. 2.1.3. Spacer – based Devices Fig. (8). a) Dummy structures laid out to form spacer pattern, b) top view of spacer pattern, c) cross-sections of fin FETs. Another example of multiple patterning is fabrication of spacer-based finFET devices to reduce overlay errors be- (e.g., DRC, LVS), parameter extraction, layout place and tween photomasks [4]. A spacer based layout may be exe- route matching verification of paired elements and other cuted by first generating a global grid pattern of a dummy procedures. layer. A logic operation is then performed on the overlay patterns to find critical margins and regions where bias may In Figure 8, the first pattern defines dummy structures to be added to the adjacent features, to protect geometries of the form spacer elements abutting the pattern line. The spacers first pattern. This is followed by simulations, verification define critical dimensions for the features, such as a fin, on

138 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski the substrate. A second pattern removes top spacer material and the third, cut pattern, defines the active area by removing B* Tree unwanted spacer elements. Their width and pitch define fin- FET devices at less (50%) than minimum critical dimension of the photolithography. Apply random move The pattern formed from the overlay of the first, second, and third patterns is then used to etch the substrate to form a masking element. The hard mask is patterned as derivative Evaluate obj. function dummy or a spacer layer and then removed from the substrate, eventually to form a grid of masking elements Fig. (9). The fins may be formed by etching the substrate. No Accept move?

Modify B* Tree

Obj. function No optimized?

Fig. (9). Masking elements creating spacer pattern. Terminate process In summary, the spacer – based methodology of defining 3D devices is one of the key drivers for further technology Fig. (10). Annealing algorithm using the B* tree. shrinks. It has already been proven successful for many it randomly applies one of the three moves to evaluate the products. One should note that the IC companies readily newly generated B* tree. The move is accepted or rejected have experimental material predating this disclosure, as the depending on whether it improves placement objective such spacer-based concepts of CD reduction have been considered as area or wirelength, and repeated until a satisfactory solu- for many years. tion is obtained. 2.1.4. Advanced Die Floorplanning The sequential floorplanning progresses by repeatedly Another important application of CBC design is auto- applying a random move of a block and modifying the floor- mated layout floorplanning. It should be done right for the plan based on the acceptance of the move. A typical run will first time, as it can not be easily corrected and it influences evaluate thousands of moves, creating a long chain of control many parameters of the product. While efficient floorplan- and data dependencies. This chain must be broken to restruc- ning needs tools with significant computing power, the im- ture the process for efficient mapping onto a GPU, while plementation of parallel processing claims about 30% im- preserving the solution quality. provement in time to solution, compared to the prior art At high-level, the CPU uses the GPU as an accelerator based on serial computing architectures [5]. for a specific function (kernel function). The CPU will send Efficient block data structure should represent non- a kernel function to the GPU, along with data for manipula- slicing floorplans. One is an ordered B* tree (binary tree), in tion. All threads execute the same kernel function, but differ- 2 which nodes are kept /3 full by redistributing keys to fill two ent threads may perform different data manipulation. To child nodes, then splitting them into three nodes. O-tree (or- parallelize the floorplanning by breaking the dependency dered tree) is a data structure where the children of every chain of sequential process, one can apply multiple concur- node are ordered: first, second, third child, etc. For any ac- rent moves on a given floorplan Fig. (11). For the initial ceptable placement, B* tree inherits desirable properties floorplan B* tree selected in the CPU, several concurrent from the O tree but it overcomes the irregularity typical in O GPU threads are launched after copying the state from the trees and has a 1-1 correspondence with its compacted CPU, with each thread applying a separate move and concur- placement, where individual modules cannot move down or rently evaluating the objective function for the resulting left. This attributes certainty to the complexity involved with floorplan. The CPU then inspects the evaluations and accepts B* trees. one of the moves evaluated during the concurrent phase. The process repeats unless a stopping criteria is met, according to Typically, simulated annealing, i.e. a probabilistic opti- the general flow: mization is applied on the B* tree for floor-planning. The moves to explore the solution space are: (a) rotating a mod- Input: ule; (b) moving a module to a new location; and (c) swap- 1. A circuit with modules ping two modules Fig. (10). Starting with an initial floorplan,

IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 139

Fig. (12). Parallel floorplanning data flow between CPU and GPU.

objective results are copied back to the host memory. This floorplanner shows about 30% run time speedup compared to the sequential version of kernel execution based on four steps: 1. Copy: Device to shared memory 2. Move: B* tree 3. Objective evaluation 4. Write to device memory Interestingly, 97% of the total run time in GPU takes copying data from the device memory to shared memory and Fig. (11). Breaking the dependency chain in floor planning process 3% of time is spent for the computation to evaluate the by multiple concurrent moves. newly generated floorplan. Restructured tree data and access pattern give dramatic 2. A floorplan that optimizes the objective (area, wire- speedup, e.g. by 20x. Larger circuits would show greater length, pattern density distribution, etc.) speedup, as the data copy cost is better amortized by concur- rently computing costlier move operations. Begin In summary, this new methodology of IC floor planning 1. Read input circuit claims two major advantages: 2. Construct initial floorplan B* tree applicability to the most complex IC architectures, to 3. If stopping criteria not met, do: optimize the goal function (e.g., die area or routing length) 4. Copy tree and attributes to GPU device memory processing time reduction over the serial floorplanning 5. Launch B parallel thread blocks process, by 30%. 6. Copy tree and attributes to shared memory That latter advantage could still be enhanced by several times when improved data copying from CPU to GPU is 7. Select and perform move applied. 8. Modify tree (local copy in shared memory) 2.1.5. Slotting of Wide Metal Buses 9. Evaluate objective To prevent the damage caused by dishing of copper wires 10. Write objective in GPU device memory during the polishing process, copper pattern density is re- 11. Copy B objectives from GPU device memory to host quired to be within a range, e.g. 85%, checked every e.g. 50 memory μm of square area of an IC design. The maximal width of copper wire is also limited [6]. These limitations do not cre- 12. Pick best move ate significant layout challenge, as only a small subset of 13. Modify tree with best move interconnect lines in a design are critical for modeling as transmission lines (T-lines). 14. End while loop The width of an interconnect line (depending on the cur- Figure 12 shows the dataflow between the CPU (host) rent it should carry) determines the number of elongated and the GPU (device). The B* tree structure of a floorplan apertures (slots) to be arranged across it. If the wire Fig. (13) along with circuit related information (e.g., width, height) is wider than the maximum defined by the design rules, it are copied to the device memory. Subsequently, multiple has to be slotted. thread blocks copy the tree to their own shared memories. Different moves are explored in different thread blocks, and The algorithm Fig. (14) first defines the number of slots the objective function is evaluated and stored. Finally, the and determines if any bridges or shorts are needed in the

140 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

Fig. (13). Wide metal bus with slotting.

between the shorts should be less than a tenth of the shortest signal wavelength and the highest speed signal dictates the

spacing of approximately 50 μm. Slots should be large enough to keep OPC at minimum. Metal density in wide slotted wires should comply with pattern density rules, checked within windows of specified size. The slotting and tiling should preserve the capacitance and inductance effectively the same as for the one-piece copper line. The splitting of copper interconnect lines into connected fingers can be implemented as a parametric cell (Pcell). A layout instance with slots would emerge automatically, with proper symmetry with respect to conductor hole pattern distribution, making it a CBC solution.

The change in electrical parameters of a transmission line due to slotting is programmed into its parametric model for time and frequency domain simulations. The low frequency resistance model of a line with slots can be easily imple-

mented in transmission line models. The high frequency line parameters can be calculated due to the 2D nature of the described approach compared to the 3D nature of the “iso- tropic” hole-generation process. The “anisotropic” length is equal to an interconnect line length, unlike for the “iso- tropic” slotting where the effective current path is always greater than the interconnect length, causing an additional resistance. The finger shorting every predetermined length causes no periodic interference and has a negligible effect. In summary, while the proposed invention addresses an important aspect of IC design, one may expect that IC manu- facturers have readily implemented slotting solutions of their

own. A novelty here is the use of pCells as CBC solution, with parameters depending on the current flow. 2.1.6. Antenna Ratio Suppression Fig. (14). Flow chart of the proposed slotting method. One key aspect of DfM is Design for Reliability (DfR) [7] including Gate oxide integrity (GOI) response to plasma middle of the slots along the length of the interconnect line, process induced damage (PPID). Plasma damage depends on according to the technology rules. The optimum interval IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 141 the density of the charging current flowing through the gate insulating film due to the large area of the gate electrode that function as antennae. An IC layout should have antenna size no greater than a predetermined threshold (antenna criterion). The antenna ratio (AR) represents a ratio of an area of the signal wiring (the metallic wiring) connected to the gate relative to gate area in the transistor. When the antenna criterion is exceeded (i.e. creating an antenna error), the layout has to be corrected, e.g., by inserting a protective diode for bypassing the charge current that concentrates in the gate electrode. But when the area coverage ratio of standard cells is high and no free region in the die exists, the area of the circuit would have to increase to accommodate protecting diodes. If a protective diode is inserted inside the cell, it in- creases the input capacitance.

A preferred solution to reduce AR is to increase gate area by inserting a buffer [8]. However, since one has to do so in wiring, an arrangement of other cells and wiring lengths may have to change, causing a timing error. Fig. (15). Insertion of buffer cell for antenna ratio reduction. The proposed method of AR reduction requires computing gate area to be added to avoid PPID. The layout is modi- Since a primitive cell can be inserted as the fill to elimi- fied by arranging a logic cell with a second gate electrode, nate antenna error, it is not necessary to prepare a dedicated without contribution to the circuit logic, in a free region of cell (e.g., a diode). But one should prepare a bank of various the layout, and connecting the second gate electrode to the buffer logic cells to find one with a function of the circuit wiring [8]. Since the gate area is increased by insertion of a where the antenna error arises. cell that performs no logic operation, the antenna ratio can improve without altering other circuit cell arrangement and During layout correction, the algorithm searches the wiring. empty region on the chip nearest to the subsequent stage input gate, places the logic cell in an empty region, and con- In a circuit consisting of three logic cells Fig. (15) the nects the gate electrode within a shortest path. gate electrode in the first and the second cell, and the second gate in the third logic cell are connected together. The third In summary, the proposal addresses an important DfM logic cell makes no contribution to the logic. The gate area concept and can be useful to define chip-level CBC layout connected to the wiring that acts as an antenna in the plasma for high GOI and reliability. process is enlarged by the second gate electrode. Since the 2.1.7. Three Dimensional Packaging cell that performs no logic operations is placed in the empty region of the die, improving of the AR should not largely Another aspect of DfM by CBC is related to SoC device after the layout and the timing due to the layout correction applications requiring advances in die packaging [9]. A new should not change either. method of designing the package enables up to four semiconductor dice, with one or more internally connected switch The cell library includes information about the layout and nodes, in a package, e.g., to form a dual output or phase syn- performance of the logic cell (size, transistor count, gate chronous buck converter. The package may have control area, etc., Fig. (16). The design support system verifies the leads at opposite sides containing semiconductor dice ori- antenna ratio on the preceding stage logic cell (a second ented perpendicularly to one another Fig. (17). logic cell) and the subsequent stage logic cell (the first logic cell) connected together through metallic wiring. An equiva- Semiconductor die packages containing several devices lent circuit of the verification object circuit is the same. with similar connections (e.g., inputs or outputs) separated from each other require longer or more electrical connectors

Fig. (16). Cross-sectional view showing buffer cell connectivity. 142 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

Fig. (17). High – and low – side components of a 3D package. to the rest of the circuit. Output connections may be on opposite sides of a package, such that the circuit board to support the package would need to have circuit traces (e.g., pads) to be similarly separated making it difficult to design a circuit board. Figure 18 shows an inside view of a package without molding material and Fig. (19) shows its bottom perspective. The leadframe structure contains multiple die attach pads and leads. The first and the third control lead can be at the opposite sides allowing for four dice within the package, oriented perpendicularly to each other. The leads extend past the lateral edges of the housing. Depending of whether molding is used, a housing could simply be assembled around the dice and the leadframe structure. Vertical devices may include an input on one side and an output at the other side of the die so that current can flow vertically. The pinout (i.e., Fig. (18). Inside view of a 3D package. location of the leads) allows for easy layout of a dual output e.g., of phase synchronous buck converter or other suitable vertical or horizontal devices. A user can place power train components (inductors, capacitors, and transistors) to create dense power supplies, critical for reducing board area. The exposed die attach pads at the bottom of the package have good heat dissipation and electrical connectivity to exterior devices such as circuit boards.

The design enables PCB layouts to reduce parasitic loss due to routing of internally connected switch nodes with low inductance or other parasitic losses for the die package to be used at high operating frequencies.

In summary, package development is becoming an important aspect of DfM. Mechanical and electrical simulations are required to confirm the robustness of the build.

2.2. Execution: Layout Corrections Fig. (19). Bottom view of a 3D package. When CBC methods are not readily applied at cell or block level, post-layout modifications at die level may be required to make the design DfM-compliant, typically by The disclosures related to OPC discuss its cycletime reduction (a common DfM goal) by focusing on the regions in die post-processing algorithms such as OPC. Such post- requiring significant computing effort. OPC adjustment processing has to preserve both design intent and schedule. would need to resolve the tradeoff between the magnitude of

IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 143 edge placement errors (EPE) and device sensitivity. The pro- For conventional (sparse) OPC, chip layout is fragmented posed procedures take advantage of simple or redundant along the edges of features. Edge placement error (EPE) is geometries to expedite the solution. then measured against a simulated image and the layout edges are moved as needed to reduce these errors. Such 2.2.1. Pixel-Based OPC “sparse OPC” is often not capable of making corrections to OPC corrections are added to design data to compensate the accuracy target. for light refraction at the boundaries of small features on the A more recent approach referred to as “dense OPC”, de- photomasks, by adjusting their widths or lengths through fines a pixel size to analyze portions of the aerial image to corner serifs, line end extensions, etc. The OPC operation is determine the corrections, pixel by pixel. An OPC tool costly as it may take weeks for an entire device design to places a global grid over a design layout, calculates image converge to an OPC solution acceptable for all geometries in parameters for each pixel, and compares them to the target the layout. The new methodology is focused on optimizing image to determine the correction. A small pixel, e.g. 20 nm OPC processing time and accuracy [10]. x 20 nm, is required to achieve high accuracy, but at exten- In contrast to a regular mesh used for the prior, time- sive run times Fig. (22). consuming method of determining OPC Fig. (20) the new method uses mesh with different pixel sizes, with smaller pixels in more sensitive areas after empty regions are found by the scanning operation at a larger pixel size. When a feature is detected, the pixel size is reduced for calculations Fig. (21).

Fig. (22). Flow chart of OPC process using different pixels.

Receive Design

To Analyze

Fig. (20). OPC – standard method of creating a layout mesh.

Cluster Polygons In Design

Identify Pattern Repetition

Perform Operations Or Analysis On

Unique Patterns

Apply Operations

Or Analysis On Replicated Patterns

Fig. (21). Proposed OPC method with different pixel sizes. Fig. (23). Extraction of polygons for cluster OPC definition. 144 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

In the approach, proposed in [10] portions of the calculated aerial image are compared to the target image for each 1 2 pixel, to determine the correction. Then, the layout of the 3 calculated aerial images is divided into an array of large pixels, e.g. 100 to 200 nm, and scanned by an OPC tool to determine whether a portion of a pattern resides within each pixel. If pattern is found, then that pixel location is stored in 4 the memory of the OPC tool. Then, the algorithm defines 5 6 smaller pixels close to the edges of the patterns and performs detailed calculations. If accuracy is required, pixels may be divided into smaller ones, e.g. quarters or ninths. Small pixels close to the edges and corners of features and larger pix- 7 els in areas with no features present require less time for 8 9 calculations. In summary, a grid of small pixels in areas requiring high accuracy and large pixels in stable and homogeneous imag- ing areas should reduce OPC runtime. This approach is conceptually similar to mesh definition for mechanical or electrical simulation programs. Fig. (24). Examples of polygon clusters. 2.2.2. Cluster-Based OPC In summary, parallel analysis of similar layout elements As complexity of IC layout becomes too high for effi- for process corrections should shorten layout optimization. cient analysis of elements not interacting with each other, One may note that even multiple day runtimes, are still only clusters of elements instead of individual geometries can be a fraction of the overall design cycle. As long as they are extracted and then handled separately. A set of polygons predictable, they would not absorb design resources. forms a cluster if for any two polygons, the distance between them is less than or equal to a given threshold number. The value of the approach may be compromised by the Rather than analyzing each and every polygon in the design, complexity of the code leading to the high cost of debugging, unique but repetitive patterns are analyzed once and then compared with the few days of runtime reduction per design, replicated for all clusters with the same general pattern [11]. which can also be accomplished by a more powerful computation engine. An alternative is to use cells from a standard In a cluster, OPC algorithms search for polygons with a library, pre-processed for layout corrections. segment or a wall not near enough another polygon Fig. (23). Light refraction in such region could result in a curved line 2.2.3. Resolving OPC Conflicts segment on the wafer, which needs to be corrected to the During rule – or model-based OPC implementation, con- acceptable EPE value. As mitigation, a scattering bar, i.e., a flicts may arise between edge corrections and mask manu- geometry below the resolution limit of the lithography facturing rules for minimum width, spacing, or notch reduc- equipment, may be added – space permitting – parallel to the tion. One way to resolve these conflicts is by assigning edge segment of interest to produce a straighter line. Given the correction priority [12]. Because a suboptimal wafer pattern large numbers of components in a typical IC design, it takes may not be identified by the OPC algorithm, a dedicated time and resources to perform a full set of scatter bar analy- system may need to alert a user about it. As response, the sis. Therefore, a cluster – based approach is a time-saving user may change the layout or relax the system constraint for measure. the critical corrections. The algorithm recognizes all clusters in a given layer and OPC tool assigns priority to edge segments of a feature to forms a list of classes of equivalent clusters with repetitive be corrected such that movement of a less important edge patterns. Adding scattering bars is done for each polygon does not hinder the correction of a more important one Fig. individually. The next action is pattern recognition to iden- (25). In order to print properly on wafer, the OPC tool may tify the set of repeatable, unique patterns. For clusters 1-9 suggest for a portion of a feature (stippled area) that its from the example set, there are three unique patterns: A, B, boundaries be extended outwards (dashed area). An edge C. To replicate the processing for each instantiation of these segment of the feature is to be moved to avoid a conflict with patterns, the set of scattering bar for Pattern A is repeated for an edge segment that forms a jog. But if the OPC tool moves clusters 1, 3, 4, and 6, etc. Fig. (24). the edge segment further outwards, the distance between that The distance between clusters is modifiable to optimize segment and the jog violates an MRC rule. The designer the clustering. If the distance is too large, there would be should like to see the edge segment assigned a less than de- only a small number of clusters, each of them potentially sired OPC correction and either re-fragment the area around having a large number of polygons, if it is too small, then the concave corner such that the distance between the final there may be a large number of clusters, with only few poly- OPC corrected positions is greater than the minimum MRC, gons each. The process can be configured to iterate with dif- or relax the MRC in order to permit the correction, at the ferent cluster spacings, e.g., 3 to 4 times the value of the expense of a mask of higher accuracy. The system keeps minimum spacing design rule. track of which edges can not be moved to their desired OPC corrected position without causing a conflict. IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 145

Fig. (26). Pattern bridging in an SRAM cell. Fig. (25). Examples of edge shift conflicts for OPC corrections.

Edge segments can be categorized based on their func- tional location in the layout or on their MRC constraint information, e.g. as being part of a gate, a line end, a signal wire, etc. That way, critical portions of layout are corrected first. In summary, this disclosure intends to resolve conflicts between the complex OPC algorithms and mask manufacturability requirements. While tagging feature edges by a recognition system makes sense, involving layout designer at chip level post-processing may be a difficult proposition. If the conflict resolution algorithm is allowed to work at IP block level, decisions can be made more easily assuming that the designer is aware of the lithography parameters. Pushing the responsibility to find optimal OPC from the tool back to the designer may trigger arbitrary decisions a designer would have to make.

It is difficult to extrapolate directions of OPC development based on patent activity. The discussed OPC concepts do not necessarily reflect the actual process roadmaps for the Fig. (27). Main and auxiliary mask pattern to control line end ex- inventor companies. But judging by the types of disclosures tensions. discussed here, one may conclude that the standard OPC approach with refinements aimed at complexity reduction and time savings are still of interest for technologies well An overlapping exposing process may not need to use an below 45 mm. additional mask plate, but instead a different mask pattern on the same mask, to easier align mask patterns. 2.2.4. Auxiliary OPC Patterns An example mask may contain a pattern including light- Improving pattern resolution can be achieved by fine blocking features and fine auxiliary patterns within a light- auxiliary features patterns within a light-transmitting region. transmitting region, and a another pattern, adjacent to it, with Overlapping a mask with the opposite tone over the desired light-transmitting fine auxiliary patterns within a light- pattern located next to it helps remove pattern bridging re- blocking region, to facilitate an overlapping exposing proc- gions [13]. ess. The second mask pattern may have the opposite tone of Figure 26 shows pattern bridge problems in line end por- the first mask pattern. The light-blocking and the light- tions of an SRAM cell. Figure 27 shows the auxiliary mask transmitting fine auxiliary patterns would be aligned at the pattern, placed in order to extend the end portions of the same positions during an overlapping mask exposing proc- lines, i.e. an example mask proposed in this invention. Since ess. the occurrence of pattern bridges at the line and region are In summary, dividing a mask into a first and a second particularly problematic, fine auxiliary patterns are not in- region, containing respectively main design and fine auxil- serted there. If a fine pattern having a line width less than the iary patterns with opposite field tones can help improve obtained resolution is independently applied to a mask, a process margin for small gap printing. However, this process pattern where light physically passes only though the mask scheme would not fit well within the current state-of-the-art but does not appear in the photoresist material can be de- manufacturing, due to: fined. 146 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

the need to use double – patterning which can accomplish much more optimized pattern features, than the

ones discussed here,

placing clear – and opaque – field patterns next to each other which would compromise mask CD targeting reducing the usable printing field size by at least 2 times, due to the two adjacent patterns. It is possible that the concept of printing sub-resolution features using a separate mask layer would become of interest, but it would be likely in an implementation significantly different from the proposed one. 2.2.5. Process Compensation in IP Libraries Pattern transfer from design to wafer is never accurate. Cell layout can be optimized with process bias compensation techniques (PCT) across the hierarchy, from leaf cell, through block, to die level, through optical proximity correction (OPC), resolution enhancement techniques (RET), etch proximity, gap fill, pattern density adjustments for chemical mechanical planarization (CMP) etc. Circuit extraction should be performed on aerial images of the PCT version before placing and routing of the layout [14]. Aerial images of the cells subject to PCT based extraction would be added to the library of attributes. At timing closure, extraction tools would combine layout information based on idealized polygon shapes with a wafer fab technology data to add parasitic components to the circuit schematic. Since the as-fabricated features on the wafer do not exactly match the polygon shapes of the layout, the accuracy of geometry dependent parasitics (resistances and capacitances) would need to be improved. Fig. (28). Defining litho buffers by duplicating the main cell. Process compensation at cell level is easier compared to full chip level. Figure 28 shows cell area surrounded by a litho-buffer with an area that could impact its printability. The outward extent of this buffer indicated by arrows could be about 1 micrometer out from each side of the cell. If the difference between the contour in the aerial image simulation (i.e., the EPE) and the drawn layout of the cell prior to PCT processing are too large, further refinement of PCT is required. If the EPE’s are acceptable, the method stores the final PCT version of the cell and its aerial image to the library.

Figure 29 shows layout of transistors with gate electrodes that extend over an active region with aerial images not matching the polygon representation. This causes MOSFET characteristics to vary along the length of the gate electrodes. For accurate modeling, each transistor can be sliced into segments along the length of its gate, such that each segment is modeled separately [7]. The current disclosure includes Fig. (29). Corner rounding and line end pullback of poly gates. extraction methodology into IC design the hierarchical analysis. 2.2.6. A DfM Flowchart In summary, while agreeing with the concept and as- One role of DfM is to enhance interactions and commu- sumptions of the proposed disclosure, it is difficult to evalu- nication between designer and manufacturer. Manufacturing ate its RoI without reducing it to practice. Cell level PCT data are formulated, quantified, and integrated to reduce de- may be readily built into many simulation engines. The po- sign time and cost. An IC manufacturer needs to provide tential savings would depend on the type of the circuitry and multiple qualified processes. EDA tool vendors, intellectual required accuracy. property library vendors, and customers may involuntarily duplicate the effort without sharing resources, potentially providing inconsistent results [15]. IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 147

Figure 30 is a block diagram illustrating an integrated system including its structure and method to implement DfM EDA Tool Vendors Foundry Customers among semiconductor manufacturing, design tool vendor Tool vendor(s) submit tool to Foundry set unified qualification Qualification foundry and acquire qualification criteria partners, Intellectual property library (IPLib) partners, and process status customers Fig. (31). Figure 32 is a flowchart to implement a Foundry license tool vendors to Foundry qualify EDA tool vendors joint motoring program (JPM) for centralizing qualification use DUF format data and grant compliances to vendor and unifying qualification criteria of design tools utilizing Tool change, tool vendor notify for Data change, foundry notify for partnership, between a manufacturer a design tool vendor, tool change tool change and IPLib partnership between a manufacturer and an IPLib Joint Two parties join and perform impact Monitoring quality due to the change partner. Program (JMP) Feedback to unified No impact on tool/ Tool/Data qualification criteria data Change impact based on tool/data change DFM data kit Impact on tool/data Take action for tool / data impact LPC

CMP DFM utilities Fig. (32). Flowchart to implement JMP.

CAA LPE

Checker DFM advisories Enhancer Required rules

Dummy insertion Recommended rules Guidelines

Fig. (30). Integrated DfM system.

Statistical Logic/Circuit Design SPICE Model

CAA Analysis Physical Implementation & Improvement Fig. (33). Derivation of lithography and etch models: a) lumped

model, b) retarget model, c) staged model.

Dummy Utility & Layout Enhancer

Correction LPC & CMP Guidelines Hot Spot Check

Verification (DRC, LVS, RCX & DFM LPE)

Fig. (31). Flowchart to implement integrated DfM system.

DFM unified format (DUF) categories are to help share manufacturing / DfM data among design tool vendors, manufacturer, and customers.

A DFM tool kit and a DFM data kit (DDK) contain manufacturing data, such as processing recipes, production statistical information, etc., are compiled, and accumulated, into the DDK for manufacturing simulation. DDK can be provided to an IC designer readily integrated into a design tool, or distributed directly with DFM rules and advisories i.e. guidelines for the designer to follow in implementing a procedure) extracted from the manufacturing information. Fig. (34). Etch bias as a function of line width and spacing.

148 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

Fig. (35). Flow charts of a modified staged and b) retarget model fitting for etch – aware OPC.

Fig. (37). Mismatch pattern determination and verification for in- terconnection layers.

license DFM modules to IPLib vendors to be built into an IPLib package. Thus the design tools and IPLib are integrated for DFM enhanced design. A joint motoring program Fig. (36). OPC calibration with modified retarget model. (JPM) Fig. (38) unifies qualification criteria of design tools and partnership between a manufacturer and a design tool In an enhanced design flow, DFM provides model-based vendor. The design tool vendor submits a tool generated with utilities from simulations and rule-based utilities from advi- criteria to the manufacturer for qualification, the manufac- sories. LPE deck may be implemented at extraction or at turer qualifies the tool and the tool vendor may grant com- timing simulation, before or after the tape-out, to eliminate pliances and licenses to utilize DfM information in the uni- hotspots before fabricating a mask. After logic design with fied format. The manufacturer may change the manufactur- input of a statistical design model (SPICE), the flow pro- ing data and notify the design tool vendor, to change tool ceeds to physical design implementation with interaction to configuration, database, etc. CAA analysis, layout enhancer, dummy insertion, layout tuning, LPC and CMP hotspot check, and then to design In the process of centralizing and unifying qualification verification: design rule check (DRC), logic vs. schematic criteria between a manufacturer and an IPLib partner, the (LVS), resistance and capacitance extraction (RCX), and manufacturer defines DFM compliance criteria for an IPLib DFM LPE. vendor, who provides evidence of compliance to review to the manufacturer, design tool vendors, and customers A design system requires various interactions among design entities. An IC manufacturer can license DFM mod- In summary, DUF as one unified format to present manu- ules integrated with data in DFM unified format (DUF) to IC facturing data among design tool vendors, manufacturer, and design vendors to be built into an EDA design tool for en- customers for DFM associated integrated circuit (IC) design, hanced functionality. Similarly, the IC manufacturer may may include at least three categorized data structures: lithography process control, chemical mechanical polishing, and

IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 149

model properties. However, the rule table based on previous measurement data is required for the retargeting

and therefore the OPC model accuracy is limited by the previously measured pattern structure. c. For the staged model, the lithography and etch are modeled separately. The staged model is an unfitted lithography model, calibrated by post-litho data. The etch model is calibrated with both post-etch data and output of fitted lithography model. Unfortunately, staged models calibrate the lithography independently from the etch. Because the post-litho measurement data can be noisy and the lithography model output is an input to the etch model, the staged model accuracy is limited by the accuracy of the lithography model. Fig. (38). Characteristic influence as function of distance. Figure 34 illustrates the etch bias and the inverse of the critical area analysis. The unified DFM data may be plugged etch bias depending on line width and spacing. If we denote into a manufacturer certified DFM design tool to validate the post-litho measured data as “ADI_wafer” (after- DFM associated design process. This methodology may be- photoresist-development inspection, ADI) and the post-etch come important for DfM standardization. measured data as “AEI_wafer”, (after-etch inspection AEI), the etch bias can be expressed as: bias = AEI_wafer – ADI_wafer 2.3. DFM Verification: Defect Reduction Calibrating the lithography model should cause ADI_ The final opportunity of DfM implementation is defect model to match ADI_wafer for a minimized model residue. reduction, when the expected level of CBC and quality proc- However, when ADI_wafer cannot be accurately measured, ess execution cannot be accomplished. Defects are identified this calibration does not produce an accurate lithography by thorough modeling and sensing of process variations. model by simply fitting ADI_model to ADI_wafer. 2.3.1. Etch Process Model In Figure 34, each curve represents the etch bias (Y-axis) Only a few semiconductor process steps have mathemati- at a constant line-width as a function of line-spacing (X- cal models. One critical missing link affecting pattern print- axis). Etch bias, which should be determined where the resi- ability is the gap between the photolithography and the etch due is computed, also depending on trench width, trench process. Conventional, staged OPC model is enhanced by a density, polygon width, and pattern density, displays an in- rule table for correcting CD’s based on data from photo- creasing trend with respect to an increasing line-spacing and lithography and etching [16]. Large variations in feature to a decreasing line-width. sizes can lead to micro-loading and aperture effects which The coefficients can be determined by fitting the set of should be captured in OPC model. A key inaccuracy arises functions with measured etch bias. In order to trace the li- from modeling of the non-uniform and non-linear etch bias thography behavior and maintain the accuracy of the model, i.e., the difference between a resist contour after the photo- one may fit the residue to the reversed etch bias with a mean lithography and an etch contour after the etch. The new con- value substantially equal to zero. For example, if the first cept calibrates a model for the photolithography followed by line-width corresponds to an inverse bias between (-20 nm, - the etch with an etch bias model for critical dimension (CD) 40 nm), the system can choose the constant to be 30 nm, so difference between the values measured separately after that the shifted fitting target for the first line-width is be- these two steps [16]. tween (-10 nm, 10 nm). Three techniques are used to include the etch effects into Figure 35 shows fitting of a modified staged model, calibration of an OPC model: the lumped model, the retarget where a lithography model receives both post-litho measured model, and the staged model Fig. (33). data and an etch-bias-based fitting target as inputs. During a. For the lumped model, post-etch data should directly fit the calibration, the system fits lithography model so that its a lithography model, based on the optical and resist residue is equal to etch-bias-based fitting target. The flow components. Unfortunately, the lumped model ignores chart for the fitting of the retarget model is shown for com- the intermediate measurement after the photoresist de- parison. The calibration flow Fig. (36) may be configured to velopment, which loses the lithography process window receive an output of the photolithography process model and information. post-etch CD data. b. For the retarget model, both the layout and the post-etch In summary, the proposed concept goes a long way to data are biased by the values stored in a rule table to ac- build in the etch process into the overall model of pattern count for the etch effects. The modified data, i.e., biased transfer from design to wafer. For the upcoming technology post-etch data and layout biased to compensate for etch generations, the accuracy of the aggregate model would be effects are then used to fit a lithography model. The of increasing importance. One may recommend algorithmic retarget model has the advantages of using one stage coverage of the proposed process, by adding user interfaces correction flow while maintaining the lithographic to EDA tools. 150 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

2.3.2. Mismatch Evaluation Layout matching is required for analog circuitry [17]. Figure 37 shows verification flow based on the coordinates of paired element to identify desired geometries for pattern comparison to determine a mismatch depending on the con- textual differences. Layout verification (e.g., by an exclusive OR operation) can detect whether there is a match between paired elements and their surrounding patterns, by calculating a distance between these elements and at least one mismatched pattern in the surrounding regions. This is followed by determining which of the surrounding regions contain the mismatched pattern and calculating a distance between the paired element and the mismatched pattern as the shortest of the X-axis and Y-axis Manhattan distances or a radial distance. The process to verify whether the length of characteristic influence is acceptable consists of:

Determining mismatched patterns, Fig. (39). Process variation sensing devices: a) circuit, b) simula- Dividing verification region, tion data.

Calculating mismatched pattern distance and area, Layout modification.

When characteristic influences cancel each other, layout modification is not required Fig. (38). In summary, the method improves long-range layout or- dering, critical for both IC manufacturing and device applications.

2.3.3. Process Variation On-Chip Sensor

As IC scaling down continues, the impact of process variations (PV) on circuit performance and robustness is increasingly more negative. It is critical to design circuits and systems robust to fluctuations in process outputs. Proc- ess variation sensors and techniques identify both global and local variations associated with transistors on an integrated circuit. The first step in designing such circuits is to provide calibration data to compensate variations, and provide feed- Fig. (40). Example of topography of a processed wafer surface. Y – back on what is going wrong during manufacturing [18]. axis in μm.

Sensing process variations can be accomplished by using transistor changes, the resistances of PMOS and NMOS leakage current due to its high sensitivity. The pre-existing transistors change at a different rate due to the difference in sensor circuits suffer from low gain and area overhead. Ring DIBL coefficients (Drain Induced Barrier Lowering). The oscillators (RO) as process variation sensors occupy too value of Vb changes with the threshold voltage, due to the much area to place in large number for better resolution. difference in DIBL. Since the impact of process variations is averaged out through the inverter chain in ROs, local process variations Due to decreasing channel lengths, of random doping in can not be detected. the channel affects the threshold voltage of even two neigh- boring transistors. The circuit topology for sensing local A circuit proposed to sense global process variations Fig. variations in NMOS transistors is the same as in for the (39) uses transistors operating in the subthreshold region for global variations, except that the transistors are sized differ- high sensitivity to process variations and low power dissipa- ently to sense the differences in threshold voltages of parallel tion. There is no need for external circuits since all transis- transistors placed closely to each other. The sizes are kept at tors are directly connected to ground and supply voltage. The a minimum to magnify random doping fluctuations. The devices in subthreshold region can sense both global and other transistors are relatively large to reduce the effect of local variations, respectively due to systematic variations and process variations. This design guarantees that we are sens- random dopant fluctuations. The variations can be modeled ing only the difference between two parallel transistors since as threshold voltage shifts. all the rest of the circuit is common for all measurements. Under subthreshold conditions, transistors act like resis- The individual transistors in the array are connected to tors in series and substrate bias, Vb is determined after volt- the load and amplification circuit through a hierarchical age division between them. As the threshold voltage of each switch network. Sensitivity to process variation is improved by varying sensor parameters. IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 151

2.3.4. Planarity – related Hot Spots Predicting problematic layout areas for lithography requires modeling of surface heights on the wafer to determine distance from wafer surface to focal best planes of exposure focus [19]. A three dimensional sur- plane along axis of illumination face height map of a chip generated from a lithography tool data prior to exposure of an upper metal level Fig. (43) shows peaks (surface irregularity) i.e., potential bad focus areas depending on the focal planes used by the lithography tool (scanner). Lithography tools either measure surface topography in real time (during the scan) or pre-measure the entire wafer surface at the “idle” stage first, followed by choosing best average focal plane to expose. That plane can be moved up down and rotated, to achieve the best average focus at any particular instant, adjusted as the slit scans. Figure 40 shows two dimensional surface profiles in the direction over the large surface “peak” in Fig. (41) that the lithography tool might choose as the best average focal plane. The areas of the photoresist closest to the best average focal plane will be in better focus than others. The surface topography can also be modeled by chemical mechanical polishing (CMP) simulation, which takes into account the details of the pattern. The surface height is the weighted av- Fig. (41). 2-D wafer planarity profile. erage of the copper and dielectric height mapped by square regions of a specific size (tiles). Still, modeling cannot accurately predict all areas problematic for lithography, by look- ing for high or low points within the CMP modeling surface, without taking into consideration the way in which the lithography tool decides the focal planes to use. The points, which have the same height above reference plane might be considered to be “high” along the surface profile, at risk of bad focus. But because of the way that the lithography tool must select the best average focal plane, one point would be exposed with better focus than another. Therefore, surface height alone is not an indicator of quality.

The invention described in [19] proposes a method of predicting problematic areas for lithography based on surface heights of tiles of a wafer using modeling of a lithographic tool and determine best planes of focus. The average distance of the surface heights for each tile is a 3D representation of the surface at a location on the modeled wafer. The method predicts that distance calculating a predetermined number of focal planes for each tile in a reticle field to ensure an equal percentage of exposure dose for the entire reticle. The focal planes are used to measure surface irregularity in three dimensions and to find an average focus offset, by calculating an average distance along an axis of illumination from a best average focal plane. A plane which best fits Fig. (42). Surface model of a wafer using standard CMP modeling CMP modeling surface height data has to be calculated for a tool. predetermined number of values within a slit Fig. (42). Fig- ure 43 is a flow diagram of the proposed process to predict offset by calculating the average distance from the planes to areas of poor focus (hot spot) the way in which a stepper the wafer surface. decides the planes of best focus based on the surface heights of the wafer. For example, the tool calculated 10 focal planes In summary, the analysis of exposure field for wafer to- for each tile in the reticle. Each point (focal plane) would pography may become an important step to ensure high fi- provide 10%, of the exposure dose for the tile. These focal delity of pattern transfer of design to wafer, especially for the planes are a reflection of a three dimensional surface texture. short wavelength of the EUV. The proposed methodology Once each plane of exposure for each desired point in the helps reducing the risk related to wafer planarity and it reticle field is calculated, the tool finds an average focus should be of interest to see results of experimental studies in this area, especially for designs using multiple patterning. 152 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski

As an option, an interposer structure may be placed between the first and the second 2D device, to include inter-

connects that route signals from contacts from the first to the second circuit. If interface data includes the interposer, routing analysis can verify that the interposer properly routes the signals.

Figure 44 shows a flowchart of verifying interface design data. Data for first and second device are provided to the data identification unit, to identify their interface portions as the ones closest to the other device, combine them for physical verification and perform a routing analysis (layout- versus-schematic).

Fig. (43). Flow diagram of the proposed process of hot spot identification.

2.3.5. Verification of 3D Devices

A two-dimensional integrated circuit aimed to be a part of a stacked device is typically formed by a standard IC process and has metal lines on one side of a substrate (“front”). If a two-dimensional IC is to be stacked on top of another IC, it requires metal layers on the opposite side of the substrate (“back” side), connected to the circuit and metal layers on the front side by the vias that pass through the substrate (“through-silicon vias”, TSVs). There are three basic techniques for manufacturing a stacked IC: wafer to wafer stacking, die to wafer stacking, and die to die stacking. Fig. (44). Flowchart of interface cell verification for stacked cir- But the EDA verification routines for stacked IC’s are still cuits. under development [20]. In summary, the process flow of combining design data One technique for verifying a stacked IP is to combine all from two or more die IP’s to take advantage of the TSV designs of the component devices together for a multichip process is critical for the extension of silicon technology into physical verification (PV). However, this complicates the three dimensions. The question is, is the proposed concept verification process of TSV designs. Conceptually simple, generic enough for different types of devices to help create such “mega merge” PV may alter the integrity of the initial common 3D PV standards. design and “golden” verification rule file. When merging all two-dimensional IC databases into a single three- 2.3.6. Table-Based DFM dimensional design, “shifting” of all the design layers and Performance data is related to device geometries by a PV rule decks, must be done to incorporate them without shape model linking equivalent dimensions to the electrical collision. For a stacked device, interface layers between two performance. One can create a data refinement table using two-dimensional circuits that will be electrically connected is the equivalent dimensions and electrical performance [21]. first identified. These layers are then combined and physi- DFM uses equation-based solutions for layout parasitic ex- cally verified as a single set of design data. Once the inter- traction (LPE) to predict device behavior on chip. The equa- face, the first, and the second IC design data have been tions are obtained by best fitting to the limited silicon data physically verified, the design can be recombined to form friom the test patterns. But electrical drift induced by process verified data of stacked device. variation cannot be separated and accurately predicted by an equation. The equation-based approach cannot handle abrupt IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 153 layout transitions without costly high-order approximation and the risk of introducing singular points.

The proposed method helps estimate electrical performance of nonrectangular MOSFETs using a table-based post- layout analysis to investigate their manufacturability during patterning processes. For the distorted layout areas, such as rounding comers of the real contour, the table-based strategy provides a cost-effective and more accurate approach to predict electrical behavior. Figure 45 shows a table-based IC DfM flow and Fig. (46) is a top view of an exemplary IC device. In addition to “W” and “L”, the device with the rounding H – shaped active region can be described by various heights “h1”, “h2”, “h3”, and “h4”, and spaces “s1”, “s2”, “s3”, and “s4”.

Fig. (46). Top view of a device subject to table-based analysis.

data, the dimensional parameters, and the shape related

model, in multiple dimensions. It can be used for post layout analysis including tuning the design layout and identifying the hot spots. In summary, the table-based approach is aimed at adding another level of corrections over the model-based DfM approach. It may be logistically difficult to maintain for a variety of devices. 3. CURRENT & FUTURE DEVELOPMENTS As evidenced by the variety of the discussed disclosures, DfM continues to be a discipline of growing complexity. Its domain already expands past the fields of design, layout,

process integration, yield management, optics and lithography, and product definition into the floorplanning and packaging. Its further development looks unavoidable due to the emerging IC applications including Systems-on-Chip. Com- Fig. (45). Table based DfM flow. pared to the status from several years ago, DfM started to meaningfully improve the design or layout via tool optimiza- A set of IC devices are designed first with different di- tion as well as by employing best practices to arrive at the mensional parameters. The geometry and electrical perform- results well beyond the original RoI expectations. With many ance of the IC device can be described by two sets of the different designs and companies adhering to the different dimensional parameters. Silicon data enables extracting standards, foundry design rules and DfM recommendations equivalent dimensions of the devices. First, an IC contour is should continue to be conservative, also because, as stated in generated based on the layout and the channel regions are the Introduction, DfM is an art of compromise. Fabless com- defined as overlapping areas of the active and the gate elec- panies seem to own the DfM challenge by providing design- trode contours. Then, an effective rectangle from the layout ers with actionable information, how to build standard cells, contour is generated, to be simulated for the electrical per- custom IP blocks, memories, etc., so that they can minimize formance by a SPICE tool. A maximum rectangle inside the the impact of the most critical defects, as defined by foun- layout contour is defined followed by the width and the dries' design rule decks. length correction to that rectangle. One reason for which the implementation of DfM re- The method proceeds to relating the dimensional parame- quires careful RoI considerations is the lack of tools and in- ters to the electrical performance of the device, depending on tegrated approach. Restricted or local CBC solutions can the equivalent width “We” and length “Le” of the channel simplify DfM by addressing selected yield loss areas. But instead of the design width W or design length L. The shape they also hide DfM complexity instead of managing it and related model can be generated using a mathematical ap- may be too rigid to play well with other DfM optimizations. proximation such as multiple regression, response surface The real answer is to give the IC designer a complete, inte- approximation, etc. grated solution. The method proceeds to generating a data refinement Future work should continue to focus on developing tools table to improve electrical performance using the collected for an integrated and automated DfM approach ensuring cost and complexity reduction combined with improved perform- 154 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 Artur Balasinski ance. Point solutions pertaining to floorplan, OPC, or pack- [6] R. Gordin, D. Goren, S.E. Strang, K.A. Tallman, Y.V. Tretiakov, age optimization may be attractive for the short term but IC “Layout Determining for Wide Wire On-Chip Interconnect Lines”, U.S. Patent Application 0179392, July 21, 2011. design and manufacturing are mature enough to depend on [7] A. Balasinski, Semiconductors: Integrated Circuit Design for systematic feedback rather than being developed in isolation Manufacturability. CRC Press, Taylor and Francis, 2011. from each other. Every aspect of manufacturing flow has [8] K. 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