134 Recent Patents on Electrical & Electronic Engineering 2012, 5, 134-154 Optimizing IC Design for Manufacturability - 2011 Update Artur Balasinski* Cypress Semiconductor Received: December 17, 2011; Revised: April 10, 2012; Accepted: April 25, 2012 Abstract: Integrating Circuit Design for Manufacturability (IC DfM) involves various methodologies, techniques, and tools to improve semiconductor reliability and fab yield metrics by optimizing device design or layout. Recent years have seen propagation of IC DfM into the multiple aspects of semiconductor product definition. In addition to the traditional, mainstream DfM related to the corrections of circuit layout by the different types of pattern resolution enhancement tech- niques, recent DfM disclosures related to stacked die verification, 3D die packaging, floorplanning, and wiring have been proposed to help with the growing number of IC applications. These extended categories of DfM would be useful espe- cially for Systems-on-Chip as well as for the further pursuit of IC shrinkability, e.g. by double patterning. In this work, we discuss nineteen representative IC DfM disclosures filed or published in 2011 and 2012. Similarly, as in the previous re- view [1], we divided the patents into the ones pertaining to DfM definition, DfM execution, and DfM verification. The fo- cus of the first group of patents (definition) was the correct-by-construction (CBC) architecture, e.g., of layout (active de- vices, metal routing), die floorplan, or package. The second group (execution) pertained to process proximity correction (mostly OPC), and the third group (verification) concentrated on process model calibration and identifying the sources of process variability. These directions of DfM development, consistent over the recent years, show the validity of the exist- ing DfM approach to solve future design problems. Keywords: DfM, die packaging, floor planning, integrated circuit design, layout, OPC, process compensation. 1. INTRODUCTION hand, delaying new product design in order to comply with DfM principles is undesired. Therefore, implementing good Design for Manufacturability (DfM) has long been con- DfM ideas as early in product definition as possible would sidered a key methodology to improve semiconductor inte- not only help reduce delays but also improve cost efficiency. grated circuit (IC) manufacturing or reliability yield by op- timizing its design, or more frequently, layout [1]. Recent Depending on the stage of their introduction in the design patents filed or issued throughout the years 2011-2012 ex- cycle we had proposed before to divide DfM patent portfolio pand the DfM concepts related to layout enhancements and into three groups Definition, Execution, and Verification Fig. add disciplines serving new IC product applications. (1) [1]. At the earliest, Definition stage, DfM precedes IC design rules and guidelines, as correct-by-construction DfM is an art of balance based on the knowledge from (CBC) layout or product architecture, from single cell [2, 3], multiple engineering areas, such as electrical, optical, and to die [4-8] and to package level [9]. At the intermediate, mechanical engineering, striving to accomplish production Execution stage, DfM aligns with design or mask data verifi- goals such as high die yield, attractive product performance, cation for the IC layout, with emphasis on process proximity and zero reliability fallouts at low cost. It is at the discretion correction (OPC, PPC) [10-15]. Finally, at the latest, Verifi- of the design and manufacturing engineering, which of the cation stage, DfM patents improve manufacturing feedback techniques belong or do not belong to DfM. In this work, the to design/layout, [16-21]. Accordingly, the 19 examples of author stipulates that the new inventions in DfM apply not recent patent applications and publications discussed in this only to the layout, manufacturing or device parameters, but paper cover the following subjects: expand into the areas of floorplanning and packaging. For many patents, it may be difficult to quantify the im- A. Definition – CBC (cell to package level): portance of the improvements. Typically, there is no return on investment (RoI) discussed in patent publications, which 1. Dialed – in layout shrinking [2] leaves it to the reader to judge the value of the inventions. 2. Double patterning with hard mask [3] On the one hand, the difference between poor and good DfM 3. Spacer – based devices [4] can translate into schedule shifts of a new product yield ramp, which, when multiplied by multi-million dollar quar- 4. Advanced die floorplanning [5] terly revenues, could justify the cost of DfM development 5. Slotting of wide metal buses [6] including software tool licenses and manpower. On the other 6. Antenna ratio suppression [8] *Address correspondence to this author at the Cypress Semiconductor, 7. Three-dimensional packaging [9] 12230 World Trade Dr., San Diego, CA 92128, USA; Tel: 858 613 5532; Fax: 858 676 6896; E-mail [email protected] 2213-1132/12 $100.00+.00 © 2012 Bentham Science Publishers IC DfM: From 2D to 3D Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No. 2 135 els of DRC rules. A very robust CBC design needs only a Definition Execution Verification basic, geometric DRC deck of width and space to prevent printability violations. A layout not adhering to DfM rules Cell CBC End will require a more restrictive rule system to address pattern Level distortions. A fully random layout calls for a restrictive DRC to help with layout matching or fab transferability. These Design Multi-cell PV Start levels of robustness should be considered for the disclosures Intent IP Clean? presented below, related to a dialed – in layout shrink, p-Cell based metal slotting, or suppressing antenna effects. Other Design Drawn Hot Rules Die database Spots new concepts involving CBC such as floorplanning or 3D devices, may require establishing new design rule systems for System-on-Chip (SoC) products. Masks Cost Models reduction 2.1.1. Layout Shrinking by ePatterning Fab Mfg data One fast path to CBC layout is by applying a shrink to a known good design IP, to convert a product from the less to the more advanced technology node [2]. Geometric DRC for IP Protection the target process should suffice to ensure that the scaled down but robust layout would perform out of the box with- Fig. (1). Three domains of DfM and their implementation in design out model redevelopment and resimulations. But the ques- cycle [1]. tion is, how much effort is saved by shrinking the layout vs. designing it from scratch and what opportunities are lost by B. Execution – Validation (cell to die level): skipping the relayout phase which may allow for product 8. Pixel-based OPC [10] optimization. 9. Cluster-based OPC [11] To make sure that the shrunk design is comprehensively checked, the design libraries need to be extended to include 10. Resolving OPC conflicts [12] tables and formulae which the authors call electrical pattern- 11. Auxiliary OPC patterns [13] ing (ePatterning) information. The concept of ePattering re- flects the expected correlation between wafer pattern and 12. A DfM Flowchart [14] device parameters to help with layout corrections. When a 13. Process compensation in IP libraries [15] wafer pattern of a transistor is electrically simulated, the op- tically simulated shapes of gate electrode and active region C. Verification – Feedback to design (die to wafer are simplified to rectangles, from which the electrical pa- level): rameters are determined based on ePatterning tables. 14. Etch process model [16] Figure 2 illustrates the concept of IP migration from a 90 nm to a 65 nm technology node. A hard intellectual property 15. Mismatch evaluation [17] (IP) block after shrinking, gridding, and compaction (anneal- 16. Process Variation on-chip sensor [18] ing), must meet timing and power constraints at the target technology node, i.e., with new lithoprocess, materials, im- 17. Planarity-related hot spots [19] plants etc. SPICE model changes due to different device and 18. Verification of 3D devices [20] process targets need to be implemented, using the ePattern- ing technique Fig. (3). In the process, layout geometries are 19. Table-based DfM [21] divided, matched, and scanned for repetitive blocks, to be extracted and stored into a database or library. Optical and 2. RECENT DFM DISCLOSURES electrical targeting with OPC (scattering bars, serifs, ham- 2.1. DFM Definition: Correct-By-Construction (CBC) merheads) and eOPC (drawn geometry extensions) helps Architectures achieve high resolution according to optical simulation and equivalent electrical properties. Because design verification may take up to 80% of de- sign development effort, one should use a correct – by – con- Next, model-based or rule-based ePatterning corrections struction architectures based on known good design intellec- are applied. First, a maximum rectangle inside the channel tual property (IP) for cost reduction. For CBC layout, one contour of the transistor is defined by overlaying it with gate may first assume that no design rules need to be checked for active contours. Then, the equivalent electrical width of the the 100% product yield. Restricting layout freedom up-front channel proven by electrical simulation (e.g., SPICE), is de- due to CBC should remove the need for corrections, if at the rived. Parametric correlations between the effective geome- expense of the die footprint. However, even for CBC cells, try and parameters in ePatterning equations are saved in the some aspects of layout placement may get overlooked, so ePatterning database. one should still run a design rule check (DRC) with com- This way, when an IC product is to be transferred from plexity depending on the confidence of IP robustness with one manufacturing technology to another, the designer does respect to process and design variations. Three robustness not need to be involved. The semiconductor manufacturer levels can be proposed, depending on the restrictiveness lev- 136 Recent Patents on Electrical & Electronic Engineering, 2012, Vol. 5, No.