Navigating Through a Changing Industry

V7/ Issue 2 /2012 2 Thick Films, New Processes, A Time Like No24 Other— Transistor and38 Different Materials— Sweeping Changes Interconnect Advances What’s Next for Challenge the Industry Smooth the Way 200mm Production and the Technology to the 2xnm Node

F a b Solutions

Solutions for Factory and Equipment Efficiency

Navigating through a changing industry Nanochip FAB SOLUTIONS F a b Solutions Interesting Times: publisher the Evolution of New and Old Dana Tribula Contents [email protected] in the Semiconductor Industry EDITOR-IN-CHIEF Liz Baird [email protected] A Letter from Charlie Pappis

Production Manager 1 Gary Dagastine A Letter from Charlie Pappis CONTRIBUTING WRITERS 2 Gary Dagastine Thick Films, New Processes, [email protected] Different Materials— Strong Engineering Foundation What’s Next for Katherine Derbyshire Right now, the technology challenges our industry faces seem more complex than ever. Supports Yield Improvement 200mm Production [email protected] CHARLIE PAPPIS In addition to traditional scaling, we are seeing rapid changes in materials and device structures to Group Vice President sustain the pace of productivity increases the industry has generated over the last several decades. David Lammers and General Manager, [email protected] On top of that, the industry is working on the next transition in wafer size: 450mm. Wafer size 7 Applied Global Services transitions are nothing new; 100mm was “state of the art” when I first joined Applied Materials over two decades ago. However, these intricacies and ever increasing demands on defect densities 10 NANOCHIP is published by make this a particularly interesting time for our industry. Software is Key Applied Materials, Inc. We’re seeing major changes in both semiconductor technologies and industry players, and to Effective © Copyright Applied Materials, Inc. 2012. a number of those are explored in this issue of Nanochip Fab Solutions. For example, the success of Yield Management EUV lithography has become so critical to the industry that ASML has now forged agreements with www.appliedmaterials.com some of their key customers—Intel, Samsung, TSMC—to invest in their business. That change may

Spansion Wrings accelerate both 450mm and EUV adoption, but significant risks need to be mitigated in both. Higher Productivity, And then there are the challenges of ramping volume production for atomic level device Lower Costs from To receive extra copies of NANOCHIP designs, with technologies such as 3D architectures, through-silicon vias (TSVs), and FinFETs. The 14 200mm Fab or to add colleagues to the mailing list, please email your costs and risks associated with these rapid changes are causing some major chip makers to rethink • Name their strategies and vie for niche positions. In some cases we see companies going fabless or exiting • Title the chip-making business altogether. 18 • Company Times are interesting too for the solar and display markets. Although solar cell manufacturing Real-Time • Business address Dispatching capacity still exceeds demand, we see very strong growth in the end markets. In the display Optimizes to [email protected] Semiconductor 21 market, manufacturers are no longer focused solely on large scale LCD screens for televisions. Improve Touch Package Screen Displays with The explosion in “everything touch”— from tablets and smartphones, to all sorts of electronic Assembly Anti-Reflective Films and Invisible ITO appliances and gadgets, has fueled a resurgence of factories producing the smaller displays on an NANOCHIP is now available earlier generation of equipment. A Time Like No Other— in an environmentally The evolution of the 200mm business is also an interesting story. In this issue of Nanochip Fab Sweeping Changes Challenge the Industry friendly online version. Solutions, we look at how Spansion is achieving higher productivity and lower costs in its 200mm 24 and the Technology Please send an email to fab, and examine emerging applications for power devices, TSV structures and MEMS devices that [email protected] to request online delivery. are breathing new life into 200mm fabs. You’ll also learn what Applied Materials is doing to ensure that parts remain available for these older tools. Other articles focus on some of the manufacturing challenges around process control, and how to manage particles and film uniformities in a high volume production environment. All trademarks so designated or PLUS: otherwise indicated as product names So these are interesting times indeed—and I hope, interesting reading for our Nanochip Fab 29: FABulous Tools: M/A-COM Technology Solutions Inc. or services are trademarks of Solutions subscribers. 30: Spotlight on ITRS Roadmap: ITRS Factory Integration Updates Aim to Boost Fab Efficiency Applied Materials, Inc. in the U.S. and 34: Cut Solar Costs and Increase Yield with Better Prediction of Wire Breakage other countries. All other product and 38: Transistor and Interconnect Advances Smooth the Way to the 2xnm Node service marks contained herein are 43: A Rewarding Year trademarks of their respective owners. 44: Mitigating the Pain of Parts Obsolescence 46 Buying Tools on the Secondary Market? Six Things to Remember 48: Knowledge Management Portal Boosts Applied's Field Service Responsiveness 49: The Last Word Nanochip 1 Power Transmission On-Board Power Generation / Conversion

High-Speed Rail

100M

Light Industry 10M GTO 1M

Electric Vehicles 100k THYRISTORS IGBT Power (VA) Power 10k

1k Home Appliances Bipolar MOSFET Power Supplies THICK FILMS, 100 TRIAC NEW PROCESSES, Air Conditioning Microwave Ovens 10 100 1k 10k 100k 1M Frequency (Hz) Figure 1. New power semiconductors are needed for power conversion, regulation and control in a broad range of applications. DIFFERENT MATERIALS— (Courtesy of Yole Développement.) and cost-effective to generate POWER ELECTRONICS being developed that can more WHAT’S NEXT FOR the highest possible financial efficiently and reliably step down Semiconductor technology returns, both for customers the output power to desired development historically has and toolmakers. This class voltages, rectify it and go on to been aimed at producing ICs 200mm PRODUCTION of emerging technologies is perform other power conversion with greater functionality Electric vehicles, remotely powered sensor networks, inventive handheld among the most price sensitive, functions. By and speed. But with globally with ASPs far lower than one Hybrid/electric vehicles are devices and other new products depend on enabling technologies now heightened interest in dollar, so the bulk of the global another huge opportunity. They Mike environmentally sensitive in various stages of development. These include advanced power ICs, production takes place on have sophisticated electrical alternative energy solutions ≤ 200mm-compatible toolsets. systems that use many power Rosa 3D chip modules, thin-film batteries and novel MEMS devices— for a number of applications Over the longer term, ICs for power conversion and (see figure 1) comes a all of which are currently manufactured on 200mm wafers. however, as devices continue enable electronic systems to act greater focus on the issue of to be refined and evolve in their as substitutes for power-hungry, Although this may change Producing and integrating (≥10µm), magnetically aligned power management. Today design and process complexity, heavier, and less-efficient as device footprint, form factor these diverse devices and films such as nickel iron (NiFe), that means not only power there will be staged migration electromechanical and hydraulic and average selling price (ASP) circuits require a variety of and low-temperature CMOS- conversion and voltage/current to 300mm tools for extremely components. become greater factors, scaling semiconductor fabrication compatible films, including regulation and control, but also high volume production. Advanced power and migration to larger wafer techniques ranging from silicon germanium (SiGe). the ability to do these things at Early examples of technology semiconductors will depend sizes are not currently priorities complex dry etch processes Understandably, producing higher speeds and at increasing segments that may benefit on four key technologies: thick for these applications. What to the deposition of different this variety of devices for levels of power. from this transition include Al for heat transfer, thick epi, is in short supply is continued types of thick and thin films. myriad applications isn’t easy, In the renewable energy power devices and MEMS. deep reactive ion etch (DRIE) innovation in the areas of new Examples include aluminum and the task is made even area, for example, key goals are Here is a look at a few for trench formation, and the materials development, thick nitride (AlN), germanium (Ge), harder by today’s economic to increase the efficiency and technologies needed to ability to handle thin wafers and film processing, and thin/thick thick oxides (≥40µm thick), imperatives. Technology power output of wind turbine produce the devices and the stresses relevant to their wafer handling. thick epitaxial films (>150µm) development must be generators. Next-generation circuits for some of tomorrow’s extremely thin material layers. and thick aluminum (Al) volume-production worthy power conversion systems are most exciting products. 2 Nanochip Nanochip 3 Manufacturing steps of super junction MOSFETs (Source: Super Junction MOSFET report, June 2011, Yole Développement) APPLICATION Process Parameters G S S Etch • High etch rate and uniformity S G G (Si etch) • Small scallop size • High resist selectivity THICK FILMS, n • Low cost of owership (CoO) CVD • Excellent thickness uniformity and coverage NEW PROCESSES, p (liner and passivation) • Thermal budget n epi • Adhesion to PVD Ta/TiN barriers DIFFERENT MATERIALS— p p + WHAT’S NEXT FOR n substrate PVD • Continuous barrier coverage D D (barrier/seed) • Cu seed coverage on via even on scalloped sidewall 200mm PRODUCTION Manufacturing steps of Manufacturing steps for ECD • Enhanced bottom-up fill, wide process window, reduced over-burden multi-epi SJ MOS: deep trench SJ MOS: (electro chemical • Lower thickness requirements for ionized Cu seed • First epitaxy • Creation of trenches using deep deposition) • Lower combined CoO PVD B/S+ECD+CMP • Implantation Repeated reactive ion etching process • Epitaxy 4-5 times • Filling trenches with epitaxial layers • Diffusion • Planarization with CMP CMP • High removal rate These four technologies with fully dielectrically Commercialized by Infineon, Used by Fairchild, Fuji Electric, Toshiba… (polishing) • Excellent thickness uniformity ST Microelectronics, Fairchild, • Low cost of consumables (CoC) are needed for each of the isolated power switches MicroSemi, Ixys… THIN-FILM BATTERIES main types of advanced power and analog components When moving to high voltage, +95% of the MOSFET’s resistance comes from the epitaxial layer Figure 4. Process capabilities and associated parameters required for TSV production. Implantable medical semiconductors: for complex power Super junction MOSFETs reduce ROn by a factor of 5 devices, smart cards, RFID ■■ management functions. Discrete power tags, wireless sensors for highly Figure. 2. The two main methods used to produce the thick films required transistors: Super junction distributed networks, and other by super junction MOSFETs. (Courtesy of Yole Développement.) transistors (SJTs) switch 3D ICs: electronic products designed quickly and can handle TSVs AND THIN WAFERS for autonomous operation high currents, voltages and To address the cost and Multiple epitaxy process steps, all require power. Solid-state power levels. Today there used to make +90% of super junction MOSFET sold technical challenges associated (Source: Super Junction MOSFET report, June 2011, Yole Développement) thin-film batteries (TFBs) are two ways to fabricate with continued device scaling, being developed on 200mm the SJT device (see figure n epi n epi Via Formation Insulation Barrier/Seed Via Fill Removal of Fields one emerging alternative is DPS DT+ CVD USG SIP EnCoRe™ Raider-S™ ECD Cu CMP platforms (see figure 6) can 2 ). The first is a thick epi n+ n+ to stack chips and wafers in a substrate substrate open the door to many of these deposition doped in one 3D configuration to achieve G S G new applications. area. The deposition is Figure 5. Typical steps in TSV fabrication. higher circuit density and a TFBs may enable repeated several times to n smaller overall footprint, and innovations such as power build thickness and then it TSVs are being used The process capabili- standard wafer thickness to integrate chips made with supplies that last the life of is annealed (see figure 3). p in applications such as ties needed for TSV produc- of 700µm. Without any different technologies. Key a system; distributed power n LEDs, power devices, and tion are etch, CVD, PVD, modifications, existing tools With the second method, n epi epi systems consisting of multiple, to the 3D architecture is the MEMS to enable low-profile ECD and CMP (see figures can only handle wafers a trench is etched and + + ability to fabricate through- n substrate n substrate small form-adhering TFBs; and then filled with doped interconnects and as a path 4 and 5). of ~200µm thickness silicon vias (TSVs). These high D even near-perpetual energy epi material. toward 3D integration and In 3D architectures successfully. Also, process aspect ratio vias run vertically modules (when combined Figure 3. The lengthy and repetitive thick epi deposition process—while die-stacking. TSV technology extremely thin wafers are steps such as wet/dry etch ■■ Insulated gate bipolar through the stack and are filled with energy harvesters). TFBs widely used—is less efficient and precise than the alternative dry etching is quickly migrating across needed to facilitate stacking and CMP must be handled transistors (IGBTs): Used with metal to interconnect the are also well suited to serve as and filling approach now in production. (Courtesy of Yole Développement.) application segments to meet and bonding, on the order differently with wafers that backup power for memories where both high efficiency various chips. the demand for devices that of 50µm-thick wafers vs. a are so thin. and microcontrollers. and fast switching are Manufacturers had are not only thin but also have 2011 top 10 providers of power devices Solid-state TFBs have required, IGBTs combine expected to use 200mm small footprints. the characteristics of both tools for TSV development technical and performance 1. Infineon This push, once thought Encapsulation MOSFETs and bipolar and 300mm tools for volume advantages such as high cycle 2. Mitsubishi Electric to be motivated by the Cathode Anode transistors. They are often production. However, other current current life (2–3 orders of magnitude trend toward end-device collector collector 3. Toshiba Anode higher than conventional Li- found in power conversion/ emerging technologies miniaturization, now is Electrolyte ion batteries); a fast charge/ conditioning applications. are being developed on 4. STMicroelectronics supported by a combination Cathode discharge rate and near-zero ■■ Bipolar-CMOS-DMOS 200mm wafers and some 5. International Rectifier of overall size reduction and self-discharge rate; high (BCD) circuits: So-called of them require stacking and 6. Fuji Electric the need to free-up space for power capability; non-liquid “smart power” technology isolation, which can leverage other critical elements, such as 7. Fairchild Substrate electrolyte; wide operating that combines high- TSV processes. Therefore, displays and batteries. 8. Vishay temperature range; and a density logic circuitry manufacturers decided to also develop TSV technologies on 9. Renesas Figure 6. Cross-sectional schematic representation of a solid-state thin- 200mm tools. 10. Semikron film battery.[2] Table 1. A globally diverse group of IC manufacturers is currently engaged in power electronics R&D on 200mm tools.[1] 4 Nanochip Nanochip 5 contemporary smartphones impacting our daily lives in and portable devices. countless ways. For example, THICK FILMS, MEMS fabrication distributed temperature and NEW PROCESSES, technologies for the production flow sensors could be placed STRONG of next-generation, integrated on a building’s heating/air DIFFERENT MATERIALS— functionality devices are also conditioning vents to monitor WHAT’S NEXT FOR under development. One is total system performance with a reduced aspect ratio dependent degree of precision not currently ENGINEERING 200mm PRODUCTION etch (ARDE). When combining available except at high cost. accelerometers or gyroscopes The question is, how will very thin form factor. This gyroscopes, accelerometers, with large-cavity devices such this new class of independent makes them appealing for use and digital compasses. FOUNDATION as pressure sensors, a key sensors be powered? MEMS in a wide range of applications MEMS is fertile ground productivity challenge is to etch technology theoretically could (see figure 7). for new technologies, and the large critical dimension (CD) be used in an energy-scavenging Yet despite their technical integrated pico-projector is trenches alongside smaller role; for example, to convert advantages and market one of the potentially high- trenches (CD=1µm or less) at the mechanical energy of SUPPORTS YIELD potential, the transition from volume ones. Integrated in the same rate. ARDE promises vibration into the tiny amounts R&D to high-volume TFB smartphones or other mobile to make this possible. of electrical power required manufacturing has been devices, pico-projectors are IMPROVEMENT Other MEMS processes to operate the sensors and slow and challenging. The based on an assembly of under development are aimed broadcast sensor readings to a immaturity of emerging MEMS micromirrors, with at process challenges related larger network. applications is part of the the most recently announced to material properties; for reason, but other major developments using red, example, micro-bolometers THE FUTURE BEGINS NOW factors include lower energy green and blue lasers to Yield is the single largest contributor According to Patrick Fernandez, director of Applied Materials’ used in night vision and content (which nevertheless “write” an image on a rastering Manufacturing innovative, FabVantage Yield Consulting Practice, a large majority of yield thermal-imaging systems. In to the financial performance of a may be suitable for specific micromirror surface. highly integrated future products loss is due to process and equipment behavior. The remainder the case of thermal imaging for application requirements), a Stand-alone models will require new technology is due to device design issues, process integration marginality, industrial applications, micro- semiconductor fab. Yield loss during a higher cost per mAh, and lack currently on the market have capabilities such as the ones manufacturing errors, and facilities problems such as airborne bolometer film requirements of compatibility with high- limited functionality. As described in this article. Applied new technology or product ramp costs molecular contamination. may need tuning beyond what volume production. more integrated, brighter, Materials sees 150mm/200mm Process tools are deterministic: for a given set of process is considered typical in other the industry as a whole billions of dollars and less power-hungry tools as attractive platforms on and equipment inputs, the on-wafer result can be derived from segments. Specific electrical NOVEL MEMS DEVICES units become more widely which to advance many of these engineering or statistical models that are verified with physical properties will be needed annually, or tens of millions of dollars available, they may spur key technologies. understanding. Thus, the majority of yield problems can be solved by MEMS devices first that may require additional new and innovative uses of Independently, and in per fab. But in addition to the poor yield fixing issues on the process tools. For example, a fundamental driver gained volume production development effort, adding this projection technology. collaboration with customers, of a high density plasma (HDP) process is the deposition-to-sputter in automotive and printing complexity and cost to the results themselves, yield losses impair Emerging projectors employ Applied continues to invest in ratio. If deposition and sputtering are not optimized, the deposited applications. More recently, manufacturing challenge. MEMS-based technologies process and equipment devel- film can pinch off the entrance to the “gap” (a recessed region that, growth in consumer applica- Even within a device family, the rate of learning because scrapped capable of targeting device opment that will turn workhorse in cross-section, looks like a via). The result is an incompletely filled tions has spurred the growth applications may require thicknesses of less than 5mm, 200mm tools into enablers of wafers or confounded results require gap. This defect, known as voiding, causes electric current leakage, of MEMS devices such as different categories of making them suitable for most new technologies that will a yield killer. Figure 1 illustrates such a void. MEMS performance. make life easier and better. additional learning cycles, thus further In the future, as more tangible, everyday objects contributing to loss in time-to-market ≤ 5x5mm ~ 25x25mm ≤ 5x5mm For more information, contact become embedded with (<50 µAh) (up to 1 to 10 mAh) (<50 µAh) [email protected]. and in revenues. A fast learning rate is a sensors and gain the ability to Backup Tagging/ID Wireless Devices Sensors communicate, the resulting [1] http://www.eetasia.com/ requirement for high-achieving fabs. Real-time clocks RFID Automotive Consumer Memory backup SmartCards Energy Telecom network—which some are ART_8800669970_765245_ SecurID Environmental Medical calling the “Internet of Things”— NT_59f88ef4.HTM Smart Keys Health BY Industrial will begin to take shape. The [2] N. J. Dudney, Solid-State Internet of Things will have the Thin-Film Rechargeable HELEN potential to quantify almost Batteries, Materials Science 10’s µAh 10’s mAh every aspect of our environment, and Engineering B 116 (2005) ARMER reducing costs, changing 245–249, Elsevier. Figure 1. Illustration of a void caused by deposited Figure 7. Replacement and emerging applications for thin-film batteries. current practices and ultimately film pinching off the entrance to the gap in an HDP gapfill process. 6 Nanochip Nanochip 7 STRONG performance metrics and best known methods (BKMs). It contains variation (far exceeding recommended range) between zones during

ENGINEERING 4.5 data on each tool’s entitlement for uptime, throughput, process results the temperature ramp up step, as illustrated in figure 3a. This was

4.0 on the wafer, and particles. It contains BKM recipes, equipment con- determined to be the root cause of the substantial within-wafer FOUNDATION stant settings, maintenance procedures, hardware configurations, and variation in transistor characteristics reported by the customer. 3.5 Voids software revisions for >500 kinds of process chambers. Resolution of this issue included improvements in mainte- SUPPORTS YIELD 3.0 Additionally, the knowledge base contains process trend charts nance procedures and a recipe change, resulting in a much tighter 2.5

Gap Aspect Ratio that show process sensitivity to the various controllable inputs and temperature range during ramp (see figure 3b) and tighter transistor IMPROVEMENT No Voids 2.0 that show regions of process marginality. According to Fernandez, performance. When the root causes were corrected, the temperature

1.5 “It is difficult to troubleshoot yield problems without understanding spread dropped to the specification of <50°C (see figure 3b). 3.0 3.5 4.0 4.5 5.0 Deposition to Sputter Ratio these fundamental drivers. We have seen incorrect recipe or

(2a) Process regime that gives void-free gapfill on HDP chamber. equipment setup that has resulted in many wafers being scrapped.” 600 A common example of faulty equipment setup is incorrectly Process and hardware characterization of an Applied Materials set mass flow controller verification and correction factors. These HDP chamber identified process regimes that give a void-free can result in flow errors of up to 10% and cause a process to gapfill as a function of the structure’s aspect ratio (see figure 2a). 140 operate on a cliff. Other problems frequently encountered include 500

This model, combined with other process characterization on this 120 overcleaning during in-situ cleans, resulting in particle generation; chamber, can be used to troubleshoot a void problem. Figure 2b underseasoning, causing a wafer-order effect; and running a process (°C) Temperature 100 illustrates a second characterization model needed to optimize this with the throttle valve fully open, preventing pressure control. 400 80 process on a given set of hardware. Older fabs have the challenge that they are typically operating Time from start of recipe step (seconds) In all, seven process parameters need to be simultaneously (sccm) Rate SiH4 Flow 60 with legacy tools and processes. They may not have the latest (3a) Before optimized to produce a high-yielding structure. While this example is 40 process BKMs or maintenance BKMs and their tools may no longer 3.0 3.5 4.0 4.5 5.0 5.5 6.0 simplistic, it illustrates the extent of process characterization needed Deposition to Sputter Ratio (dimensionless) be set up correctly for the processes that are currently run. Leading-

to identify and correct misprocessing on a tool and thereby eliminate 600 (2b) Model to tune the process to achieve a target deposition-to-sputter ratio. edge fabs face a different challenge. While they typically have new yield problems caused by process and equipment. or nearly new equipment, overseen by very capable engineering Figure 2. Process characterization models for the HDP process. teams, they often need to operate the tool at the edges of the KNOWLEDGE BUILDS BETTER YIELD process window in order to push the device performance envelope. 500 FROM BOTTOM UP Understanding the process chamber’s behavior helps show at what

Conventional yield improvement methodology is essentially over many years of experience and builds on our vast tool and point yield is likely to break down, or where the trade-off between (°C) Temperature top-down: start with the outputs—low-yield and non-yielding process knowledge. Some examples of our methodology are: device performance and process stability lies. 400 wafers—and attempt to determine which process steps are the root ■■ Benchmark each tool against best-in-class data from our cause. One problem with this approach is that failure is observed at knowledge base. Benchmarking is used to identify tools with YIELD IMPROVEMENT IN ACTION Time from start of recipe step (seconds) (3b) After the end of the line (after hundreds of process steps) or much farther poor defect performance and high unscheduled downtime, both The bottom-up methodology discussed above was used in a down the line, and weeks may have elapsed since the wafer was of which flag potential yield loss. recent FabVantage customer engagement. A customer was having misprocessed. During this time, the tool could have been changed, Figure 3. Each color in above figures represents one of seven heater ■■ Review parametric failure paretos. These may show mani- yield issues resulting in a large gap to world-class yield performance. zones in the RTP tool. (3a) shows large within-wafer non-uniformity such as by doing preventive maintenance (PM), and the problem may festations of failures that have previously been documented. The yield loss was believed to be associated with new technology during the RTP ramp. Once BKMs were implemented, the temperature have been fixed. For example, high transistor leakage variation is sometimes introduction, but the root causes were not readily apparent to the spread dropped significantly to <50°C (3b). Usually, it is difficult to identify the root cause. Fabs still have the associated with poor temperature control on rapid thermal customer. FabVantage benchmarking and assessment identified historical statistical process control (SPC) or fault detection (FD) processing (RTP) spike anneal tools. issues related to transistor control and defects. Further, the yield loss CONCLUSIONS data for the tool, and this is used to perform root cause analysis, but was traced to a small set of tools, including RTP. Subsequent detailed ■■ Study customer inputs and the history of what they have tried. the root cause may remain elusive if the SPC models are not tracking assessments of these tools identified faulty equipment, incorrect Yield is the most serious problem affecting fab productivity, Customers can often isolate problems to a few tools or modules the correct sensors or if the control limits are not correctly set for equipment setup, recipes missing critical steps, and overcleaning and often it is one of the most challenging to solve. However, with based on factors such as chamber mismatch, high downtime, detecting yield-detracting excursions. Furthermore, traditional during in-situ cleans. the right approach and information, it is also an eminently solvable and difficulty recovering tools after maintenance. SPC and FD models present their own problems related to the A joint task force between Applied and the customer was problem. Fundamentally, yield loss occurs when a tool fails to apply large amounts of data collected and acted upon, alarms, and false ■■ Review failure paretos and wafer-level metrology data from formed. The team set inline targets with weekly reviews. A golden the correct process to a wafer. Though the number of inputs to positives or negatives (see the article “Software Is Key To Effective tools with the most failures. For example, if a CVD tool is being tool approach used split lots to verify and qualify improvements. any given process is large, most semiconductor manufacturing Yield Management” elsewhere in this issue). taken down frequently for faceplate or liquid flow meter issues and Inline improvements were achieved within three months, and over equipment is well characterized. Systematized knowledge, rigorous In addition to these top-down methods, the Applied Materials we see marginal thickness or thickness uniformity performance, the following year yield improved significantly. audit and analysis methodologies, and deep tool expertise can bring FabVantage consulting group offers this bottom-up approach: then we have a suspect tool. This tool may be running an unopti- While a full discussion of the issues found is beyond the dramatic yield improvement results. ensure that the process and equipment inputs are optimized for the mized recipe or it may have incorrect equipment constant settings scope of this article, the RTP analysis is typical. As a first step intended result. The bottom-up approach requires a methodology or hardware setup, or perhaps it is not being properly maintained. toward better RTP performance, the team discovered that the Special thanks to Katherine Derbyshire and Patrick Fernandez for their for identifying the suspect processes and equipment, no small task As the above discussion of methodology suggests, the knowledge tools’ characteristic fingerprints were far from expected baselines, invaluable support in the preparation of this article. in a fab that contains hundreds of tools running hundreds of process base is one of the critical capabilities of the FabVantage approach. and that process BKMs were not being used. For example, the steps. FabVantage uses a rigorous methodology that was developed The Applied knowledge base is our extensive compilation of tool temperature sensor trace comparison revealed a large temperature For additional information, contact [email protected]

8 Nanochip Nanochip 9 waste engineering time, it slows the has so many parameters affecting acceptable Idrive performance (gray progress for real yield improvements. yield that very sophisticated shaded box) yet the inline process To achieve optimum yields, methodologies must be used to data was all within control. manufacturers must move from interpret the results. This analysis identified chambers excursion control based on SPC Applied’s FabVantage consulting with the highest yield variability, as and FD to an overall total yield team initiated a project to assess well as process steps that were the control solution that leverages high- the situation and identify a solution. most closely linked to these yield performance automation to handle Detailed data mining was done on variations. A subsequent analysis large volume data processing. They a variety of measurements across using Applied’s E3 equipment must also utilize advanced data the suspect chambers (see figure engineering system and extensive mining and modeling, and move to 1). The analysis showed that certain knowledge base, plus commercial yield-driven control methodologies. chambers exhibited much larger statistical analysis packages and Yield-driven control augments variability in Idrive performance— proprietary software and models, traditional process control (SPC and resulting in yield loss—even though enabled the FabVantage team to FD) by correlating end-of-line yield all the inline process parameters were identify potential root causes. A data (device performance) with inline within control limits. For example in further analysis “weighted” each process data. Instead of process figure 1, the “green” chambers show item, enabling identification of the Software is Key control based on process centering, that most of the results are outside of most likely root cause. control limits for the inline process TO EFFECTIVE YIELD MANAGEMENT control are modified to optimize end- of-line yield results, which could be Idrive Distribution Across Chambers different than process centering. By Today’s advanced IC manufacturers are collecting more data than they are Applied Materials’ FabVantage able to manage effectively. Our discussions with leading semiconductor consulting team recently used Scott yield-driven methodology vs. SPC manufacturers indicate that more than 90% of data is not accessed after it and FD to resolve yield issues for a Watson 300mm customer. Even though the Gray Area = Yielding Area Gray is initially processed during data collection. And the volume of this data is inline process data was in control for

growing exponentially, driven by the improved computing and communication a specific process step, there was a Chambers yield problem. Inline measurements capabilities of tool platforms and expansion in the number and type of sensors were not identifying the cause of the Figure 1. Idrive variability across process chambers. All chamber process parameters yield variance. installed on advanced chambers. are within spec for inline process control, yet yield failures are seen (all data points Advanced analysis techniques, outside shaded box above do not yield). Forward-thinking manufacturers valid methodologies, but may not fabs but the number of FD models is including analysis of variance see this deluge of data as a huge always be applied appropriately. SPC growing rapidly, so it is reasonable (ANOVA), clearly showed that untapped opportunity to proactively and FD normally utilize statistical to expect they will soon exceed the the problem originated at specific Root Cause Pareto improve yield, one of the largest control limits that are derived based number of SPC charts. chambers within a specific process

contributors to a fab’s profitability. on the inline process parameters However, the sheer volume of step. The inline process data did 0.6 Effective data management at the specific process step or SPC charts and FD models is simply not show a statistically significant 0.5 can help fab managers identify yield tool to center the process. Yield impossible to monitor. Too many variation between chambers but 0.4 excursions, initiate root-cause analyses excursions—which are shifts in exceptions would be flagged each did show a statistically significant and provide predictive feedback to device performance as measured at day, well beyond the ability of an difference in the resulting device Weight 0.3 equipment engineering systems (EES) the end of the line—can still occur engineering team to handle manually. performance, which in turn resulted 0.2 in order to improve yield. even though SPC or FD determine Coupled with the fact that these in yield loss. However, the customer 0.1

Statistical process control that the inline process parameters exceptions now need to be tied to was unable to determine the cause of 0.0 (SPC) or fault detection (FD) are in control. end-of-line yield data, the challenge the variation in device performance Root Causes systems are the current standard Leading-edge device makers is huge. As a result, the engineering results across the chambers. A methodologies used to process data often have tens of thousands of SPC response becomes ad hoc and more automated process-driven Figure 2. Use of analytical tools and data mining provide pareto of potential root as it is being collected in order to charts and thousands of FD models. may or may not address major methodology was required because causes of yield variation. identify yield excursions. Both are FD is still relatively immature in most yield problems. Not only does this leading-edge device complexity

10 Nanochip Nanochip 11 the yield-driven control methodology event-driven strategy engine. All in order to improve the results. The Software is Key described in the example above communications between compo- key is to consistently utilize this TO EFFECTIVE YIELD MANAGEMENT and enable automatic modification nents (arrows) leverage standards untapped data. of limits as yield performance wherever possible to maximize Moreover, as EES solutions ad- correlations change over time. interoperability and the interchange- vance, these capabilities will become Create Model for Top Causes Set New Control Limits Figure 4 shows an overview of ability of components. integrated as standard models for the YMeAPC concept. It leverages an Although the YMeAPC frame- transforming current tool control equipment automation layer that is work begins to take advantage of the methods and practices into more Transistor Actual vs. Predicted Requirement typically already provided with an EES vast amount of data being captured automated, advanced yield control. deployment. It includes collections of by IC manufacturers, there are data from equipment (settings), the further opportunities to leverage it. Special thanks to Dr. James Moyne and manufacturing process (variables) Because a significant number of yield Patrick Fernandez for their assistance in drive I and the product (metrology, e-test) surprises are caused by events known creating this article. in real time as necessary to support to impact yield that go unobserved, For additional information, contact capabilities such as FD control. there is an opportunity to use [email protected] A subset of the equipment advanced data-mining and modeling New FD Limits to Replace automation data is summarized by techniques to analyze the massive Statistical Limits Additional reading on this subject: Wafer ID New FD Limits the FD system and then is correlated volumes of data in a background with yield information from e-test and mode to identify and prioritize the J. Moyne, B. Schulze, “Yield Management Enhanced Advanced Process Control yield metrology to derive a total yield- source of yield variances. Original FD Limits System (YMeAPC): Part I, Description prediction capability. This modeling can employ and Case Study of Feedback for This yield-assessment and standard statistical methods such as Figure 3. Models that predict Idrive are correlated to FD limits and yield. Such yield-driven control limits are often different than Optimized Multi-process Control,” -prediction capability serves as a ANOVA to provide ongoing reports locally optimized inline process FD limits. IEEE Transactions on Semiconductor crucial early-warning system. It can of potential causes of yield variance, Manufacturing, Special Issue on enhance productivity by providing which then can be used by process Advanced Process Control, Vol. 23, No. These root causes will typically tool performance parameters, and across the tools to identify variability yield information to critical functions, and yield engineers to prioritize their 2, (May 2010), pp. 221-235. be a combination of critical chamber establish yield-driven control limits. that could impact yield performance. including maintenance, scheduling work. Ideally, these models initially J. Moyne, N. Ward, R. Stafford, B. sensors, tool constants, and recipe In the previous example, FabVantage In the example above, this was done and dispatching, and run-to-run would be established as part of the Schulze “Yield Management Enhanced parameters. The results allowed the used a variety of software solutions to manually. However, this represents control, enhancing decision-making technology integration process so Advanced Process Control (YMeAPC),” FabVantage team to model these derive results as listed below: another opportunity to apply software and yield optimization. they can accompany new process (Invited session keynote), International top causes of yield variation and set ■■ Applied E3 equipment engineering to automate the comparison of key This collaborative and flex- introduction into the wafer fabs. SEMATECH AEC/APC Symposium new inline yield-driven control limits system: High speed/high volume equipment constants. ible integration is achieved by an Over time, they can be optimized XX, Salt Lake City, UT, (October 2008). that were derived from the yield chamber sensor data collection, With the rapid growth in the results versus inline statistical control trace analysis and data mining. amount of data being collected and as limits (see figure 3). The transistor yield issues for advanced technology ■■ Commercial statistical analysis requirement (green arrow) identifies nodes become more challenging, it packages: SAS, JMP, Spotfire the range that ensures good yield. will become critical to automate this Yield and others utilized for additional Data The team created a model of the yield methodology. Such a solution Yield Reporting yield analysis, modeling and Warehouse root cause sources to the expected will enable manufacturers to correlate Mining data mining. resulting transistor requirement. This yield and device performance ■■ model is then used to derive new Proprietary software/models: excursions to key tool performance Consolidated inline process control limits that will Models developed by the parameters and establish specific FD Data Warehouse control the resulting yield perfor- FabVantage team to augment models to improve yield. FDC PLS E-Test Yield Analysis Analysis Analysis mance. These changes were imple- E3 and commercial software Applied calls its methodology mented on a “golden tool” and suc- packages. for implementing this automation Equipment Automation Layer cessfully qualified by the customer. ■■ FabVantage Knowledge Base: solution enhanced advanced process The changes are now being deployed Capture of a wide range of critical control (YMeAPC). It integrates across the remaining chambers. equipment control (FD) with yield SECS/ EDA SECS/ EDA yield/process information and GEM GEM ECA Strategy Engine The key to all this is software— best known methods to facilitate management system (YMS) and R2R Real-Time software that can collect the requisite root cause analysis. equipment engineering system (EES) Maintenance Equipment Control S/D data, support the data mining capabilities in order to improve yield Test Health Indications In order to implement yield- Patterning (Traditional Use) activities to derive the root causes, and reduce cost. Implementation of driven control limits, it is also crucial model the root causes to inline this capability will further automate to analyze the equipment constants Figure 4. High-level view of YMeAPC solution.

12 Nanochip Nanochip 13 No fab can remain static for long in today’s competitive world, and older fabs require just as much innovation and creativity to remain competitive as the leading-edge fabs—perhaps more so.

Worldwide more than a third of 2009. It emerged from Chapter 11 production volume must come from the wafers processed this year will in May 2010 and now has annual making the existing equipment and be 200mm in diameter, according revenues of roughly a billion dollars. space more efficient and productive. to market research firm IHS iSuppli, The new management team, That is where a series of Applied to make a wide variety of products, led by CEO John Kispert, recognized FabVantage consulting engagements including analog and power ICs, that the 200mm Fab 25 in Austin came into play. sensors and MEMS. Europe, with was fully depreciated and able Dawson said one of Spansion’s its strength in automotive ICs and to profitably make the chips that challenges with its 200mm sensors, is a major 200mm center. became Spansion’s bread and butter: equipment “is not so much base Among the world’s 200mm fabs, highly differentiated “embedded functionality, but defect performance. Spansion’s flash memory operation flash” solutions sold to some 7,000 A very large improvement as the in Austin, Texas, has remained different customers. industry went to 300mm from particularly dynamic. Spansion is Fab 25 may be unique in that it 200mm is in the ability to process among the many companies coaxing can manufacture at 110nm, 90nm, wafers more cleanly,” he said. The higher productivity and lower costs and 65nm simultaneously, with an defect challenges come partly from A Customer Story from 200mm fabs. aluminum back end for the 110nm the wafer handling equipment, with Not far from Spansion’s fab, devices and copper interconnects chamber design also playing a role. Freescale Semiconductor makes for the 90 and 65nm products. microprocessors and MEMS at When demand exceeds Fab 25’s two 200mm facilities. In nearby capacity of 40,000 wafers per San Antonio, Texas, Maxim relies month, the company relies on on its 200mm facility to make its foundry partner SMIC for some leading analog products. These 65nm production needs. are just a few examples of large SPANSION semiconductor companies relying on FINDING YIELD KILLERS 200mm fabs for the majority of their To meet high demand and achieve By revenues. WRINGS HIGHER PRODUCTIVITY, profitability goals, Fab 25 director of Spansion became independent David Engineering Gary Dawson said his of Advanced Micro Devices at the team has worked to wring every last end of 2005. The perils of supplying Lammers LOWER COSTS FROM 200mm FAB ounce of productivity from its 200mm NOR flash to the cyclical cell phone tools. “Through many iterations of market and an unsuccessful effort to learning we have developed this Gary Dawson, director of engineering, Fab 25, Spansion, Inc. build a state-of-the-art 300mm fab in factory to be the ultimate in flexibility.” Japan led the company to a Chapter 11 The Spansion factory is packed with bankruptcy reorganization in March equipment and any increases in

14 Nanochip Nanochip 15 Spansion Wrings higher productivity, lower costs From 200mm Fab

To help reduce defects and boost The most successful engage- collaboration is still in progress, with outside of a statistical distribution, throughputs, Spansion engaged with ment, Dawson said, involved an effort final outcomes yet to be determined. the equipment can be stopped in Applied’s FabVantage consultants for to improve the throughput of the “One of the attractive things real time for adjustments to improve three separate projects, one each on Producer dielectric deposition equip- about Applied Materials is that it has yield and performance. Fault Mirra Mesa CMP, DPS metal etch, ment. “Applied brought in five guys, done a really good job of evolving detection is widely used to gauge and Producer dielectric deposition and they did an industrial engineering 300mm equipment improvements, equipment performance. tool sets. While each project was analysis of how wafers are queued and then back-introducing them into Also, the company’s engineering 200mm— different, Dawson said the three up and staged, with different timing 200mm equipment,” Dawson said. team has developed “Lot Dossier,” engagements all involved bringing in a scenarios within the tool. They made The FabVantage engagements allow an application that provides real- small team of FabVantage consultants recommendations, we made those Spansion to take “full advantage of not time feedback on yields, and a Alive and well? to audit Spansion’s maintenance tweaks, and we got what we wanted: just the hardware improvements, but software tool dubbed Pluto that and processing methods. Spansion a 20% throughput improvement and procedural issues and BKMs,” he said. supports changes to the mix of work Jim Scholhamer, general manager own manufacturing and continuing would ask that the effort meet 2% to 5% better uptime.” in progress (WIP) as customers of the Components and Systems investments in 200mm application certain objectives, such as reducing Avoiding unscheduled down KEEPING IT PRODUCTIVE request more of a certain product. Group at Applied Global Services, development, Applied has forged defectivity by 50%, or improving time—part of an effort to improve In addition to looking for said the 200mm business is indeed relationships with qualified, special- throughput by 10–20%, depending what Dawson calls the “variability of LOOKING FORWARD continuous improvement and new alive and well, with about 12,000 ized used equipment suppliers to on the tool. availability”—is a prime focus of the applications for 200mm systems, The next big push for Spansion? Applied 200mm tools out in the field, support customers. fab engineering team. For DPS metal integrated device manufacturers Predictive maintenance (PdM), many of them still working after 20 Asked about obsolescence of key etch, Dawson said Spansion’s etch (IDMs) with “More than Moore” aimed at extending the time critical years in operation. And the 200mm parts, Scholhamer said a dedicated team contacted Applied and said they fabs are increasingly concerned that parts can be kept in service. “Again, tools keep getting better. “We have team is in place to handle that area. In wanted to improve the variability of with so much focus on 300mm, certain aspects of the PdM program an engineering team dedicated to addition to qualifying some specialized availability by 50%, as well as a 50% and soon 450mm, support for will be done collaboratively with 200mm equipment upgrades and part vendors, the team uses modern reduction in defects. replacement parts and services Applied, while key algorithms will be enhancements,” he said. For example, technologies to re-engineer OEM The Applied consulting teams on older tools will wane. closely guarded as our proprietary advances in power supplies and multi- parts that are no longer available. observed teardowns of the etch With such concerns in mind information,” Dawson said. PdM is zone CMP polishing heads originally “There are some things we just can’t equipment, how it was cleaned, Spansion set up its own repair shop all part of improving the “variability introduced in 300mm generation outsource,” he said. reassembled, and brought back into in 2008, and has expanded its of availability” that Dawson’s team tools have been brought back into Beyond the technical challenges, service. They examined preventive ability to repair boards, re-creating is so focused on, which in turn is 200mm equipment. the 200mm equipment market maintenance (PM) techniques, and some parts where needed. “We part of a “kaizen” attitude of seeking Scholhamer said that Applied represents unique business the way the process is run, including have become more self-sufficient, continuous improvement. Materials recognizes there is a lot of challenges. ”Unlike 300mm, at how the plasma is struck, gas flows, improving our ability to survive,” In addition to sharing the company’s 200mm equipment 200mm the deals are large in and pressure. They compared what Dawson said. “We do more with less, benchmarking data with ISMI out in the field and that it is “not number and of relatively small size they saw against Applied’s best and when it makes sense we try to do and the Fab Owners Association, fading away and dying.” With the and it creates a challenging market to known methods (BKMs) and made more things internally.” Dawson said that internal controls power ICs, automotive sensors, address,” Scholhamer said. Demand remedial recommendations. For example, Dawson said are critical as well. “Part of our kaizen and MEMS markets growing, shot up in 2010, and while the market “After we discussed the some of AMD’s skills at advanced process is that we monitor ourselves Applied is continuing its efforts in has eased back in the last two years, BKMs with the FabVantage team, process control (APC) were refined obsessively, on a daily, weekly, and refurbished and, in some cases, it continues to be “a pretty robust and we did another PM, invoking the by in-house teams as Fab 25 passed quarterly basis,” he said. new 200mm tools. In addition to its healthy market.” recommended changes, and into Spansion’s possession. APC monitored for improvements,” For additional information about allows on-the-fly adjustments; Dawson said. He noted that the Spansion visit www.spansion.com for example, if a lot is found to be

16 Nanochip Nanochip 17 Rule-based real-time dispatching is one such solution that has enabled factories to improve performance for Required Capabilities for Achieving Enhanced Factory Performance on-time customer delivery, work-in-progress (WIP) cycle Reporting and business rules representation time, and product output. Dispatching can be defined Dispatching and scheduling execution Real-Time Dispatching as the setting and initiation of production activities and instructions in accordance with factory objectives such Real-time data access and representation as on-time delivery, cycle time, bottleneck utilization, etc. Change management OPTIMIZES Its goal is essentially to get the right product to the right Compliance monitoring equipment at the right time, a capability typically beyond SEMICONDUCTOR what an MES is capable of doing. Table 1. Summary of required dispatching capabilities to achieve Dispatching solutions must be seamless, execute enhanced factory performance. PACKAGE quickly, use aggregated real-time data, capture business rules easily and provide useful information to all operator compliance with automation decisions enables ASSEMBLY manufacturing stakeholders. timely corrections and better planning. For example, As shown in table 1, effective solutions must support when operators don’t follow dispatch decisions it may in- Complexities in semiconductor packaging assembly and significant technician involvement. This results such critical requirements as: dicate that there are inherent flaws in the business logic. have increased significantly over the years, challenging in wasted production time at the bottleneck and lost ■■ Reporting and business rules representation. on-time delivery and cost performance. product (because units are consumed during setup). A successful planning and scheduling solution DISPATCHING SOLUTION INCREASES by In particular, the wire bonding step is a common Further, manufacturing effectiveness is negatively must provide planners with data management/ ASSEMBLY PRODUCTIVITY bottleneck in assembly operations,[1] where its impacted due to unplanned setups, product priority transformation functions so they can create weekly, David Let’s take a closer look at a high-volume OSAT manufacturing efficiency directly affects on-time changes, quality problems, unscheduled equipment daily, or even per-shift plans. These functions must manufacturer’s assembly operation. customer delivery. A medium-sized or larger assembly downtime, and improper product routing. have access to real-time data so that operational Hanny The factory experienced a high degree of variability for facility generally has hundreds if not thousands of wire changes can be made nimbly as needed. 3. Manufacturing-related data is becoming complex both products and processes. This was impacting their abil- bond machines. Product lots typically spend more and now is gathered from many sources, such as ■■ Dispatching and scheduling execution. Once a ity to deliver products on time to their customers. A deep processing time in wire bond than in any other assembly manufacturing execution systems (MES), product good plan is created, a means to execute to it must dive into the customer delivery dilemma uncovered a manu- operation because of the growing complexity of packages and equipment engineering systems, and enterprise be provided. The solution must be systematic and facturing problem at the wire bond step, wherein the wire and the increasing number of lead and wire counts. resource planning (ERP) systems. This makes it not prone to human-introduced errors; thus it must bonders (the factory-designed bottleneck) were exceeding Additional operational challenges stem from challenging to quickly gather all needed data for timely be integrated with factory MES transactions so that their planned idle time and also were exceeding the number increasingly shorter product lifecycles, growth in product decisions. Relying on shortcuts such as examining the same business logic used to generate plans of setups, hindering the ability to meet throughput goals. mix, and the movement to outsourced assembly and test process data less frequently or using stale data can is used in dispatching and scheduling. Shop-floor With thousands of wire bonders, the problem was services (OSATs) where multiple packaging technologies diminish the ability to deliver the right quantity of and equipment-specific considerations must be impacting overall production and had a particularly adverse must coexist in the same factory. These factors contribute product on time. incorporated to balance factory objectives with impact on high-priority lots. Additionally, although the to growing costs in semiconductor back-end operations. practical operating constraints. process at the wire bond step required highly capable The major challenges arising from these factors 4. The influence of factory dynamics should not be ■■ operators with great expertise, there were time lags in generally fall into four main categories: capacity understated. Even when good plans are developed, Real-time data access and representation. Real-time making key manufacturing decisions. Digging deeper into imbalances, management of equipment setups, good execution mechanisms are in place and data data is crucial. Without it, decisions are less effective the manufacturing challenges, it was discovered that the manufacturing data management, and factory dynamics. is aggregated effectively from multiple sources, and the planning and scheduling functions are less productivity suffers when operational adjustments credible. When people don’t trust the system they tend decision-making process regarding what to process next 1. Capability imbalances occur because the growing are not properly executed. This has been observed in to circumvent it, which leads to higher manufacturing was unclear and poorly defined. The result? Inconsistent diversity of assembly equipment has brought varying scenarios such as product holds, equipment downs, variability and poor planning execution. operator behavior, poor loading/unloading time, and degrees of both automation and capabilities to handle product priority changes, and when peripheral unpredictable results. ■■ Effective change management. Many good different product types, wire/pad pitches, and wire The OSAT manufacturer determined that to resolve this resources like paddles and clamps are unavailable. planning and scheduling solutions fail because they types and sizes. When equipment disparities are not challenge, it was necessary to standardize and automate Add it all up, and short predictable cycle times are are implemented as add-ons to existing business well understood, operational planning is suboptimum their process at this bottleneck step. The expectation was becoming more and more difficult. This in turn results in a processes. A successful solution must minimally and shop-floor performance suffers. One major that if this key process was automated, it would enable an reduced ability to deliver shipments to customers on time. disrupt business processes and shop-floor end users. integrated device manufacturer (IDM) has reported increase in wire bonder utilization and a decrease in process It also must easily handle changes in business logic that capability imbalances alone led to a 13% drop in variability, thereby creating a more predictable factory. The DISPATCHING REQUIREMENTS and data sources without complex coding, and allow wire bond tool utilization (68% actual utilization vs. OSAT manufacturer selected Applied’s APF Real Time [2] production engineers to define and manage the 81% planned utilization). In the past, human decision-making alone was Dispatcher (RTD) software for the project. business logic representation. 2. Wire bond setup has become complex, tedious, and adequate to manage and operate semiconductor packaging Manufacturing execution data was captured from iterative, and thus the management of setups and assembly operations. But today’s challenges, coupled with ■■ Compliance-monitoring. Even the best planning and multiple sources. These event-driven updates allow the product changeovers greatly affects productivity. the growth of networked production environments, dictate scheduling solution can’t be effective if it isn’t used. dispatching system to continually make decisions with Success on the first pass is the goal but in reality the need for timely, accurate, consistent, and scalable data- Therefore a successful solution will enable decision- the current state of the factory, including process step several attempts are needed, causing long setup times driven solutions to support operational decision-making. makers to monitor its usage. The ability to measure completion, WIP on hold, and equipment down.

18 Nanochip Nanochip 19 Real-TimE DISPATCHING

OPTIMIZES SEMICONDUCTOR 200 production facilities globally, it is a real-time, high- PACKAGE ASSEMBLY performance dispatching and reporting system. RTD enables manufacturers to make better-informed and more consistent dispatching/scheduling decisions in order to Further, because order fulfillment priorities were improve productivity across the assembly and test facilities. changing as customers made frequent updates to their APF RTD and Reporter directs prestaging, releases orders, best practices for operators were developed to lots, and adjusts load-balancing of production equipment determine which lot to process next, creating execution through “what next, where next, and when next” rules that logic at the wire bond step. For example, tool allocation improve performance of product, carrier, equipment, and reports are executed in order to provide the latest status labor, with minimal load impact on MES performance. It of available equipment. As equipment is ready for the next helps manufacturers identify and implement process im- WIP, a “what-next” logic is executed, which in real-time provements without complex application programming, and determines what WIP is being processed, taking into provides reporting tools for analyzing manufacturing data Improve account factory dynamics. This logic considers the latest and identifying key constraints and areas for improvement. WIP location and expected arrival times of future WIP. On the shop floor, operators were trained on the new CONCLUSION Touch screen procedure, and compliance reports were used to verify Applied RTD and Reporter offers semiconductor adherence to the manufacturing process changes. assembly, test and package customers the opportunity to enhance their planning and scheduling functions. It is MANUFACTURING RESULTS displays designed for their unique manufacturing needs: real-time The results reported were very favorable. They are data access, rules-based dispatching, real-time reporting, categorized as shown in table 2. and scheduling for reacting to changes as they occur. Production planners are using the reporting and dispatch WITH ANTI-REFLECTIVE FILMS capabilities of RTD to optimize the daily production and Results customer delivery plans. These plans are then driven to * Equipment: measured between 5–10% OEE improvement execution through dispatch decisions that also improve AND INVISIBLE ITO • Reduced tool idle time asset utilization, enabling greater returns on investment • Reduced tool set up / change over time and profitability. Developed and deployed at over – Increased train size 200 factories worldwide, RTD has incorporated these – Reduced cycle time Touch panel technology is one of unique requirements into an out-of-the-box solution WIP KPI that has successfully demonstrated bottleneck capacity the most exciting developments • Reduced hot-lot cycle time expansion and cycle time improvements. Production • Improved on-time delivery planners using RTD have optimized dispatch decisions in displays, with smartphones Human effort KPI: 30% reduction in operator workload and improved asset utilization, driving greater returns on • Significantly reduced expertise requirements for operators investment and profitability. and tablet PCs representing the • Significantly reduced the training time required for new operators • Enabled new operators to be assimilated quickly into manufacturing For additional information, contact: [email protected] most prolific applications for the • Significantly reduced human loading for material push or [email protected] • Significantly reduced human loading to follow up lot (hot-lot ) technology. Touch interfaces are an [1] Management Daniel Quadt, Simulation-Based Scheduling of Parallel Wire- Bonders with Limited Clamp & Paddles, Proceedings of the • Provided transparent and real-time information for production control personnel enabling technology for the mobile 2006 Winter Simulation Conference, Perrone, Wieland, Liu, • Provided resource allocation in advance to forecast change-over per shift Lawson, Nicol and Fujimoto. Eds. display market, which accounts for Table 2. Results in assembly using RTD. [2] Alvin Y. Fong, An Assignment Model in Optimizing Wire sales of about 100 million tablets Bond Total Utilization in Multiple Tool Type and Product ABOUT Applied APF REAL TIME Mix Environment, Proceedings of the International and 690 million smartphones. DISPATCHER/REPORTER MultiConference of Engineers and Computer Scientists 2008 Vol II, IMECS 2008, 19-21 March 2008, Hong Kong Today more than 40% of Meeting the disparate requirements for semiconductor assembly, test, and packaging is critical to success in Additional Reading smartphones use touch panels, today’s fast-moving, ultra-competitive markets. The Bala Iyer & Binay Dash, Real Time Dispatching—A Catalyst leading commercially available solution specifically to Assembly Test Manufacturing Execution Automation, and this is expected to surpass designed to meet these challenges is APF RTD and APF Proceedings of the 2011 Winter Simulation Conference, Jain, [1] Reporter from Applied Materials. Deployed in more than Creasey, Himmelspach, White & Fu. Eds. 50% of mobile phones by 2014.

20 Nanochip * invisible indium tin oxide Nanochip 21 Improve Touch screen Anti-reflective, color-neutral coatings enhance Q. How do invisible ITO and anti-reflective coatings displays RITO sunlight readability and increase display brightness by work, in layman’s terms? R WITH ANTI-REFLECTIVE FILMS Etch reducing the visual reflectance on the substrate surface; A. Both technologies utilize the wave-like nature of light. RITO AND INVISIBLE ITO ITO for example, on the cover lens outer surface. Invisible The thin-film stacks are designed and integrated in REtch Low index ITO electrodes in the layer stack, meanwhile, offer such a way that each layer alters both reflected light as ITO High index pattern invisibility, enhanced color-fastness, increased well as the light passing through it. Working in concert, Glass Glass INTRODUCTION transmittance, and reduced reflectance. the layers have the combined effect of changing the More than a dozen touch screen technologies exist, display’s overall visual appearance as desired. In the including projected capacitive, surface capacitive, resistive, Discussion case of anti-reflective coatings, such cooperation among the layers is called destructive interference, on-cell, infrared, optical touch, acoustic wave, digitizer, Thomas Zilbauer, Applied’s project manager of R&D for RITO REtch RITO REtch and others. However, in small/medium displays such as PVD Display Engineering, has been developing invisible which means the reflected light’s intensity is decreased phones and tablets, capacitive touch has emerged as the ITO and ARC films at Applied Materials in Alzenau, in the visual range. In the case of invisible ITO, the film clear leader because of its form factor, reliability and multi- Germany for the past two years. He spoke recently with stacks are designed to achieve a light interference that produces a miniscule visual difference between the touch capability. Multi-touch refers to a touch screen’s Kerry Cunningham, product marketing manager in Figure 2. Invisible ITO for projective capacitive touch screen technology. Good zones with conductive ITO and without conductive ability to recognize the presence of two or more points of Applied’s Display Group. index-matching is possible with thin ITO layers, resulting in the ability to produce ITO. This difference is indistinguishable to the human contact with the surface. A good example of this is when “invisible” ITO electrodes. R (reflectance of ITO) and R (reflectance of Q. Thomas, do consumers enjoy an enhanced visual eye, both in intensity and hue. (See figure 2.) ITO Etch you are using two fingers on the touch screen at once to etched area) refer to the fact that the ITO is partially etched for patterning, and experience from invisible ITO in touch panel- pinch a photograph to zoom in and enlarge it. However, to achieve these results both the stack in the etched area the structures become visible. There is a difference in the capable devices? In general terms, capacitive touch works by having design and film deposition require a lot of care. An reflection of the ITO layer compared to the etched sections, and a key property for two layers of transparent conductor patterned into an X-Y A. Invisible ITO targets enhanced optical performance, analogy might be an orchestra, where all contributing the ITO layer stack is the invisibility of the etched structures, both in transmission cross-pattern. The two layers are separated by an insulator enabling the user to experience brighter displays, instruments must be well tuned to give a pleasant and reflection, for a uniform visual experience. of glass, or deposited thin film. When a finger touches the more colorfast displays, and displays without any sound. Similarly, the thin films need to be very screen, its electric field is distorted. The location of the distracting sensor patterns. With regard to the latter, precisely manufactured. For example, when our touch screen products and scale them to larger sizes. distortion is sent to the controller for processing. In the in most of today’s smaller mobile phones the touch customers use one huge glass sheet to produce many The Aristo Twin system and its wide range of process “one glass” solution shown in figure 1, the X-Y ITO layers sensor patterns are barely visible if at all in off-mode phones, the film thickness is allowed to vary only by solutions represent the state of the art in touch are deposited in one layer, eliminating one layer of glass to under sunlight reflectance. When they are visible they a few atoms across the entire utilized substrate area, screen panel manufacturing, making possible sunlight reduce manufacturing costs. can generate complaints from people who see them which is as large as 1.1 x 1.3 m². A capacitive touch panel film stack may have 15+ and worry needlessly that they may have received readability, improved color appearance, and clearer Q. How fast are these technologies being adopted and film layers, and most of these stacks require 4–5 physical a low-quality device. But as larger, thinner devices touch screens that enhance the user experience. what are the key advantages for our customers? vapor deposition (PVD) layers. Some of the layers, such with reflectance reductions for improved sunlight A. I am impressed with the adoption of invisible ITO For additional information, contact [email protected] as anti-reflective (ARC) coatings and invisible indium tin readability fill the market, the conventional ITO pattern for touch sensors on glass. Leveraging our in-house [1] oxide (ITO) electrodes, are there to improve the user’s becomes increasingly visible and results in distracting Internal Applied Materials data. expertise on the original invisible ITO concept from our perceived viewing experience and thus are unique to patterns even during display operation. Invisible ITO SmartWeb technology (roll-to-roll deposition on PET), touch panels. then becomes an inevitable necessity. we could quickly consult with our customers on this Q. Do the invisible ITO and anti-reflective coatings material. We have continued to do so as the solutions Manufacturing cost reduction support the competing technologies in touch panel? About Dr. Thomas Zilbauer have gotten increasingly difficult and demanding. Our Thomas Zilbauer earned a Ph.D Cover lens A. Yes. Anti-reflective coatings are helpful in all 12 major customers are aware of our expertise in customized in electrical engineering from the OCA / OCR/ Air touch technologies, although projected capacitive stack solutions that address performance, as well as Touch sensor (x-ITO) touch is the main one. Projected capacitive touch University of German Federal Armed Touch Cover lens Touch manufacturing robustness for larger yield. Additionally, Sensor Glass Forces, where he developed ALD Sensor is found in approximately 90% of all touch devices our rotary magnetron sputtering approach and the Touch sensor (y-ITO) Touch sensor (xy-ITO) processes and equipment for high-k OCA / OCR/ Air Touch OCA / OCR/ Air given its multi-touch capability, manufacturability and process portfolio we have developed are designed for Polarizer Display Polarizer based CMOS technology. He joined smooth touch operation even in harsh environmental cost-effective deposition of highly demanding optical CF-glass CF-glass conditions. Invisible ITO supports all technology Applied Materials in 2010 and now is LCD LCD enhancement coatings. LC LC part of Applied’s PVD Display group concept variations of this mainstream technology, Dr. Thomas Zilbauer, Backplane Backplane These anti-reflective and invisible ITO solutions are in charge of touch screen technology, whether the touch screen is placed in or on top of the project manager, R&D PVD Standard projected capacitive P-cap “one glass” touch module offered on the Applied Materials Aristo platform, roadmap, and process development. touch screen film stack displays. In addition, it enables that technology to be Display, Applied Materials enabling touch screen manufacturers to further scaled to devices with 30-inch or larger displays. Figure 1. Examples of projected capacitive touch screen integration schemes. enhance the product portfolio for high-performance

22 Nanochip Nanochip 23 A time For this writer, a Spurred by competition comparable period of from GLOBALFOUNDRIES and 2012F SHARE intensity came in the mid- Samsung, and calls for more Top 5 Leaders Like No other 1980s, when the transition capacity from its top customers, Top 10 Leaders Sweeping Changes to CMOS coincided with TSMC has roughly doubled its Top 15 Leaders Japan’s investment push. capex spending in recent years, Top 25 Leaders U.S. companies bailed McClean said, shaking his head Challenge the Industry 87% out of DRAMs and into in wonder at the company’s 2005 SHARE 82% microprocessors. Trade change in spending behavior. Top 5 = 40% and the Technology 77% frictions boiled. IC Insights recently reported Top 10 = 55% 64% Ironically, Japan’s that the top three spenders Top 15 = 67% manufacturing excellence for 2012—Samsung ($13.1 Top 25 = 82% helped it dominate then, billion); Intel ($11.2 billion); while Japanese companies and TSMC ($8.3 billion) will Figure 1. 2012F Capital spending leaders’ shares of total worldwide are now figuring out how account for slightly more than semiconductor industry spending ($61.4B). Data source: IC Insights to adapt and survive half of the expected $61.4 in a gigafab era. Three billion in semiconductor capital decades ago, PCs drove expenditures forecast for 2012. before. What is striking now demand, while growth in If SK Hynix ($3.7 billion); and is that there are a lot fewer the current era is driven by GLOBALFOUNDRIES ($3.1 customers. As consumers, smartphones and tablets, billion) are added to the mix, we may all benefit from the products that didn’t even the five largest spenders will higher efficiencies created by exist in the mid-1980s. account for 64% of the total, the technology and scale of The myriad technical and according to IC Insights (see these large companies, but business challenges facing figure 1). the equipment industry must the semiconductor industry Chris Moran, vice president Figure 2. TEM of a 32nm develop sustainable ways make this a time unlike any of strategy at Applied Materials, gate-first HKMG device. Image to deal with ever-increasing other, according to analyst said the industry may have courtesy of GLOBALFOUNDRIES technology and business Bill McClean, president of faced a similar mountain of complexities,” he said. IC Insights. challenges during the transition semiconductor companies have Lithography expert Chris “Most people in to 300mm wafers and copper become more creative, coming Mack sums it up: “Only the the industry just don’t interconnects. “We’ve had up with techniques such as biggest players will survive, and realize how fast things these big technical changes strained silicon, replacement the survivors will get bigger.” are changing,” McClean gate high-k, and immersion said. Throughout most of lithography. Adding Process its history, there were a Strained silicon, for Complexity BY Has there ever been a time like this, with so many dozen or more companies example, requires new epitaxial which invested heavily, However, the greater deposition steps, and high-k/ David technical and business challenges facing the including half a dozen complexity of these new metal gate technology (see Lammers semiconductor industry almost simultaneously? Japan-based companies. technical challenges also makes figure 2) serves to reduce gate Now, investments have them expensive. In order to leakage while adding atomic The list is daunting: industry consolidation, concentrated largely in just a maintain performance and layer deposition (ALD). The few top players, while the so- reduce power consumption, drive to 20nm and 14nm will add EUV lithography, FinFETs, through-silicon vias, called second-tier companies have sharply moderated their Chris Moran, vice president of 450mm wafers, and new memory types. fab spending plans. strategy at Applied Materials

24 Nanochip Nanochip 25 A time Like No other Sweeping Changes Challenge the Industry and the Technology

lithography that will not achieve Kurt Ronse, chair of the sympo- Japan’s Future sensors and micro-controllers, the expected SRAM density sium and director of lithography for example, could be used to Bill McClean said several doubling. Later, if and when at imec, said the higher targets reduce energy consumption. of Japan’s semiconductor EUV becomes cost-effective relate to the expected sensitivi- The “Internet of Things,” with vendors are “adjusting their for the critical mask layers, ties of EUV resists, particularly home appliances linked to the business models, carving out those companies will jump to for the contact holes, which are Web, is another opportunity. their niches” in automotive a second-generation 14nm exposed with slower photore- Japan needs to encourage double patterning and additional ICs, NAND flash, mobile technology with true density sists, requiring more photons an entrepreneurial culture, etch steps, while high-mobility DRAMs, and the like. Other doubling, Van den hove said. and thus, more source power. Itow said, and not rely on the germanium and indium gallium companies, such as Fujitsu, EUV’s success is so critical The pressure is similarly “old conglomerates.” arsenide channels (see figure are deciding how they might that ASML, which has an high for creating an EUV mask Toru Watanabe, president of “I think they are picking 3) will require more epitaxial exit the chip business and effective monopoly in the EUV infrastructure. Stefan Wurm, a Applied Materials Japan the right areas to focus on for deposition. That will boost concentrate on their core demand for more process tools, field, was able to convince GLOBALFOUNDRIES assignee development,” she said. other suppliers in the U.S. and systems businesses. as chip makers redouble efforts its top customers to share to Sematech who runs the Asked about the mood in Europe, face challenges from Seven years ago, according to control process costs. the cost of next-generation Consortium’s lithography Japan, Watanabe said he sees lower cost vendors emerging in to IC Insights, Japan-based EUV and 450mm lithography program, said he is less worried an improving atmosphere Taiwan and South Korea. companies accounted for 4 development, selling shares to about source power now than the compared with the first Japan-based semiconductor 22% of worldwide capital InAs HEMT Intel, Samsung, and TSMC, with half of 2012. “Remember 2 challenges of getting defect-free µn ~ 13,000 cm /V-s companies are in the process investments. This year, Japan Intel’s investment potentially EUV mask blanks and patterned that earlier this year Sharp 3 of sharpening their focus on is on track to invest about reaching the $4 billion plus level. reticles. Franklin Kalk, CTO at stopped some of its display specific product areas, going 9% of the total (see figure 4), In0.53 GaAs Further, ASML’s planned Toppan Photomasks, agreed, manufacturing, and Renesas µ ~ 9,500 cm2/V-s 2 n from companies that “tried and McClean said he sees

cm/s] acquisition of Cymer, a supplier saying that the industry needs said it would close several of 7 to cover all areas.” Sony, for several of Japan’s chipmakers

[10 of EUV light sources, under- “zero defects in the 10–15nm its older fabs. Panasonic and

x0 continuing “a defensive v example, has become the 1 *Strain-Si scores the need to reduce risk range by the 10nm node. That Sony had huge losses in their dominant supplier of CMOS posture.” *Si nFETs and accelerate the introduction will be tough, because today we TV businesses. So it is quite V = 0.5 V DS (VDS = 1.1 ~ 1.3 V) image sensors for Nikon and Toshiba, along with its 0 of this complex technology. can’t find all of the defects which natural that people became 10 100 other leading digital camera NAND flash partner SanDisk, EUV source power, which print. EUV brings with it huge somewhat pessimistic.” Lg (nm) makers. And Toshiba will will build a 450mm fab at directly impacts the wafer per metrology challenges.” continue to invest in leading- some point, as they continue Figure 3. III-V improves performance at V =0.5V vs. Si. Data source: hour (wph) throughput of EUV dd edge tools for NAND flash. to, as McClean put it, “put SEMATECH scanners, is only one of the Japan Investment This year and next will their stake in the ground as a Other Companies North American major challenges facing EUV. Rebound 9% (9%) EUV Challenges prove to be an important leading-edge vendor.” Companies Hans Meiling, director of EUV 33% (29%) How will Japan-based transition period for Japan’s However, the yen-dollar European Companies Much less predictable product management at ASML 3% (8%) companies cope with the trend semiconductor industry, exchange rate puts Japan- than the industry consolidation Holding NV, said throughputs Japanese Companies to bigger leading-edge fabs, Watanabe said. “A lot of big based manufacturers in a trend is how the technical need to be at 70 wafers per 9% (22%) equipped at some point with things happened this year. tough position. With the yen challenges will play out, with the hour next year, with source 450mm tools and expensive Renesas said it will shut trading at about 80 yen to biggest question mark hanging power increasing to “full power” EUV scanners? down almost half of its fabs, the dollar, McClean said “it is over the commercial viability (200–250 Watts) by 2014 to Toru Watanabe, president and others will shut down tough for Japanese companies Taiwanese Companies of EUV lithography. If EUV reach 125–150 wafers per hour. 18% (19%) Korean Companies of Applied Materials Japan, said manufacturing as well. Next to compete” in cost-sensitive 28% (13%) throughputs lag, patterning will And the bar keeps getting Japan continues to supply many year will be a restart and consumer areas. be so expensive that companies higher for EUV. At the 2012 of the critical materials—ranging recovery time. There was not Joanne Itow, foundry may slow down the cadence of International Symposium on ( ) = 2005 Share from wafers to photoresists— much investment in Japan analyst at Semico Research, *Includes contract assembly and test houses Moore’s Law scaling, said imec Extreme Ultraviolet Lithography, and will remain a leader in that this year because of the said Japanese companies CEO Luc Van den hove. Already, held in Brussels in early October, area. And several of the world’s restructuring. Next year, we have opportunities as the companies plan to introduce the 25-member steering com- Figure 4. 2012F and 2005 share of capital spending. top equipment vendors are believe we are going to see a world shifts to new energy a first-generation 14nm mittee issued a surprising call Data source: IC Insights based in Japan, though they, like restart in investment.” paradigms. Combining node with double patterning for 500–1,000 Watts by 2016.

26 Nanochip Nanochip 27 A time Like No other Old But Faithful: 12,000 Sweeping Changes Early Production 10,000 Volume Production ALWAYS THERE WHEN YOU NEED IT Challenge the Industry Post Depreciation and the Technology 8,000

6,000 2012 4,000

$ Per 300mm Wafer $ Per 2,000 90 nm 65 nm 45 nm 32/28 nm 22/20 nm 14 nm 10 nm Fabulous Figure 6. Manufacturing cost for different nodes at three stages of production. Data source: Gartner tools

However, even after the yen, electrical generation will ever build 450mm fabs these public announcements, problems, and other issues, (see figure 5). Once the transi- the companies continued many Japanese people “have tion to 450mm production manufacturing and the impact become rather negative. for high-volume products is When Thomas C. Parolisi, presently M/A-COM Tech actually has a second E220 was less than expected. Then Business was crazy good until completed, one $10 billion fab equipment service group leader at M/A-COM system, S/N 374, which is used only for silicon. Elpida announced its merger 1992, but for 20 years the may be able to produce $30– Technology Solutions Inc. (“M/A-COM Tech”) S/N 1 is used exclusively for GaAs, and Parolisi with Micron, and the Japanese economy has not been so good, 40 billion worth of ICs, equivalent It’s a fair bet that after in Lowell, Massachusetts joined M/A-COM, Inc. noted that although S/N 1 has no backside coolant government and private equity even as other Asian countries in 1989, little did he know he was about to begin function, it isn’t desired anyway in this application to a tenth of today’s semiconduc- more than 40 years in firms said they may invest in keep getting better and better.” tor industry production. a relationship with a Varian medium-current because gallium is very fragile. Renesas. Demand for power “All of the Japanese people For the midterm, other business, Applied Materials ion implanter that would continue to this day. In From time to time the company has consid- ICs has remained strong, are trying to figure out what companies will stay on has semiconductor fact, that machine—serial number 1 (S/N 1), the ered eliminating one of the tools—the fab has prov- often in 200mm fabs, and Japan should be like in the next 300mm wafers but push first of 842 E220 EHP ion implanters that were en it could run both GaAs and silicon processes on production tools installed Japan’s continued strength 10 or 20 years. What everyone transistor scaling (see figure ultimately manufactured—recently celebrated its the same tool. S/N 374 is run at high dosing levels, in automobile production agrees on is that Japan needs 6). “Equipment companies in virtually every fab in the 25th anniversary. and therefore more maintenance is required, so supports demand from Japan- to change.” will have to develop two more world. So at any moment of M/A-COM Tech is a leading supplier of a motivation for replacing the older medium- based IC suppliers. nodes of leading-edge 300mm high-performance analog semiconductor solutions current S/N 1 with a higher-current model would any day, somewhere on the for use in radio frequency (RF), microwave, and be that a higher-current implanter would reduce “Supply and demand came Expensive 450mm tools, even after 450mm planet someone is building into better balance than in the Transition manufacturing gets started. millimeter wave applications. Its Lowell facility maintenance requirements and also would lead to early half of the year, and we That will be wildly expensive semiconductors on an fabricates gallium arsenide (GaAs) and silicon- lower operational costs, because one tool could One worrisome topic, still are ready to do more business and the industry will have to based components. conceivably run both GaAs and silicon processes. under debate, is whether the Applied Materials system. next year,” Watanabe said. The investigate more productive Parolisi recalls that his first assignment was However, Parolisi said, “We prefer not to put all our semiconductor industry can bigger challenge is that in the R&D methods to keep our cost This got us wondering to assist in moving the tool and other equipment eggs into one basket,” and so S/N 1 is still in use. continue to deliver on the 30% from its original owner, Adams-Russell Electronics, The E220 was the precursor to the E500, face of the high valuation of in line with the opportunities,” about whatever happened per annum reduction in the Moran said. to M/A-COM Tech. Prior to the move, Parolisi had a higher-energy version designed to meet new cost per function at the heart of to all those tools we sold to run the tool for 24 hours straight to build up an requirements for emerging process requirements. That attitude—that the chip industry’s success. If years ago. inventory of wafers because it wasn’t going to be The single-wafer platform of the “E-Series” 80 somehow the semiconductor 76 it costs more to make tomor- installed immediately—installation costs were high medium-current tools led to the single-wafer 70 71 industry will figure it out, 60 row’s transistors, with EUV and at the time and there wasn’t yet a clean room for VIISta platform, which all four of Varian’s dealing with its challenges as 50 process complexity as the lead- it. As he remembers, the tool was finally installed semiconductor products—medium current, it always has managed to do— 40 ing causes, will revenue growth in the summer of 1991 after the company found high current, high energy and ultra-high dose— 30 seems to prevail. “Forty years 31 30 continue its upward trend? it was unable to get reliable product from off-site currently utilize. There is an active installed base 20 of scaling have shown that, Number of Companies 10 The largest semiconduc- vendors doing the implant. of 729 E220 models in the field, which Applied 7-10 ultimately, people find a way,” 0 tor companies have turned to Many upgrades have been installed on continues to support with parts and services. 200mm Fab 200mm Fab 300mm Fab 300mm Fab 450mm Fab Moran said. Owners Owners Owners Owners Owners the 450mm wafer transition as S/N 1 over the years, as might be expected with “The tool has never been a limiting factor in (Max in 2008) (Current) (Max in 2008) (Current) Potential one answer to wafer processing a tool of this vintage, “It has most of the bells and what we could get out of the fab,” said Parolisi. Veteran journalist David Lammers, Got a FABulous story about Each member of joint-venture companies counted separately costs, environmental impacts, whistles of any new tool out there and we consider “It’s kind of like Old Faithful—it’s always there formerly Tokyo Bureau Chief for a production tool legend? and fab throughputs. However, Share it with us at it state-of-the-art,” said Parolisi. “The reason we when you need it.” Figure 5. Number of companies with 200mm vs. 300mm fabs. Data Electronic Engineering Times, Moran said the view at Applied [email protected]. don’t replace it? It does the job just fine.” The tool source: IC Insights’ Strategic Reviews Online database has covered the semiconductor Thanks to Debra Vogler, president of Materials is that only a few com- is also unique in that there isn’t another tool of the industry since 1985. Instant Insight, Inc., for support of this story. panies—five or six at the most— same vintage in the entire fab. “For a tool to still be running in good operating condition after all these

28 Nanochip years is pretty amazing,” said Parolisi. Nanochip 29 Cycle Time Operational Flexibility: Cycle Time Reduction & Multiple lots per carrier and/or fewer wafers Operational Flexibility per carrier. Get new products to customer much faster.

Ouput Per Tool Must Increase: More Good Wafers Out Per Tool Find breakthrough solutions that result in significant increases in good wafer out and SPOTLIGHT ON increased OEE (eg: APC, e-Diag)

The 300mm factory is much more automated Highly Automated Factory and must be designed to transport hot-lots and ITRS ROADMAP hand-carry’s.

ITRS FACTORY INTEGRATION UPDATES Reduce Time to $$$/Cycle-time reduction: Reduce Time to Money What are stretch goals for cycle time from AIM TO BOOST FAB EFFICIENCY ground-breaking to first full loop wafer out. How to achieve quicker shrink?

By The International Technology Roadmap for Semiconductors (ITRS) is Increased Floor Space E„ectiveness: probably the single most important document governing the direction of the Don’t want each new generation to drive big James Factory Size Is Becoming An Issue increase in cleanroom size, especially since fab semiconductor manufacturing industry. The roadmap’s guiding principle is to is segregated Cu/non-Cu and new metal layers Moyne keep the industry on pace with Moore’s Law by maintaining the decades-long added at each node. trend of 30% per year reduction in cost per function. Figure 1. ITRS factory integration requirements drivers.

The roadmap sets targets for future manufacturing The entire ITRS is updated every odd year. Major FI difficult challenges beyond 2019 Some potential solutions cited in the latest roadmap capabilities, identifies areas where technologies don’t revisions made during 2011 were published in 2012. The 1. Meeting the flexibility, extendibility, and scalability include: exist to meet specific capabilities, and highlights 2011 FutureFab publication summarizes the events of the needs of a cost-effective, leading-edge factory ■■ Designed-in APC inside or outside the tool, [1,2] emerging technologies that could be harnessed to 2011 major ITRS revision year. Because only minor 2. Managing ever-increasing factory complexity communicating with a fabwide system meet them. revisions were made in 2012, this article will summarize 3. Increasing global restrictions on environmental ■■ Fingerprinting and equipment health monitoring The roadmap is divided into chapters representing the 2011-12 chapter structure and provide a glimpse into issues [3] ■■ the various aspects of semiconductor manufacturing. plans for 2013. 4. Post-conventional CMOS manufacturing Enhancement of equipment systems to support move The factory integration (FI) chapter focuses on uncertainty from reactive to predictive enterprise systems that are designed and integrated FI ACTIVITY FOCUS 2011-12 Some issues cited as making these challenges ■■ A common prognostics and health management for efficient, effective development and manufacturing. The chapter’s factory integration requirements drivers difficult include: (PHM) capability across tools Semiconductor FI experts from around the world ■■ are summarized in figure 1. Integration of fab and facility management control ■■ Standardized equipment data model make up an FI Technology Working Group (TWG) to The chapter breaks up the list of FI difficult challenges ■■ evaluate the challenges, determine near- and longer Lack of and the need for increased emphasis on ■■ Built-in chamber matching: movement from chamber into shorter term (through 2019) and longer term sections, term technology requirements, and set forth potential communication standards variance reporting to chamber variance correction as follows. solutions. ■■ Maintaining availability and productivity A review of the 2011-12 FI chapter shows that FI TWG The FI TWG is currently organized into five teams. FI difficult challenges through 2019 ■■ Supporting the move from reactive to predictive efforts are strongly focused on topics such as moving Each team is concerned with one of the following: 1. Responding to rapidly changing, complex business systems from reactive to predictive, integration (for example, 1. Factory operations requirements fab and facilities), and mechanisms for improved control FI potential solutions to address these challenges, 2. Production equipment 2. Managing ever-increasing factory complexity and repeatability. meanwhile, are presented both through narrative 3. Automated material handling systems 3. Achieving growth targets while margins are declining The 2012 ITRS roadmap provides a complete pre- and via tables that define the relevant technologies. 4. Factory information & control systems 4. Meeting factory and equipment reliability, capability, sentation of the challenges, issues, and potential solution A timetable also is given for the migration of these 5. facilities and productivity requirements per the roadmap roadmap for FI in semiconductor manufacturing. To down- technologies from research through development, 5. Emerging factory paradigm and next wafer load the roadmap, visit http://www.itrs.net and follow the qualification and pre-production, and ultimately size change appropriate links. continuous improvement.

30 Nanochip Nanochip 31 SPOTLIGHT ON ITRS ROADMAP ITRS FACTORY INTEGRATION UPDATES to grow in importance. Concepts such as predictive SUMMARY maintenance, predictive scheduling and metrology AIM TO BOOST FAB EFFICIENCY The FI chapter of the ITRS focuses on integrating prediction (“virtual metrology”) will be expanded factory components to efficiently produce the required to support yield prediction and fab component products in the right volumes on schedule while meeting simulation in lock-step with reality. The roadmap will cost targets. Over the past two years this chapter has been draw heavily from other industries and focus not only updated to focus on prediction, facilities integration, and on prediction technologies, but also on migrating technologies across these domains and promote other technologies that will be required components of the LOOKING AHEAD TO 2013 existing systems to “prediction-ready” systems. smooth FI migration from 300mm to 450mm fab of the future. As we move into the 2013 major revision year, a technologies. ■■ Rethinking key performance indicators (KPI). A good As we move into 2013, another major revision of the number of changes to the FI chapter and even to the FI example is the need to define the wait time waste FI chapter is being considered. This revision will better TWG are being considered. Here is a summary. ■■ Looking outside the semiconductor industry. metrics for equipment productivity, currently a SEMI address FI challenges in the information age by eliminating Considering the acceleration of information Eliminate the “Silo-ing” of Specifications standardization effort. (SEMI is a standards body for roadmap silos and looking at common technology technology in recent years, FI more than any other As mentioned, the FI chapter is broken into the semiconductor manufacturing industry.) solutions across the FI space. ITRS chapter must consider solutions from other subchapters (figure 2), each with its own set of roadmap ■■ industries. Challenges such as moving from reactive New control paradigms. Centralized control is specifications. This approach was appropriate for the For additional information, contact james_moyne@ to predictive, big data, and supply chain integration being questioned in other industries and should 1990s and 2000s, but the information age has forced amat.com are pervasive across all of manufacturing. The be addressed in the FI roadmap. The possibility of a reevaluation. semiconductor industry must accelerate its adoption autonomous control (“autonomous agents”) should For 2013 it has been proposed that these “silos” be Acknowledgments: We are grateful to all members of the FI of general manufacturing solutions. be considered, and predictive control should be eliminated, and information technology be presented explored as part of the movement from reactive to TWG, especially Dr. Gopal Rao, for supporting the group’s ■■ A more data-driven approach. The advent of as common to all areas. This will highlight technological predictive. Control performance should be quantified. work and contributing to the FI chapter content. concepts such as cloud computing and autonomous commonalities across the fab and facilities, and even Time-based (i.e., time-synchronized) control should agents is part of a larger movement toward data- [1] up-and-down the supply chain. It will promote a stronger be considered in some instances. R. Oechsner, “ITRS Chapter: Factory Integration,” FutureFab level of integration and standardization, and also will allow driven solutions. The FI chapter may be reorganized to International, Issue 40, January 2012. ■■ A stronger focus on technology ramps and costs. [2] www.itrs.net. for consistent incorporation of non-nanomanufacturing FI promote commonality of data-driven solutions across As technology cycles get shorter, the importance [3] J. Moyne, “International Technology Roadmap for technologies into the roadmap. all elements of the FI space. of technology ramp speed and cost grows. Specific Semiconductors (ITRS) Factory Integration Chapter Update: The net result of this fundamental change to the FI ■■ Addressing the big data problem. The amount challenges, solutions and metrics for technology ramp 2013 Major Revision Plans,” (invited), APC Conference XXIV, chapter is that subchapters will likely be reorganized or of data available today delivers benefits but also should be considered. For example, the integration Ann Arbor, Michigan, September 2012. eliminated, probably along data-driven boundaries rather creates challenges in dealing with data sizes of process control and design for manufacturability than physical partitions. and rates. These challenges aren’t unique to the techniques should be considered to reduce the semiconductor industry, though, and a roadmap is New Challenges and Potential Solutions number of redesign cycles in a new technology needed that addresses the big data problem while About The Author 2013 updates likely will focus on continued emphasis ramp-up. also aligning the semiconductor industry with other James Moyne is the standards and technology specialist of some of the 2011-12 concepts, but will also introduce ■■ manufacturing arenas. FI technologies as barriers. The importance of for Applied Global Services at Applied Materials, and new challenges and potential solutions. FI technologies continues to grow in the fab to ■■ also is an associate research scientist in the department ■■ FI solutions for 300mm and 450mm. FI requirements An increased focus on moving from reactive to the point that, in some cases, these technologies of mechanical engineering at the University of Michigan. and solutions for 300mm and 450mm should be predictive. This concept has been accelerated in the might be barriers to achieving the next technology He has been a member of the FI TWG within the ITRS fundamentally the same to allow for leveraging of FI chapter over the past few years and will continue node. For example, process control (e.g., run-to- for four years and is expected to chair the FI TWG for run control), once an add-on technology, is now a 2013-14. For the last two years, the FI TWG has been required technology in most 300mm processing. chaired by Dr. Gopal Rao of Intel, who will remain For some emerging technologies it’s a prerequisite active in the FI TWG to facilitate a smooth transition of to achieving necessary yields. Such critical FI leadership and provide invaluable technical input. Also, technologies must be identified and a roadmap for it is expected that Dr. Jonathan Chang from Taiwan them devised, in order to keep pace with the overall Semiconductor Manufacturing Corporation (TSMC) Factory Production Factory Information AMHS Facilities ITRS technology requirements. will serve as co-chair, with the aim of succeeding Moyne Operations Equipment & Control Systems in the leadership position in 2015.

Figure 2: 2011-12 Factory integration subchapters organized by technical focus.

32 Nanochip Nanochip 33 A review of data from models are exercised during run- 5. multivariate prediction When WB occurs, a a solar-panel manufacturer time to determine if and when model development number of sensor stastics show showed that wire breakage maintenance is needed. The reduced data set from large value spikes immediately (WB) accounts for 25% of all The predictive model step 4 is used to develop before and/or after. For failures on a particular tool set. development process consists multivariate models. As the purpose of meaningful WB typically occurs multiple of the following steps: part of this process, simple prediction, this data was times per month and results in 1. Collection and preparation univariate limit models filtered out as part of the data- a total downtime of 1 to 2 hours of historical data are employed to develop a strengthening process because per tool per month. Additionally, FDC and SPC statistics are multivariate limit model. In it is only useful for notification. quality yield, a fundamental collected along with tool future works, more advanced The remaining data is divided driver of total cost of ownership, maintenance and yield techniques such as partial into three categories: WB failure, is a challenge; yield levels lower information. The data set least square (PLS) and “other” (i.e., non-WB) failure, than 90% were observed 32% must be of sufficient length support vector machine and “good,” representing normal of the time, causing 74,000 so that a stastically significant (SVM) will be employed. process runs. wafers lost per tool annually. number of WB and varying To determine which are the Consequently, there is qualities of yield are observed, Predicting WB important sensor statistics, we strong interest in the ability to and must be categorized to used univariate and multivariate CUT SOLAR COSTS In applying the predictive predict and prevent both WB indicate which data belongs analysis iteratively. We selected maintenance (PdM) process to and low-process yield. to good or bad runs. The data potential sensor statistics that predict WB, the goal is to predict AND INCREASE YIELD also may need filtering; for correlate with WB, and filtered WB hours in advance. To this DEVELOPING example, to remove the impact out those with very low variation end historical data was collected WITH BETTER PREDICTION PREDICTIVE MODELS of external events that might or with a high correlation over 1 month from 38 tools, each FOR WB AND YIELD hide the prediction signal, or to to a sensor statistic we had OF WIRE BREAKAGE with 133 sensors, and this data remove data from immediately already selected. PLS was then When impending breakage was merged with maintenance before breakage that might employed iteratively to rank By Silicon accounts for approximately 20% of the total cost of a or poor yield is predicted information. For each sensor, hide or “swamp” the long-term the sensors and determine a during normal operation, that hourly minimum, maximum, multi-crystalline solar module. Manufacturers are now looking prediction signal. reduced set. The result is a set jimmy information can be used to mean, range and area statistics of sensor statistics (see figure plan maintenance and avoid 2. Data merging were calculated, and the data for ways to reduce this cost as much as possible. One strategy is 2) that collectively provide a iskandar disruptive, unplanned system Historical tool and analyzed as described above to promising distinction between stoppage and conditions that maintenance data must be develop predictive models. and to improve the yield of the wafering process, which depends on WB data and normal data. cause yield loss. This prediction [1] aligned, usually with time as James Moyne the wire saws that slice silicon bricks into wafers (see figure 1). capability can reduce downtime, a key parameter, and yield wafer scrap, overall system measurements merged with disruptions and maintenance the tool data. PLS Loading costs, thereby lowering the Upper Ingots 3. Data strengthening Table overall cost per good wafer out. Wire The merged data is analyzed 0.2 Slurry Web Predictive models are Manifolds and, wherever possible, its Inlet developed by leveraging quality is improved using 0.0 Spool automation software solutions techniques such as outlier such as Applied E3 fault removal, data overlays, Loading -0.2 detection and classification interpolation, and categorizing. (FDC) or statistical process Takeup -0.4 Spool control (SPC) systems. 4. Data reduction to determine Historical tool data collected important sensor statistics Top Sensors via these systems is analyzed The large data set is analyzed Sensor Type Lower using a variety of multivariate Table to develop multivariate Before Cut After Cut prediction models that relate techniques to determine which equipment state information sensors are most important to Figure 2. PLS loading, by indicating the strength of the parameter Figure 1. Wire saw system on left, cutting assembly on right. to maintenance events. These the prediction process. contribution, points to the top-ranked sensors contributing to the signal.

34 Nanochip Nanochip 35 Cut Solar Costs and Increase Yield rise causes a big viscosity drop. the yield-prediction process: yield loss 68% of the time For additional information, As a result, the wire exposes bearing box water cooling Bearing Box (see figure 7). The result is a contact jimmy_iskandar@ with Better Prediction Water Cooling itself directly to an ingot, amount area, water cooling Amount Area net savings of $41,000 per amat.com or james_moyne@ of Wire Breakage creating friction and potential amount area, and slurry amat.com 39% tool per year, not including failure. DC bus voltage is the cooling minutes. These improvements related to higher power supply to the motor, were picked because (1) overall yield, lower scrap, and [1] Iskandar, J., Moyne, J., Schwarm, A., and Liu, H. and sharp fluctuations in it they have a high ranking 3% 16% lower maintenance costs not cause motor instability—again in the rules ensemble data quantified in this study. (2012), Predictive Maintenance 10% creating disruptions in the wire reduction process and a low of Wire Breakage and Quality Yield of Wire Saw Tools with movement through the ingot. correlation with each other; 14% 18% Conclusion 0% Multivariate Limit Model, 27th Top Sensors Scatterplots (2) they agree with process Water Cooling Slurry Cooling Both PdM and predictive European Photovoltaic Solar 0 2 4 6 8 knowledge as determined Predicting poor Yield Amount Area Minimum yield have great potential to Energy Conference (EU PVSEC), 8 through consultations with Yield data from 162 impact cost of ownership in September, 2012. 6 process experts; (3) they [2] Friedman, J. H. and Popescu, r = 0.36 r = 0.08 full-load (full capacity) cuts nanomanufacturing. These Slurry Temp. Range 4 can be predicted with a limit B.E. (2008). Predictive Learning across 17 tools were used Figure 5. Quality yield prediction contribution from univariate models. capabilities are an important 2 model; and (4) they are easy via Rule Ensembles, The Annals for the yield analysis. Hourly part of Applied’s prediction 0 to inspect. of Applied Statistics 2008, minimum, maximum, mean, strategy, which will leverage It makes sense that these Once we identified these good yield). Therefore we Vol. 2, No. 3, 916–954 DOI: 8 range and area statistics were our E3 automation and sensor statistics would relate to “high impact” sensors, we concluded that univariate 10.1214/07-AOAS148, Institute 6 calculated for the 133 sensors. equipment engineering of Mathematical Statistics. r = 0.36 r = 0.21 yield prediction. For example, created a yield-prediction limit DC Bus Voltage models could be used 4 The data was merged with the system capabilities to support Range when the rotation precision model for each sensor statistic. effectively in this instance. The 2 yield data, and categorized as customers as we move from a of a bearing box decreases, An alarm is sent when a sensor model outputs were combined low, normal, or high yield (see reactive to a predictive mode of 0 each cut generates more heat statistic is above its limit. so that, in the case of multiple 15 figure 4). This categorization fab operations. and more cooling water is (With successive alarms, only models generating alarms, only provides contrast as to r = 0.08 r = 0.21 10 needed for the bearing box. the first is sent because only one alarm was reported. Cooling Water Flow which sensor statistics are one alarm is needed per cut.) Range Therefore, the total amount 5 associated with high variation WB Prediction Rate 58% of cooling water needed for A high number of false alarms Results in yield. one cut will increase. Slurry (i.e., an alarm is sent, but Non-WB Failure Prediction Rate 56% 0 A technique called “rules For the PdM application, 0 2 4 6 8 0 5 10 15 temperature rises after a cut the cut nevertheless results False Positive 4% ensemble” was employed the WB prediction model could and a nonoptimal cut generates in high yield) is permissible Tools Without Model 19% to rank sensor statistics in be applied to 81% of the tools. more heat. Therefore, heat because tool inspection can Figure 3. Illustration of low correlation among top sensor statistics. order of their importance in Models for the remaining 19% Median WB Prediction Time (hours) 40 generation indicates a be done following the cut, the determination of yield.[2] couldn’t be developed given Median Non-WB Failure Prediction Time (hours) 50 suboptimal operating condition and inspection of these The matrix of plots However, there were a number Three highly ranked sensor- an unacceptably high rate that results in lower yield. three sensors is nonintrusive WB = wire breakage failures in figure 3 shows that of false positives (i.e., false of false positives. When we statistics were picked for and inexpensive. Non-WB = non-wire breakage failures applied the model it predicted the parameters have low indications of WB). To reduce Figure 5 summarizes Tools without model = % of tools for which wire-breakage prediction models could WB occurrences 57% of the not be developed correlation (the off-diagonal them, we suppressed any alarm the contributions of the time at a median of 40 hours Figure 6. WB prediction results. plots have low ‘r’ values, that appears within a fixed time Yield Distribution individual univariate models in advance, with a 4% false indicating little correlation frame after a previous alarm. High to overall quality yield 80 Yield positive rate (see figure 6). between pairs of sensor (The timeframe was derived prediction. Overlap regions statistics). This means that from a process MTBF analysis.) Normal Note that this means—for Prediction Accuracy 68% Yield show duplicate predictions each of these sensor statistics The resulting combination of these tools—over half the Tool Participation 71% 60 between models. While there unscheduled downtimes and brings a unique contribution to multivariate prediction and Low Yield (32% of all cuts) is overlap between the models, False Positive 77% the prediction process. suppression of false alarms related scrap associated with the majority of the prediction Average Saving Per Tool Per Year $41,000 WB events are eliminated. The We analyzed the represents the PdM model. 40 space (39%+18%+14% = 71%) contributions and determined Why these two particular solution also predicted other Tool participation = the number of tools participated in prediction; those which do participate are Frequency can be predicted effectively that combining two sensor statistics? It makes sense that failure modes as well. The total due to unacceptably large number of false positives with univariate models and Average saving per tool per year = 10% yield loss * prediction accuracy (68%) * tool participation 20 downtime saving per month statistics—slurry temperature these two are important to WB an analysis of the remaining (71%) * percent low yield (32%) * 2300000 (number of cells produced per year) * $1.15 (price per tool is 5.9 hours, which per solar cell) and DC bus voltage—produced prediction. Slurry temperature prediction space revealed that a good prediction model. has a major impact on slurry translates into $26,000 per Figure 7. Quality yield prediction result. 0 the univariate models did not tool per year. viscosity—a slight temperature provide conflicting predictions 40 50 60 70 80 90 100 The low-yield prediction Yield Percentage (i.e., one predicting bad yield model predicts and enables and the other(s) indicating Figure 4. Quality yield histogram. prevention of impending

36 Nanochip Nanochip 37 At the 2xnm node, dopant activation and defect creation in the Silicon Surface extension, source-drain junction, and A/C Surface contact regions can impede scaling. Crystalline Silicon Logic devices require a high-k/ metal gate architecture that requires RT -100°C additional process steps and (a) demands stringent process controls. Silicon Surface Equivalent oxide thickness (EOT) A/C Surface scaling and gate leakage challenges drive the need for atomic layer Crystalline Silicon -20°C ° ° deposition (ALD) of high-k dielectric RT -40 C -100 C (b) gate stacks. For DRAM devices, new Applied Materials internal data deep plasma processing is required Figure 1. Cross-sectional TEM images for (a) boron 2keV 3e15/cm2 at RT and -100°C; to enable higher dose nitridation (b) carbon 5keV 1e15/cm2 at RT, -20°C, -40°C, and -100°C reveal thicker amorphous without increasing leakage current layers and smoother a/c interfaces with cryo-implantation. The effect is more evident or transistor threshold voltage. High as temperature decreases. aspect ratio (HAR) etch faces the most demanding requirements to optimize performance of n- and beyond the amorphous/crystalline date for critical dimension (CD) p-type devices is subject to interface.[3] (See figure 1.) Fewer uniformity and profile control in relaxation from implant misfit and defects formed upon annealing addition to new specifications for threading dislocation propagation greatly reduce dopant diffusion 3D structures. after high-temperature dopant- and deactivation. In addition, TRANSISTOR AND Scaling is also challenging [1,2] activation annealing. Defects, defect reduction preserves strain interconnect technologies. Dielectrics which commonly form at the and minimizes potential junction are becoming more porous in pursuit implant boundary during annealing, leakage pathways. of lower values, yet must withstand κ can become nucleation sites for Shallower junctions and smaller INTERCONNECT stresses from extensive downstream dislocation formation or aid in gate pitch require balancing needs processing and advanced packaging the inter-diffusion of boron and for a deeper SDE to lower resistance steps. Feature size is such that germanium that, in turn, can and a shallower SDE to improve ionized physical vapor deposition ADVANCES accelerate this detrimental strain short channel effect performance. (PVD) cannot guarantee the required relaxation. Contact areas become Conventional nMOS contacts coverage and void-free metal gap so small that contact resistance can have been made using arsenic ion filling for electroplating. severely inhibit device performance, implants, but smaller contact areas SMOOTH THE WAY Fortunately, advances in challenging integration and process at advanced nodes dictate greater transistor- and interconnect-related engineers to increase dopant active dopant abruptness and technologies for 2xnm and beyond TO THE 2xnm NODE activation without incurring major higher concentrations to reduce are proving successful in overcoming process changes. series resistance. Phosphorus is an the above challenges. Ion implantation has evolved on attractive alternative to arsenic; co- several fronts to address these issues. implantation with carbon at −100˚C As scaling continues to the 2xnm node, planar transistor TRANSISTOR CHALLENGES In particular, cryo-implantation (at overcomes the limitations of pure AND ADVANCES temperatures as low as −100˚C) phosphorus implantation and enables combined with energy-pure dopant very abrupt, low-resistance junctions. fabrication faces growing challenges. This has prompted Cryogenic Ion Implantation profiles and special species, such as Cryo-implantation improves a transition to 3D architectures for leading-edge devices At advanced nodes, ultra- carbon and germanium, is proving nickel silicidation interface qualities, shallow junction formation in the versatile and effective in creating reducing the roughness that results while other innovations stretch extendibility of planar source/drain extension (SDE) ultra-shallow junctions with minimal when pFET channel stress-enhancing requires extremely abrupt profiles, damage, improved activation, and germanium concentrations exceed scaling to the ultimate extent. Both paths forward involve aided by the elimination of energy reduced leakage. Cooling the wafer 25%.[4] Cryo-implantation also contamination in the implanted to cryogenic temperatures during makes it possible to meet pMOS greater manufacturing complexity and sophisticated profiles as well as means to implant promotes amorphization depth and abruptness requirements engineering of materials and interfaces. suppress diffusion. Beneficial strain at lower doses and to greater depth by trapping interstitials and limiting incorporated to independently with fewer target interstitials left nickel diffusivity.

38 Nanochip Nanochip 39 with industry-standard HDP-CVD consistent, vacuum-controlled a fundamental challenge for very high INTERCONNECT CHALLENGES silicon dioxide and ensures the queue time between each process aspect ratio etch. The two key ap- AND ADVANCES absence of fixed charge. step. The necessary increase in the proaches are an oxide-poly alternat- TRANSISTOR AND Low- Dielectrics The low thermal budget (<150˚C) κ-value of bulk HfO2 is achievable by ing stack and an oxide-nitride alter- κ INTERCONNECT process sequence also gives flowable incorporating a κ-boosting element, nating stack with wet etch removal of As geometries shrink, the ability ADVANCES CVD the compelling advantage of such as titanium, into the matrix the nitride for tungsten filling. to increase device signal speed is liner-free integration compatibility during deposition. Critical dimension uniformity significantly affected by the dielectric SMOOTH THE WAY with tungsten and titanium nitride For DRAM, scaling the peripheral and vertical profiles are especially constant (κ) of the insulating TO THE 2xnm NODE metal films used as electrodes, gate is essential for advanced high- critical (i.e., high bottom-to-top CD materials between the copper contacts, and conductive lines. These performance, low-power devices ratio, absence of bowing or bending, interconnects. For ideal electrical Dielectric Gap Filling W Selectivity Vertical Profile films are prone to oxidation during but current nitridation processes and distortion-free bottom holes). In performance, the effectiveκ -value Chemical vapor deposition low-temperature steam annealing. are limited in achieving the optimal addition, for the staircase contact, it (κeff) of the inter-level dielectric (ILD) Figure 3. Critical 3D NAND staircase etch. (CVD) has historically enabled For electrodes and narrow conductive leakage and threshold voltage. A is essential to avoid punch-through and associated barrier films must

void-free filling of pure, dense oxides lines, such as buried bit and word lines high-temperature, high-power NH3 of the gate tungsten. In other words, scale correspondingly. In addition, for metal isolation with minimal in advanced DRAM, the resulting re- nitridation process with pulsed the tungsten layer at the top of the advanced packaging techniques and copper oxide removal prior to barrier leakage and no parasitic capacitance. sistance change can jeopardize device RF plasma resolves this issue by staircase will experience more than the trend toward lead-free solder deposition can disrupt the chemical With continued scaling, though, function. Consequently, depositing generating the higher nitrogen doses 300% over-etching, effectively make chip packaging interaction structure at the surface of low-κ conventional interlayer dielectric flowable CVD oxide directly on metal needed for the 2xnm node without increasing the selectivity requirement increasingly important for high yields. film.[9,10] This, in turn, can adversely

(ILD) CVD faces severe challenges of without a nitride liner reduces integra- degrading leakage and threshold to >350:1. Lead-free solder materials exert affect the finalκ eff of the device such smaller features, higher aspect ratios, tion complexity, allows implementa- voltage. High power compensates for A new triple-frequency greater stresses on the packaged chip that the benefit of lower-κ materials re-entrant profiles, and reduced tion of novel device architectures, and the lower nitridation rates associated capacitive-coupled etch system and in the interconnect.[7,8] Achieving is not fully realized. At 2xnm and

tolerance for thermal and oxidative offers a means to scale devices to with NH3 plasma. Pulsing delivers addresses these aggressive etch κ ~2.2 for scaling to 2xnm and below beyond, preserving the bulk dielectric treatments. narrower pitch. a “soft” plasma at higher RF power performance requirements using necessitates re-engineering the constant is essential for reducing Flowable CVD technology and temperature. Combining these a unique very high frequency dielectric’s composition and structure cross-talk noise and RC delay. ALD High-κ Dielectrics overcomes these challenges, enabling conditions with an integrated post- source, optimizing RF delivery, and to withstand downstream process A novel κ-treatment process Although ALD high- dielectrics profile-insensitive, void-free gap filling κ nitridation annealing on a common innovatively coupling different bias steps while retaining essential restores the desired chemical bonds. relieved the EOT scaling roadblock of reentrant gaps with diameters platform delivers superior nitridation. frequencies. The source enables mechanical properties. It also Introducing a carbon-containing when SiON reached its limit,[5] less than 7nm and aspect ratios Furthermore, a unique feature of high etch rates and throughput in requires treatment of the dielectric reactant in the presence of an energy extending Moore’s Law to 2xnm exceeding 50:1. The process involves the NH chemistry is the formation hard mask etching, and high plasma following these other processes to source creates an active supply and beyond now challenges high- 3 the reaction of a carbon-free silicon κ of NH radicals in the plasma, which density and polymerization for the preserve desired chemical, electrical, of the methyl group for restoring logic gate stack scaling. Fortunately, precursor and inorganic reactant is typically associated with greater dielectric etch process. and mechanical attributes. the disrupted Si-CH bonds and proven solutions are available. 3 gas that produces condensation process conformality. As device Innovatively coupling high and New chemistry enables the accelerates the treatment cycle. The The oxide interface layer (IL) has of a low-viscosity film upon the structures transition to 3D, this low bias frequencies achieves the necessary material re-engineering, energy treats both the surface of a low value; therefore, reducing wafer substrate. The film flows κ property may facilitate new nitridation required dielectric etch rate, profile, enhancing the mechanical the film and several monolayers of its thickness will produce a large to the bottom of gaps, producing applications using NH plasma. and uniformity. High frequency bias strength contributed by the carbon the dielectric, which promotes bulk effect on overall EOT. Both rapid 3 true bottom-up filling. Carbon-free improves plasma density and ion backbone structure in contrast film robustness. The ILD thus retains thermal oxidation and radical HAR Etch chemistry creates high-density, non- energy control to optimize ARDE. to the weakening effect typical of its chemical properties without oxidation processes offer a means Emerging 3D architectures are porous silicon dioxide comparable Step-to-step wafer temperature methyl in existing organosilane weakening its dielectric performance to scale the IL below 8Å,[6] while intensifying demands placed on etch control facilitates precise polymer chemistries. As with earlier low-κ and the key structural properties of scaling to 2Å can be achieved with processes, including very high aspect management to simultaneously films, the engineered, nano-porous modulus and hardness. LT RadOx 5s 1%H2 9 radical oxidation (N2O/H2) in a ratio (>50:1) etch requirements, LT RadOx 60s 1%H2 achieve very high aspect ratio etching ILD is cured with ultraviolet light to 8 controlled and repeatable fashion high throughput, and very high Copper Barrier/Seed and very high tungsten selectivity. drive out the labile species and set 7 with a thermal budget compatible tungsten selectivity in the case of 3D Incremental enhancements of 6 This “active” temperature control the desired mechanical strength Chem-Ox with either gate-first or gate-last NAND staircase contacts (figure 3). both barrier/seed and electroplating 5 avoids the temperature creep with (elastic modulus and hardness). As 4 sequences (figure 2). The -value of The advent of 3D NAND has also processes have enabled void-free κ plasma thermal load that would an added benefit, the new chemistry 3 IL Thickness (Å) IL Thickness the ALD HfO2 layer can be increased increased the aspect ratio of mask copper gapfill as far as the 2xnm node. 2 severely limit conventional wafer results in a significantly thinner HF-Last through post-deposition plasma etching and requirements governing Beyond this, however, ionized PVD 1 cooling systems in managing the transition layer between the barrier nitridation and annealing, reducing mask etch rate, selectivity, and cannot ensure that barrier/seed layers 0 multi-aspect ratio staircase etch. and bulk low-k film that lowers 450 500 550 600 650 700 750 800 deformation. achieve the requisite coverage for Temperature (°C) the EOT by a further 1-2Å. Wafer temperature tuning also allows overall κeff, enhances adhesion, and For ultra-thin to zero IL formation The common element among electroplating, making void-free gap for controlling sidewall passivation strengthens the interface. Figure 2. Radical oxidation enables controlled, repeatable (beyond 2xnm), integrating dry 3D architectures is a stackable device filling extremely challenging. Even the during mask etch, thus enabling in Plasma etching, photoresist IL scaling to 2Å for both gate-first and gate-last (shown plasma gate pre-clean on the same structure comprising multiple alternat- most optimized barrier/seed process, situ all-in-one etching of both mask ashing, wet cleaning, chemical above) processes. mainframe delivers the stringent ing dielectric layers that exacerbate showing conformal coverage without and dielectric stacks. mechanical planarization, and IL control attainable with short, aspect-ratio-dependent etch (ARDE),

40 Nanochip Nanochip 41 A Rewarding Year iterated to gradually increase bottom [4] A. Renau, “Device Performance [12] L.J. Friedrich, et al., “Study of the coverage to the point of complete fill and Yield—A New Focus for Ion Copper Reflow Process Using the (figure 4b). Independent temperature Implantation,” 10th International GROFILMS Simulator,” J. Vac. Sci. TRANSISTOR AND control for deposition and reflow Workshop on Junction Technology, Technol. B 15 (5) 1780, 1997. Customer satisfaction is a key measure of business IEEE, pp. 1-6, 2010. [13] INTERCONNECT steps enable the process to be used W.W. Mullins, “Flattening of a Nearly success. In 2012, Applied Materials earned more than [5] K. Mistry, et al., “A 45nm Logic Plane Solid Surface Due to Capillarity,” with cobalt and ruthenium liners. ADVANCES Technology with High-κ + Metal J. Appl. Phys. (30) 1, 1959. 70 awards or commendations from customers in the SMOOTH THE WAY Gate Transistors, Strained Silicon, semiconductor, solar and display industries for support OUTLOOK FOR THE 9 Cu Interconnect Layers, 193nm TO THE 2xnm NODE Thanks to the following individuals for Dry Patterning, and 100% Pb-Free of production ramps, productivity improvement and 2xnm NODE their contributions to this article: Packaging,” Proceedings of the IEDM, increased tool and factory output. We are deeply honored.

any overhang, increases feature as- Transistor technology is pp. 247-250, 2007. pect ratios beyond levels manageable advancing in multiple directions. [6] M.J. Bevan, et al., “Ultra-Thin SiO2 Tom Parrill is director of high-current for electroplating (figure 4a). While material properties and Interface Layer Growth, “Proceedings implant marketing in the Varian Semiconductor Equipment business However, augmenting deposition physical barriers are driving the of the 18th Conference on Advanced These customers included: unit of the Silicon Systems Group at with subsequent thermal reflow growing trend from planar to 3D Thermal Processing of Semiconductors designs at the 2xnm node, much – RTP 2010. Applied Materials. He holds his Ph.D. in offers a potentially limitless solution [7] C. Odegard, et al., “Dielectric Integrity materials science and engineering from ■■ to this challenge. Creating a selective is being done to extend planar AU Optronics Corporation Test for Flip-Chip Devices with Cu/ Northwestern University. profile (thinner field coverage and scaling and capability to the utmost. Low-κ Interconnects,” Proceedings of ■■ Anticipating these challenges, GCL Solar Energy, Inc. thicker bottom coverage) in the the 58th Electronic Components and Tushar Mandrekar is a global product processes and systems are deposition step and then heating Technology Conference, Vol. 55, Conf. manager in the Silicon Systems Group ■■ Green Energy Technology, Inc. proving successful in enabling 2, pp. 1163-1171, 2005. the wafer promotes the optimal at Applied Materials. He holds masters [8] both approaches. T.C. Chai, et al., “Impact of Packaging ■■ interaction of grain boundary degrees in physics and materials Hua Hong NEC Electronics Company Design on Reliability of Large Die Cu/ movement, capillary forces, and science from the University of Illinois at [1] F.T. Sanuki, et al., “Sophisticated Low-κ (BD) Interconnect,” Electronic ■■ wetting properties of the underlying Urbana-Champaign. Intel Corporation Methodology of Dummy Pattern Components and Technology Confer- layer to produce bottom-up fill.[11-13] Generation for Suppressing Dislocation ence, pp. 38-45, May 27-30, 2008. ■■ JinkoSolar Although temperature regimes [9] Atif Noori is a global product manager Induced Contact Misalignment on F. Sinapi, et al., “Surface Properties vary with different underlying in the ALD division at Applied Materials. Flash Lamp Annealed eSiGe Wafer,” Restoration and Passivation of High ■■ Lightway Solar He holds his Ph.D. in materials science materials, lower temperatures (50- VLSI Tech., pp. 156-157, 2009. Porosity Ultra-Low-κ Dielectric After 200˚C) enhance surface diffusion [2] M. Yu, et al., “Relaxation-Free Strained Direct CMP,” Micro Elec Engineering, and engineering from UCLA. ■■ Micron Technology, Inc. of copper along feature sidewalls SiGe with Super Anneal for 32nm High pp. 2620-2623, 2007. [10] for a moderate increase in bottom Performance PMOS and Beyond,” J. Bao, et al., “Oxygen Plasma Damage Arvind Sankaran is a senior global ■■ Powerchip Technology Corporation coverage; higher temperatures (~250- IEDM Tech. Digest, pp. 1-4, 2006. to Blanket and Patterned Ultra-Low-κ product manager in the Etch business Surface,” J. Vac. Sci. Technol. A28, p. ■■ 350˚C) enable mass movement from [3] Morehead, et al., “Formation unit of the Silicon Systems Group ReneSola, Ltd. 207, 2010. the field and sidewalls into the feature of Amorphous Silicon by Ion at Applied Materials. He holds [11] L.J. Friedrich, et al., “A Simulation Study ■■ Bombardment as a Function of Ion, his Ph.D. in chemical engineering Rexchip Electronics Corporation to effect a substantial increase in of Copper Reflow Characteristics in Temperature, and Dose,” Journal of from the University of Illinois at bottom coverage. The deposition, Vias,” IEEE Trans. Sem. Manuf. 12 (3), ■■ Applied Physics, 43, 1112, 1972. Urbana-Champaign. Samsung Electronics Corporation, Ltd. reflow, and cool-down cycle can be 353, 1999.

■■ Semiconductor Manufacturing International Harry Whitesell is a global product Corporation (SMIC) manager in the Dielectric Systems and Modules business unit at ■■ SK Hynix Inc. Applied Materials. He holds his 7:1 Conventional 4.5:1 Ph.D. in materials engineering from ■■ SunPower Corporation 3.8:1 Auburn University. ■■ Taiwan Semiconductor Manufacturing Company, Ltd. Incoming Structure: ~3.5:1 Reflow (Before Barrier/Seed) Sree Kesapragada is a global product (TSMC) Aspect Ratio manager in the Metal Deposition 3x 2x 1x Products business unit of the Silicon ■■ Tianma Micro-Electronics Co., Ltd. 1.5:1 (Ideal Coverage) Systems Group at Applied Materials. He holds his Ph.D. in materials science ■■ Trina Solar, Ltd. 3x 2x 1x 1x Cycle 2x Cycle 3x Cycle 20% Fill 50% Fill 100% Fill and engineering from Rensselaer Technology Node ■■ Polytechnic Institute. United Microelectronics Corporation (UMC) (4a) (4b) ■■ Winbond Electronics Corporation Figure 4. (a) Aspect ratio of interconnect trench after Cu barrier/seed layers and the benefit of reflow at the 1xnm mode. For additional information, contact (b) Reflow performance on 2xnm structures. [email protected]

42 Nanochip Nanochip 43 BY MITIGATING ADAM KEMPF and Ajith Kota THE PAIN OF PARTS OBSOLESCENCE

Whether your equipment is a legacy 150mm or 200mm workhorse, As a manufacturer, Applied has obsoleted many parts for However, it is impractical and unaffordable for any company various reasons. One example was 200mm etch polyimide ESC. to stock every part in unlimited quantities. Therefore, we are or a newer 300mm model, it’s certainly easy to understand the need for Our supplier’s particular formulation of polyimide raw material was revamping our active part obsolescence notification processes to at risk for obsolescence and we needed to go to another supplier reduce the likelihood of unexpected supply disruptions. Customers parts re-engineering to keep equipment up and running and as productive to manufacture the ESC. In this case, Applied re-engineered the with Applied Performance Service agreements or specialized parts material from polyimide to an enhanced polymer. The enhanced contracts (for example, Total Parts Management, Applied Parts- as possible. Older parts are often obsolete and simply unavailable, polymer ESC (EP ESC) required a requalification in the installed base. on-Demand, or Applied Forecast Order) will receive closed-loop or sometimes the technology changes or just gets better. Another example is a CMP membrane. Applied had been monthly notifications of planned obsolescence for parts, with a goal purchasing membranes from one supplier, but those membranes of providing up to 180 days advance notice. When inventories are were not performing to spec and were sticking to the wafer. In sufficient, last-time buys can be processed to postpone the impact The DNA of the industrial supply chain is rife with variables obsolescence is related to performance issues, when a part is response, Applied qualified a new supplier and obsoleted the on customer operations in line with their product lifecycles. beyond anyone’s control. As we pushed Moore’s Law from the subsequently replaced by an updated version. An example would original membrane. We’re also taking actions on inactive parts to improve the micrometer into the nanometer over the last 25 years, the required be a vacuum pump with reliability issues relative to newer designs, Only a fraction of the parts we’ve obsoleted actually have reliability of the information customers receive when ordering less technology and componentry evolved rapidly. Common parts and which is subsequently obsoleted by the pump manufacturer and caused much disruption, but we recognize that obsolescence can frequently used or “idle” parts (see figure 1). In the past, we quoted suppliers were used when possible, but overlap from tool to tool and replaced by a more reliable, improved version. be disruptive to a supply chain. Applied is continually working on lead times and the prices on record from the last order. However, from node to node often has been limited. The result? With more Obsolescence, in general, is increasingly painful. Applied alone solutions that will be less disruptive to customers, such as part because this subset of parts is prone to the greatest variation in than 30,000 machines out there, ranging in age from >25 years to has about twelve thousand 200mm tools installed and currently re-engineering to minimize the impact on your fab operations. lead times, costs and availability (obsolescence), we have adjusted hot off the manufacturing floor, Applied has released hundreds of running in fabs around the world, and they have been processing At Applied, we break our parts portfolio into two general our order management process for inactive parts to improve thousands of unique part numbers. wafers for decades. The life spans of the tools usually exceeds the categories (see figure 1). Our goal is to better predict the need for accuracy on commitments. This naturally brings up the question of part obsolescence. life spans of some of the parts inside them. And it’s getting harder replacements of active parts, aligned with customer forecasts. Under this new system, Applied’s order-management team There are three main reasons for it, the most common one being all the time to find the parts, especially with acceptable quality and Keeping inventories at the ready for frequently used parts is will inform customers of the inactive status of the requested parts low demand. If it’s a part that rarely breaks over time, there’s little at an affordable price. While the incidence rate of obsolescence is common practice. Our supply chain network and on-site, near-site, and verify pricing and lead times before processing orders. Status incentive for the part-manufacturer, our supplier, to keep it in higher in older tools, newer tools are not immune, as in the case of and global inventories are designed to support this goal. updates will be provided within the first three business days from inventory. This holds true for our suppliers’ supply chains as well. the CMP sub-assembly described earlier. As an equipment supplier, order entry, and every 48 hours thereafter until accurate shipment, A good example is a CMP polishing platen sub-assembly. One of we hear you loud and clear on the pain of obsolescence. cost and availability information is locked. If obsolescence issues the sub-suppliers that produced an adhesive in the assembly exited Active parts Idle Parts are identified, customers will be advised and connected to Applied’s the business because volumes were too low to justify ongoing CHANGE-MANAGEMENT SUPPORT parts engineering team to determine a resolution with the least production, forcing our primary supplier to purchase a new type of • Global usage >1 in last year • No global usage in last year We realize that unexpected supply disruptions can wreak impact on customer operations. adhesive to laminate in house. The new configuration required a new • Existing customer forecast • No forecast havoc with your operations, and that there is no such thing as too We recognize the pain of obsolescence. We understand part number and a requalification. much notification. Applied offers comprehensive programs to help • Targeted stocking level • No targeted stocking level the pain points and we’re taking actions to make it better. We are Sometimes, though, an entire assembly may be rendered mitigate supply chain risk. These change-management programs • No recent Applied Materials orders also looking ahead to further changes that will help you mitigate obsolete because one of its components has become outdated. include supplier risk management and disaster business continuity • ~90,000 parts • ~200,000 parts obsolescence issues on your fab operations. For example, the processor on a PC board may become obsolete, (most recently tested after the 2011 earthquake in Japan). But at the rendering the entire board useless. A third major reason for part end of the day, undiscoverable financial, natural or technological Figure 1. Dividing parts into active and idle categories helps Applied For additional information, contact [email protected] disruptions persist. align parts-related activities with likely customer needs. 44 Nanochip Nanochip 45 It’s a nightmare: you buy a refurbished tool from a third party instead of the OEM based BUYING TOOLS ON THE on a lower price and fast lead time. But the tool is shipped a month late and when it’s finally installed there are problems. Parts are ordered and replaced and finally the tool SECONDARY MARKET? seems ready to run. Then you discover particle contamination from an inadequate refurbishment process. Several iterations and many months later, after spending much SIX THINGS TO REMEMBER more than the price quoted by the OEM, you deem the tool unrecoverable and scrap it. Months of productivity are lost and now you need to buy another tool.

1. Predictable Operation safety upgrades that were released For example, implanters include Also, OEMs have the specialized Purchasing refurbished equipment The tool provider and buyer since the tool went into operation tungsten parts that should be made knowledge to be able to locate and from the OEM provides the buyer with should agree on operational require- have been included. When buying of 99.9% pure tungsten in order to work with localized suppliers to factory- and field acceptance testing, ments, including an assurance that from a third party, this is an unknown. achieve the tool’s maximum allowable provide hard-to-find parts. as well as a tool warranty and assur- performance specifications will be 2. Ability to Escalate and metals specifications. But some low- 5. Software Support ances that current safety standards met at no extra charge to the buyer. Fix Problems cost brokers supply aftermarket parts and Licenses are met. Also, the buyer deserves a commit- made of 80% tungsten, which may The global nature of today’s Given today’s highly networked, ment as to what date the tool will work for some applications but can A final, very important consideration should industry mandates an equally global data-driven fabs, it is vital the tool be become operational in the fab. introduce metal contamination issues be the ongoing investments in development support infrastructure, with material equipped with current software. The Buying from an OEM assures for other processes. of 200mm technology by the tool supplier. and parts banks and field service buyer should be free from worries that the OEM is knowledgeable about There are similar issues regarding Applied, for example, is one of few OEMs operations in close proximity to the about whether the desired tool The secondary market for semiconductor a tool’s standard configuration. A the implanter’s mean time between equipment. Field service support configuration will be achieved, whether which continue to invest in developing new third-party provider is unlikely to have failures (MTBF) if the vendor does production equipment remains strong, driven must be available to fix problems fast, they can get newer software revisions applications, and in migrating 300mm this capability. The OEM can also not use the proper parts. That by devices that don’t necessarily require the including a well-defined process to if needed, and whether all required advances in technology, reliability and cost quickly identify any special modifi- raises the question of how well the latest generation of production tools, such escalate to higher levels of the service software licenses are included. to 200mm to increase the efficiency and the cations made by the previous tool implanter will perform over time if as analog and power ICs, microcontrollers, hierarchy if needed. Equipment issues If a customer buys a tool from extendibility of those assets. Many third-party owner—modifications that the new the third-party vendor has used low- MEMS, and LEDs. must be resolved cost-effectively, another semiconductor company vendors are simply not in a position to afford owner may or may not want or need. quality parts in order to sell the used making it essential that buyers nego- or a third party vendor, the original The attractive price of these refurbished Lacking this information can lead to tool cheaply. this continued investment. tiate support guidelines both before sale contract regarding the tool will ≤200mm tools is often a primary motivation unexpected and expensive surprises The key takeaway for buyers of refurbished and after the sale. 4. Obsolescence Concerns likely specify that only hardware is once the tool is installed in the fab. for buying them, but as highlighted in the Buyers who try to save by included, excluding transferability. tools is that the OEM’s name is on the tool, A third-party vendor does not 3. Parts Quality Assurance story above—which is based on an actual purchasing the lowest-cost tools on As such, a buyer needs to make sure which means that an OEM has more to lose necessarily provide a warranty. The Tool support includes enabling experience—buying from a 3rd party, based the open market can find that needed they are getting what they paid for: if a customer isn’t satisfied. It’s the OEM’s OEM, however, typically provides the buyer to purchase quality replace- on price alone, is not without risk. parts have been made obsolete by the equipment and the software to run reputation on the line, and they need to stand equipment support capabilities similar ment parts and consumables from original manufacturer. In other cases, the equipment. by that tool for years to come. Here are six “buyer awareness” issues which, to those it offers on the rest of its tools, a single, trusted source. The OEM is the company that fabricates the parts in our experience, customers should keep in covering tool acceptance, process the one-stop resource to address the 6. Known Total Costs— How the used tool performs can impact the may have gone out of business. mind when buying a used tool. qualification and operation in the full range of part requirements. No Surprises potential for the next equipment purchase, Purchasing used equipment fab. For example, Applied Materials’ Buyers must also beware of used Even when the cost of a refur- directly from the OEM can help whether it is a new or used tool. If it’s an standard warranty on used tools is equipment purchased on the open bished tool takes into account the mitigate obsolescence issues. In many Applied Materials product, we want the three months, including corrective market that may contain damaged or considerations listed above, there By cases the OEM receives notification customer to feel that Applied Materials “did maintenance parts and labor, during re-engineered parts that do not meet are still opportunities for unwelcome from suppliers on discontinued parts, right by me.” T.T. Robertson normal business hours, excluding the standards set by the OEM. In surprises. For example, buyers should allowing the OEM to consider last-time Applied Materials holidays. Extended fact, often customers buy a tool that be careful to ensure that tools pur- For additional information, contact john_c_cummings@ buys to support their installed base. warranty and service agreements looks fine, but they may not be able chased from a broker are not subject amat.com or [email protected] (implanters) The OEM’s engineers can design- covering support for multiple years are to identify who manufactured the to software license fees that were not in replacement parts that meet all also available options. parts inside. The risk is that an inferior included in the broker’s sale price. required fit-and-function specifications When buying from an OEM, the part may not be suitable for the new and are only available from the OEM. customer also can be certain that any owner’s needs.

46 Nanochip Nanochip 47 Reporter’s Notebook: A VIEW FROM BELGIUM KNOWLEDGE David LammerS As many big corporate research labs, from Bell Labs to MANAGEMENT PORTAL Hitachi’s Central Research Laboratory, have been scaled back, BOOSTS APPLIED’S FIELD SERVICE RESPONSIVENESS consortia such as imec, in Leuven, Belgium, are performing more of the basic semiconductor research. But while much of the “R”—research—of the semiconductor process R&D budget When it comes to installing, repairing, maintaining and upgrading is outsourced to consortia, the “D”—development—is closely guarded within companies. For the two dozen journalists would be introduced with smaller transistors. And because EUV highly complex production tools for semiconductor, solar and display invited to Leuven in October 2012 for the annual imec involves fewer masks than double patterning, the costs of this applications, the proverb “time is money” couldn’t be more apt. Technology Forum (ITF) for media, the event was an important second generation may improve as well. d update on the direction of leading-edge research. Other technologies will support the chip industry’s progress, People in other industries, such as pharmaceutical, are including optical chip-to-board interconnects, through-silicon The longer a tool is down, the more revenue a fab stands to More than 12,000 service-related documents, 2 million part amazed at how open companies in the semiconductor industry vias, vertical NAND, and larger 450mm wafers. Already, imec lose. Today’s faster paced and fickle markets mean the economic numbers, and all tool “as shipped” BOMs can be searched in ARK.

are within these research consortia. One compelling reason is researchers are seeing sharp reductions in gate leakage by or impact of idle equipment may be greater than ever. Whether Hundreds of new and revised documents are added monthly. that the challenges are becoming more expensive: IC Insights adding aluminum to today’s hafnium oxide high-k dielectrics. And manufacturers perform service in house or use an outside service They are organized and updated by a content management estimates that R&D spending by semiconductor companies several CVD-type low-k dielectrics will reduce R-C delays in the provider, the need is always the same: a fast, expert response to system that employs standard practices and taxonomy to assign worldwide is expected to grow 10% in 2012 to $53.4 billion, a interconnect stack. Directed self-assembly (DSA) copolymers get tools up and running as quickly as possible. key attributes and terms to documents to facilitate searches. This record high. are now beginning the arduous journey from lab to fab, and may Maximum service responsiveness and speed come not only allows new documents to be searchable immediately. Luc Van den hove, imec’s CEO, ease the burden on EUV lithography. from product experience and technical training, but also from the Through ARK, information that was previously difficult said the challenges facing the chip An Steegen, a former IBM engineer’s ability to quickly leverage company resources. These to find or that may have been distributed across a number of industry can seem overwhelming, researcher who now heads up imec’s

resources include product documentation, best known methods sources is more easily accessible. Since ARK went online in ranging from EUV lithography, which CMOS scaling efforts as senior vice st w (BKMs), product notices, parts information, service bulletins and May 2012, Applied’s field service engineers have reported an tops his list, to keeping process president of process technology,

manuals, bills of materials (BOMs) for specific tools, images and average 50% reduction in time spent searching for information, complexity and costs under control. envisions another major change at a other information that may be needed to perform the service. with a roughly 10% improvement in document accuracy, based However, “we shouldn’t overemphasize the 10nm node. By then, leading-edge Luc Van den hove, The faster company resources can be accessed, the faster on before and after tests. This reduction has significantly the difficulties,” he said, in part because devices will require high-mobility chief executive officer, An Steegen, customer problems can be resolved and BKMs implemented to improved the engineers’ efficiency. On average more than 90 the work is somewhat divided. imec-NL channel materials, including germanium senior vice president reduce downtime. To accomplish this, Applied has implemented unique users access the ARK portal each day and that number Intel took the lead on FinFET in the P-channel and III-V compounds of process technology, a customized, searchable and secure internal knowledge is trending upward. development, while ASML is the center of EUV research. such as indium gallium arsenide in the imec-NL management portal for its service engineers known as Applied “The ultimate value our service business brings to our Equipment companies will do most of the 450mm tool R&D. N-channel. Rapid Knowledge (ARK). customers is our ability to help them earn revenue by reducing or Imec has a much different role in the 450mm transition “We have to solve the epitaxial challenges,” Steegen says, ARK is an innovative and comprehensive search engine that eliminating equipment downtime,” said Cassio Conceicao, vice than the Global 450mm Consortium (G450C) based in referring to the lattice mismatch issues that challenge the enables engineers to find documentation and other information president of Applied’s service products group. “ARK helps us do Albany, New York. Albany will focus on developing the introduction of III–V materials. l The from multiple data sources using a single, simple interface. ARK that better and faster, by putting necessary information at the automation and process equipment needed to process All these technical challenges, which may seem includes collaborative features that let users provide feedback on fingertips of our expert engineers with precision and speed.” 450mm wafers, while imec’s role is to serve in the overwhelming when taken together, seem to bring a kind of product manuals, customer engineering notices, internal service For its achievement in developing and implementing development of CMOS process technology on 450mm wafers. determined good cheer to the imec researchers. The industry’s bulletins and parts. The portal also allows users to share BKMs the ARK portal, Applied Materials was named to the 2012 “There is no sense competing with Albany. Our role is to myriad R&D projects are “job security for us,” said Van den across the organization. InformationWeek 500 list of business technology innovators. enable scaling,” said Van den hove. hove. “Things are not at all easy right now. While the challenges “EUV is the most important issue. If we don’t get it to work are unprecedented, the main players are also getting bigger.” on time, then the cost of scaling will be phenomenal. That Imec is located in Flanders, the Dutch-speaking would slow down scaling,” he said. portion of Belgium, which funds a small fraction of imec’s Investments in ASML by Intel, Samsung and TSMC will €300 million budget. David Lammers enable “the right critical mass of people” working on EUV The most tangible return on the Flanders government’s is an Austin-based lithography. “More money equals more people, resulting in investment is the 2,000 people who work at the imec campus, technology journalist who has worked at faster solutions,” he added. reason enough for Flanders to invest about $130 million (€100 EE Times, Van den hove noted that scaling is already slowing down. At million) towards a billion-dollar 450mm clean room, which is Semiconductor the 14nm node, companies are likely to introduce a first version, now in the planning stages. International, based on FinFET devices, using double patterning with 193nm And that leads back to the hope that more R&D money will and Semiconductor scanners. This first-generation 14nm node would not have the bring in more people with the skills to solve the semiconductor Manufacturing SRAM density doubling seen normally from node to node. industry’s challenges. Van den hove sees employment at imec and Design. When EUV becomes fully available, a second 14nm technology going up by 500 people in the next five years.

48 Nanochip Nanochip 49 www.appliedmaterials.com

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