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Enabling the A.I. Era: from Materials to Systems

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Enabling the A.I. Era: from Materials to Systems Enabling the A.I. Era: From Materials to Systems ​Sundeep Bajikar Head​ of Corporate Strategy & Market Intelligence, Applied Materials ​A.I. Summit at Semicon Korea | January 23, 2019 External Use Forward-Looking Statements This presentation contains forward-looking statements, including those regarding anticipated growth and trends in Applied’s businesses and markets, industry outlooks, technology transitions, and other statements that are not historical facts. These statements are subject to risks and uncertainties that could cause actual results to differ materially from those expressed or implied by such statements and are not guarantees of future performance. Information concerning these risks and uncertainties is contained in Applied’s most recent Form 10-Q and other filings with the SEC. All forward-looking statements are based on management's current estimates, projections and assumptions, and Applied assumes no obligation to update them. 2 | External Use Key Messages PART 1 PART 2 A.I. Computing A.I.* Requires Requires a New New Computing Semiconductor Architectures Playbook * A.I. refers to Machine Learning and Deep Learning approaches. 3 | External Use Key Messages PART 1 What is different A.I. Requires about A.I. computing? New Computing Empirical analysis – Architectures A.I. / IoT unaffordable with current computing model 4 | External Use Explosion of Data Generation >10ZB INFLECTION YEAR SAFETY and Data generated by SECURITY machines > humans SMART VEHICLES HOME and BUILDINGS 2ZB ZB SMART 1.5 FACTORIES Machines Humans 53% 44% <10% HUMANS 2017 2018E 2022E SOURCE: Applied Materials model based on forecasts published by Cisco, Intel, Western Digital 5 | External Use What’s different about Relative to traditional A.I. computing? CPU architectures Memory Bound Traditional multi-level on-die cache Performance limited by memory latency architecture is unnecessary and memory bandwidth High Data Parallelism Traditional deep instruction pipeline Identical operations can be done on and out-of-order execution are multiple chunks of data in parallel unnecessary Low Precision Traditional 64 bit or higher precision Training and inference require much data paths are unnecessary lower floating point (16 bit) and integer (8 bit) precision Deep Learning Enabled by Processing Abundant Data Source: Computer Architecture: A Quantitative Approach, Sixth Edition, John Hennessy and David Patterson, December 2017, Applied Materials internal analysis 6 | External Use Data Algorithms ML / DL RELATIONSHIP BETWEEN Complexity of algorithms AI is about VERSUS “relentless classification” Abundance of (training) data Data quality and size are + affordable high- making AI a reality performance computing Source: Applied Materials internal analysis. 7 | External Use ML / DL CASE STUDY: Google Translate Circa 2010 ► Complex algorithms based on grammar and semantic rules ► Developed by team of linguists 70% accuracy Source: Applied Materials internal analysis. 8 | External Use ML / DL CASE STUDY: Google Translate Today ► Simple algorithm ► Trained using every single web page available in English and Chinese ► No Chinese speakers on team 98% accuracy Source: Applied Materials internal analysis. 9 | External Use From Homogeneous to Heterogeneous Computing Homogeneous / Discrete Compute Era Heterogeneous Compute Era CPU Media CPU CPU 0 CPU 1 CPU GPU ISP GPU CPU 3 GPU CPU 2 Audio FPGA ASIC / FPGA ASIC / FPGA CPU 4 Normal Compiled Imaging, AI Workloads: ASIC / Managed Code Video Playback Training, Inference, (Office, OS, Enterprise) Analytics, etc. CPU Exploits data level parallelism CPU Uses the most energy-efficient GPU GPU compute engine for a given job Client CC, Search, Gaming, HPC, Highly Audio, VOIP Parallel Workloads Source: Applied Materials internal analysis. 10 | External Use In Current Compute Model… DRAM NAND 25 500 y = 0.0081x1.3065 y = 0.0022x2.0399 R² = 0.9563 R² = 0.9569 20 400 15 300 10 200 NAND Shipments (EB) Shipments NAND DRAM Shipments (EB) ShipmentsDRAM 5 100 - - - 100 200 300 400 500 - 100 200 300 400 500 Incremental Data Generation (EB) Incremental Data Generation (EB) Source: Cisco VNI, Cisco, Gartner, Factset, Applied Materials internal analysis 2006 to 2016 data from Cisco and Gartner. 2017 to 2020 projections from Cisco for data generation (VNI IP traffic), and industry average estimates for DRAM and NAND content shipments 11 | External Use A.I. / Big Data Era Needs New Compute Models DRAM NAND 180 14,000 1% adoption 160 of L4/L5 12,000 1% adoption 140 Smart Car of L4/L5 10,000 Smart Car 120 100 8,000 SMART CAR SMART CAR 80 6,000 1% ADOPTION 1% ADOPTION 60 NAND Shipments (EB) Shipments NAND 4,000 DRAM Shipments (EB) Shipments DRAM 1.3065 5X MORE DATA X MORE DATA 40 y = 0.0081x 5 R² = 0.9563 2,000 20 MORE DRAM y = 0.0022x2.0399 MORE NAND 8X IN 2020 R² = 0.9569 25X IN 2020 - - - 500 1,000 1,500 2,000 2,500 - 500 1,000 1,500 2,000 2,500 Incremental Data Generation (EB) Incremental Data Generation (EB) Source: Cisco VNI, Cisco, Gartner, Factset, Applied Materials internal analysis 2006 to 2016 data from Cisco and Gartner. 2017 to 2020 projections from Cisco for data generation (VNI IP traffic), and industry average estimates for DRAM and NAND content shipments 12 | External Use A.I. Needs New Energy-Efficient Compute Models 250 25% Estimated current 200 computing models 20% for A.I. represent 25% of global energy 150 15% consumption by 2025 INFERENCE A.I. TAM ($B) TAM A.I. 100 10% 50 5% TRAINING A.I. as a % of Global Electricity Consumption (%) Consumption Electricity Global % of a as A.I. 0 0% 2016 2017 2018E 2019E 2020F 2021F 2022F 2023F 2024F 2025F Source: Applied Materials internal analysis. 13 | External Use Key Messages PART 2 A.I. Computing From classic 2D scaling Requires a New to architecture Semiconductor innovation Playbook From traditional materials to materials breakthroughs 14 | External Use “Classic 2D Scaling” to Architecture Innovation ORIGINAL PERFORMANCE ERA PERFORMANCE GAIN HOW Classic 2D scaling PC, Mobile When Moore’s Law scaling was 1x ~2x at it’s peak. Assumes no major architecture changes ~2x to Architecture Innovation A.I. / IoT 1x Small benefit from Moore’s Law 2,500x scaling Source: Applied Materials internal analysis . Performance broadly refers to speed or power efficiency. ~2x refers to doubling of performance every two years consistent with Moore’s Law. ISS Blog post #1: Nodes, Inter-nodes, Leading-Nodes and Trailing-Nodes 15 | External Use Litho-enabled Moore’s Law is Slowing PERFORMANCE IMPROVEMENTS OVER TIME TIME BETWEEN LOGIC (VS. VAX-11/780) NODES IN YEARS 100,000 End of Moore’s Law Limits of parallelism of Amdahl’s Law 45 to 32nm 1.8 End of Dennard Scaling 10,000 3.5% 32 to 22nm 1,000 per year 2 12% per year 100 23% per year 22 to 14nm 2.5 52% 10 per year 25% per year 14 to 10nm 5.3 VAX-11/780 1978 1986 2003 2011 2015 2018 SOURCE: Computer Architecture: A Quantitative Approach, Sixth Edition, John Hennessy and David Patterson, December 2017 SOURCE: Bernstein 16 | External Use A.I. Enabled by Materials Breakthroughs ORIGINAL PERFORMANCE MATERIALS ERA PERFORMANCE GAIN ENGINEERING PC, Mobile 1x ~2x Unit Materials ~2x to Materials Breakthroughs A.I. / IoT 1x New devices, 3D techniques, 2,500x Advanced packaging Source: Applied Materials internal analysis . Performance broadly refers to speed or power efficiency. ~2x refers to doubling of performance every two years consistent with Moore’s Law ISS Blog post #2: Nodes, Inter-nodes, Leading-Nodes and Trailing-Nodes. 17 | External Use enabled by Architecture Innovation Materials Engineering High Memory Bandwidth New Devices Performance limited by memory . On-die memory – e.g. MRAM ® ™ latency and memory bandwidth . New memory – e.g. Intel 3D XPoint technology 3D Techniques High Data Parallelism . Self-aligned structures – e.g. vias, Identical operations can be done on multi-color patterning multiple chunks of data in parallel . “Side-to-side” to “top-to-bottom” – e.g. COAG Low Precision Advanced Packaging Training and inference require . Stacked DRAM – e.g. HBM / HBM2 much lower floating point (16 bit) . Logic-DRAM and integer (8 bit) precision . Sensor-Logic Intel and 3D XPoint are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. 18 | External Use ENABLED BY PERFORMANCE New architectures New structures / 3D PPAC New materials New ways to shrink POWER AREA-COST Advanced packaging NEW PLAYBOOK NEEDED Design + Manufacturing 19 | External Use Example: STT-MRAM CAPPING >15 individual layers of film MGO CAP in MTJ stack FREE LAYER TUNNEL BARRIER Each layer 0.2-to-2nm thin REFERENCE LAYER Requires highly complex SAF PINNED LAYER process equipment Requires materials (Element, Composition, SEED LAYER Stack) and Etch co- optimization New Memory Device Enabled By Materials Breakthrough Source: Applied Materials internal analysis . 20 | External Use Investments to Enable New Semiconductor Playbook AI DESIGN FORUM Maydan Applied Packaging Applied Ventures META Center A. I. Design Forum Technology Center Development Center World’s most advanced >$250M assets Expands R&D capability Fully-integrated 300mm Expanded ecosystem 300mm R&D lab with under management and to support new types of advanced WLP process engagements $300M invested in >30 active companies collaboration from flow and a full suite of past 3 years lab to fab and accelerate equipment innovation from materials to systems 17K sq. ft. cleanroom, fully staffed Announced November 2018 Scheduled to open in 2019 21 | External Use UNLOCKED BY A.I. – Big Hardware renaissance Data Era Materials innovation to enable new architectures, = the biggest structures, ways to shrink opportunity of and packaging approaches our lifetimes New ecosystem playbook for Design and Manufacturing 22 | External Use .
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