Enabling the Semiconductor Roadmap from a Multi-Angled Approach June 13th, 2019 Steven Welch Senior Director of Strategy, Advanced Product and Technology Development, Applied Materials External Use Introduction Steven Welch is currently Senior Director of Strategy for Applied Materials’ Advanced Product and Technology Development group. In this role, he is responsible for identifying and synthesizing key inflections in the longer-term Semiconductor technology roadmap, as well as enabling disruptive technology development and business growth strategies to intercept these emerging opportunities. With over 20 years in the industry, Steven started his career in 1998 as a photolithography engineer at IBM’s Storage Systems Division in San Jose, California. Since then, he has held marketing and strategy leadership positions in KLA-Tencor’s wafer inspection, Applied Materials’ etch, and ASML’s holistic lithography businesses. Steven holds a B.S. in Chemistry from Harvey Mudd College and MA & MBA degrees from the University of Pennsylvania’s Wharton School of Business. 2 External Use Semiconductor Scaling and Enablers Logic Scaling Advancements AGENDA Memory Advancements to Scale A.I. Big Data 3 External Use Semiconductor Scaling and Enablers Logic Scaling Advancements AGENDA Memory Advancements to Scale A.I. Big Data 4 External Use Market Growth and Evolution Trillions A.I. of units Big Data Mobile + Social Media Billions of units PC + Internet 100 Millions of units Mainframe Computing 100,000s of units 1988 1998 2008 2018 5 External Use Industry’s Old Playbook… MOORE’S LAW PPAC 105 ENABLED BY 1962 104 “Classic” 2D 1965 PERFORMANCE feature shrinking 103 102 1970 PPAC 10 materials RELATIVE COST/COMPONENT RELATIVE engineering to 1 POWER AREA-COST 1 10 102 103 104 105 drive power and COMPONENT PER IC performance Now: Apple A12X Bionic >10 billion transistors https://wccftech.com/apple-a12x-10-billion-transistors-performance/ 6 External Use In the Future… ENABLED BY New architectures PERFORMANCE New structures / 3D PPAC New materials New ways to shrink POWER AREA-COST Advanced packaging … New industry playbook needed to drive PPAC 7 External Use Moore’s Law beyond 5nm Node? AI compute Negative capacitance (NC)-FET 3D Memories BEOL new materials & transistors Adapted from Nature Electronics, V1, August’ 2018, 442–450 8 External Use Semiconductor Scaling and Enablers Logic Scaling Advancements AGENDA Memory Advancements to Scale A.I. Big Data 9 External Use CMOS Scaling and Enablers 65nm 45nm 22/14nm 10/7nm 5/3nm 3nm Strain High-k Metal Gate New Metal Fill SiGe-Ch. FinFET taller/ narrower & fewer fins GAA-FET Source: AMAT, SMC Korea 2019 conference Intel, 65nm Intel, 45nm Intel, VLSI 2012 Intel, IEDM 2014 Intel, IEDM 2017 IBM, VLSI 2017 Research@Intel press event 2011 New Materials: New metal gate and new contact fill New Architecture: FinFET to hGAA Samsung announced GAA 3nm node processor will ship in 2021 10 External Use Why Horizontal-GAA Evolutional Change FinFET hGAA G Thinner & Taller Fins SiGe p-Channel G G better gate control & higher drive current mobility boosting G xFin xNW Intel, IEDM 2017 GLOBALFOUNDRIES/IBM, IEDM 2016 IBM, VLSI 2017 Vertically stackable channel (NW/NS) for increased current per area Similar structures & flows: hGAA vs. FinFET 11 External Use hGAA CMOS Initial Demonstrations Transfer Characteristics Ring Oscillator H. Mertens, IEDM 2017 Source: IMEC/ Applied Materials, IEDM 2018 Functional CMOS demonstrated – getting ready for ≤3nm-node 12 External Use hGAA CMOS – Key Challenges Parasitic capacitance reduction between sheets xNW/NS S/D epi Epi defects Inner spacer(low-k) xGate IBM VLSI-T 2017 Si NW/NS V tuning metals T Metal-gate Vt tuning in narrow gaps Source: AMAT, SMC Korea 2019 conference IBM, IEDM 2017 13 External Use Beyond Conventional CMOS (≤2nm) Ge channel SiGe PFET NCFET/Ferro (HZO) SpinFET Buried Power Rail IEDM 2011 APL. 56 665 (1990) Tunnel FET (Ru) 2D TMD (MoS2) 2016 ICEEOT Co-integration (VFET, TFT) Complementary FET Nature Nanotechnology 2011 3D integration (M3D) IMEC, IEDM, 2018 IMEC, IEDM, 2018 VLSI-T 2018 14 External Use Source: AMAT, SMC Korea 2019 conference Selective Processes – Enabling New Ways to Build Chips Inherent Selective Selective by Deactivation Selective by Activation Selective Deposition ANALOGY: 3D Printing – putting material only where you want it (materials-enabled not litho) Selective Removal ANALOGY: Removing a single weed without damaging adjacent grass or leaving residue T. Faraz et al, ECS J. Solid State Sci. Technol. 4(6), N5023-N5032 (2015) 15 External Use Scaling Opportunities in the Back-end-of-line Interconnect BEOL Cu wire resistance (R) Materials-Engineering Solutions: increasing at smaller geometries due to: New materials (lowest R at CD) Inherent bulk conductor resistivity Full-volume metal fills characteristics Interface management Trade-off fill volume of high- conducting vs. cladding materials Length of line Scattering at surfaces and grain boundaries Core Metal …resulting in slower performance and CD at mid height higher power consumption Cladding (barrier / liner) Source: AMAT, IEDM 2018 conference 16 External Use Copper Extension Scenarios Co-optimization of ALD barriers with thinner liners and new fill technology is key to maximize conductor volume (low line R) and minimize interface resistance (low via R) 17 External Use Source: AMAT, IEDM 2018 conference New Metals for Resistance Scaling Co, Ru, Mo better than Cu at CD’s between 10-15nm Ir better than Cu at CD’s between 15-20nm Is a barrier or liner required? How to fill? Can it be integrated? 18 External Use Source: AMAT, IEDM 2018 conference Semiconductor Scaling and Enablers Logic Scaling Advancements AGENDA Memory Advancements to Scale A.I. Big Data 19 External Use Emerging Memories for Pervasive Data and Compute 3D SRAM SOT-MRAM STT-MRAM Ferro DRAM MIMCAP STT-MRAM Speed 3D SCM 3D DRAM Cost/bit Capacity 3D FeFET More 3D NAND Molecular Memory Source: http://www.imec.be from techspot.com (February 21, 2019) 20 External Use Architectural Advancements Leveraging Memory & Design 3D Material DRAM & Distributed Analog Architecture Innovation Packaging Cache Computing NVIDIAL2 cache L1 Cache Micron.com ElectronicDesign.com (Samsung) NVIDIA Tesla P100 white paper HPE, ACM 2016 Significant investments in memory to enable better bit scaling and performance 21 External Use 3D Architectures 3D Material DRAM & Distributed Analog Architecture Innovation Packaging Cache Computing NVIDIAL2 cache L1 Cache 3D architectures extend memory densities 3DNAND Source: Intel 2015 S. Kang, IMW2018 tutorial 22 External Use 3D Architectures 3D Material DRAM & Distributed Analog Architecture Innovation Packaging Cache Computing NVIDIAL2 cache L1 Cache Materials and Interfaces ▪ Complex stacks with multiple exotic materials are required to enable new memories ▪ Deposition, etch and CMP are critical process development areas Deposition Etch Planarization 23 External Use Example of Elements to Enable New Memories PCM Selector ▪ M-K. Lee, IEDM 2012 ▪ G.H. Kim, APL 2012 ▪ L. Zhang, IEDM 2014 STT-MRAM ▪ K. Ando, JAP 2014 FE-FET ▪ X. Tian, APL 2018 ▪ A. Pal, APL 2017 CBRAM ▪ Adesto Technologies, IEEE 2013 talk 24 External Use DRAM and Packaging 3D Material DRAM & Distributed Analog Architecture Innovation Packaging Cache Computing NVIDIAL2 cache L1 Cache Packaging enables higher performance to support more complex workloads YMTC.com (2018) Nvdia V100 source: techreport.com 2017 25 External Use Beyond Chip Scaling: Advanced Packaging DRAM ON PCB to STACKED DRAM IN PACKAGE HETEROGENEOUS INTEGRATION I/O 14nm System on Chip DRAM DRAM 3x to System on STACKED STACKED CPU CORES GPU Logic DRAM 10nm Package bandwidth 10nm 22nm DRAM DRAM STACKED STACKED performance IP OTHER COMMS Integration of 14nm GRAPHICS / IMAGING / GRAPHICS chiplets provides DRAM (stacked) GPU time, cost and % SOURCES: Intel, 50 GLOBALFOUNDRIES yield benefits Substrate (PCB) Power savings per bit Si Interposer SOURCES: AMD, NVIDIA Connecting chips together in new ways using advanced packaging 26 External Use Distributed Cache 3D Material DRAM & Distributed Analog Architecture Innovation Packaging Cache Computing NVIDIAL2 cache L1 Cache ▪ Distributed computing further reduces memory bottlenecks SRAM ▪ MRAM alternative to improve area + energy efficiency 6T SRAM 1T, 1 STT-MRAM Source: techspot.com Source: Intel, IEDM, 2012 Source: AMAT 27 External Use Multiple MRAM Milestone Announcements 8/2017 9/2017 7/2018 11/2018 12/2018 12/2018 IEDM conference 3/2019 Everspin Global TSMC Spin Memory Gyrfalcon Intel Samsung Global Samsung announced Foundries “Over 50 & Applied Technology described the showed Foundries shipped the sampling of announced customers and Materials announced first FinFET- MRAM showed first 28nm the world’s availability of 140 tapeout in commercial the based design 22nm eMRAM first 1Gb embedded N22ULP, agreement to commercial MRAM technology embedded MRAM MRAM on spanning create a availability of technology co- 40 Mb product leading many comprehensive its AI ASIC (22nm) is optimization MRAM for 22FDX FD- application embedded that include production for hardware low-power SOI platform areas… MRAM solution TSMC’s ready neural automotive connectivity, 22nm networks MCU digital TV/STB, eMRAM application application processors.” 28 External Use MRAM Benefits Low Power & Non-Volatile High Density More Functionality Robust FinFET SRAM MRAM Planar SRAM Source: Everspin.com CMOS Technology Node (nm) ▪ IMEC DTCO studied: ▪ MRAM is with > 3x cell ▪ MRAM