NANOCHIP Technology Journal
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NANOCHIP Technology Journal In This Issue • Thin-Channel Transistors • Enabling Spin-Transfer Torque Magnetic Memory • Enhanced Defect of Interest Monitoring volume 10, issue 1, 2012 A MESSAGE FROM KATHRYN TA TABLE OF CONTENTS Senior Director, Albert Einstein once commented that “to raise new questions, new possibilities, 3 Thin-Channel Transistors— SSG Marketing to regard old problems from a new angle…marks real advance in science.” The Dawn of a New Era Silicon Systems Group In this age of mobile consumer electronic devices and “smart” systems for almost every sector of the economy, semiconductor fabrication exemplifies this drive to inquire, experiment, and innovate to anticipate and enable real 9 Scaling Dielectric Gap Fill advances in our technologies. With Flowable Chemical Vapor Deposition This issue of Nanochip illustrates the variety of these technical advances as anticipated limitations to planar scaling beyond the 2x nanometer node spur 13 CMP Applications Arrive at the Gate Stack us to introduce new materials, new integration schemes, lower-temperature Enabling Advanced Transistors processing, and tighter process controls, enabling our customers to achieve greater device speed and energy efficiency, longer service life, and more compact form factors. 18 Enabling Spin-Transfer Torque Magnetic Memory for the 2x nm Node and Beyond In transistors, where leakage poses a key challenge as the gate length scales, the limits on thinning the transistor channel are driving our customers to explore alternative designs, such as FinFETs and ultra-thin body silicon-on- insulator structures. We review the processing challenges unique to each, from new channel materials to novel 24 Through-Silicon Via Technology doping and etch techniques. We also present a new CVD gap-fill process that will be a key enabler of FinFET Enroute to Manufacturing fabrication and of emerging 3D memory designs, using a fluid-like, profile-insensitive fill capable of liner-free integration with the metal films used in logic and memory devices. 29 Enhanced Defect of Interest Monitoring More scalable alternatives to DRAM and Flash are driving such new designs as spin-transfer torque magneto- With Sensitive Inspection and “Intelligent” SEM Review resistive memory. Recent technology advances have addressed the need for atomic-scale control of deposition, etch, and CMP processes, facilitating development of this new memory technology. Endpoint metrology and dynamic profile control are transforming CMP into an important technology enabler for advanced transistor fabrication and expanding its role in interconnect applications. We introduce defect review technology that is able to “learn” inspection recipes autonomously while greatly reducing the rate of nuisance defects and improving excursion identification for rapid root-cause determination. Cover Photo: Design Concept – Harry Whitesell, Photographer – Richard Lewington A MESSAGE FROM KATHRYN TA TABLE OF CONTENTS Albert Einstein once commented that “to raise new questions, new possibilities, 3 Thin-Channel Transistors— to regard old problems from a new angle…marks real advance in science.” The Dawn of a New Era In this age of mobile consumer electronic devices and “smart” systems for almost every sector of the economy, semiconductor fabrication exemplifies this drive to inquire, experiment, and innovate to anticipate and enable real 9 Scaling Dielectric Gap Fill advances in our technologies. With Flowable Chemical Vapor Deposition This issue of Nanochip illustrates the variety of these technical advances as anticipated limitations to planar scaling beyond the 2x nanometer node spur 13 CMP Applications Arrive at the Gate Stack us to introduce new materials, new integration schemes, lower-temperature Enabling Advanced Transistors processing, and tighter process controls, enabling our customers to achieve greater device speed and energy efficiency, longer service life, and more compact form factors. 18 Enabling Spin-Transfer Torque Magnetic Memory for the 2x nm Node and Beyond In transistors, where leakage poses a key challenge as the gate length scales, the limits on thinning the transistor channel are driving our customers to explore alternative designs, such as FinFETs and ultra-thin body silicon-on- insulator structures. We review the processing challenges unique to each, from new channel materials to novel 24 Through-Silicon Via Technology doping and etch techniques. We also present a new CVD gap-fill process that will be a key enabler of FinFET Enroute to Manufacturing fabrication and of emerging 3D memory designs, using a fluid-like, profile-insensitive fill capable of liner-free integration with the metal films used in logic and memory devices. 29 Enhanced Defect of Interest Monitoring More scalable alternatives to DRAM and Flash are driving such new designs as spin-transfer torque magneto- With Sensitive Inspection and “Intelligent” SEM Review resistive memory. Recent technology advances have addressed the need for atomic-scale control of deposition, etch, and CMP processes, facilitating development of this new memory technology. Endpoint metrology and dynamic profile control are transforming CMP into an important technology enabler for advanced transistor fabrication and expanding its role in interconnect applications. We introduce defect review technology that is able to “learn” inspection recipes autonomously while greatly reducing the rate of nuisance defects and improving excursion identification for rapid root-cause determination. Cover Photo: Design Concept – Harry Whitesell, Photographer – Richard Lewington THIN-CHANNEL TRANSISTOR THIN-CHANNEL ARCHITECTURES DEMYSTIFIED A transistor serves as an on-off switch. An ideal switch should have high current in its on-state and zero current TRANSISTORS in its off-state. In reality, a transistor does leak current in its off-state. As the size of the transistor shrinks, the current The Dawn of a New Era Figure 1 Conventional Planar Transistor KEYWORDS CMOS transistor features scaled following simple rules Thin Channel Transistor Dennard Rule Transistors proposed by IBM’s Robert Dennard to predict changes 1000 Thin-Channel Transistors in physical properties, such as gate length, gate oxide FinFETs thickness, and junction depth needed to achieve higher [1] SOI transistor density and performance. During the ngth (nm) Le 100 Gate Length 3D Transistors 1990-era personal computing (PC) boom, demand Scaling Stalled for increased device performance was such that gate Gate length was actually scaled faster than called for by Thin Channel Dennard’s rules. Further, operating voltage reductions 10 Solution Path specified by Dennard were not followed for system considerations. Taken together, at the turn of the 432 1.5 1 0.80.5 0.35 0.25 0.18 0.13 90 65 45 32 22 14 10 7 century, these two deviations resulted in the alarming Node (nm) forecast that high levels of integrated circuit power This roadblock would have stalled on-state drive current consumption would place a fundamental constraint advances, if not for major technological breakthroughs on the further progression of Moore’s Law. in strain engineering and high-κ metal gates (HKMG). In response, new circuit and transistor technologies However, increasing device packing density according were invented to keep power consumption in check at a to Moore’s Law places renewed pressure on a means of Leakage power continues to be the single biggest challenge system level. The introduction of new materials into the scaling gate lengths below 25nm. For such short channel lengths, low off-state leakage current can be achieved only to sustaining Moore’s Law, driving the need for new transistor represented a major breakthrough. In 2003, if the electric field applied to the transistor gate almost transistor architectures. FinFETs or tri-gate transistors are Intel adopted strain engineering in high-volume completely controls the electrons or holes moving in a new three-dimensional (3D) approach to the problem, manufacturing at the 90nm node to increase electron the channel. This can be achieved if the silicon body of while ultra-thin body silicon-on-insulator (UTB-SOI) and hole mobility. To keep transistor off-state leakage the transistor channel is thin enough (<12nm). extends conventional planar transistor scaling by within acceptable limits, gate length scaling slowed dramatically shrinking the thickness of the silicon layer. at subsequent nodes while progressively increasing The challenge of thinning the transistor channel has Each approach poses significant challenges that are strain levels enabled continuing increases in device sparked distinct approaches amongst semiconductor stimulating advances throughout the fabrication sequence performance. Similarly, the silicon dioxide gate Figure 2 from the types of materials used to patterning, doping, dielectric had reached a thickness at which tunneling Planar CMOSFFinFET UTB-SOI deposition, and etching technologies. Whether FinFETs or leakage currents were unacceptably high. In 2007, Intel UTB-SOI will become the more widely adopted transistor replaced the 40-year-old silicon dioxide gate dielectric G architecture is dependent upon the industry’s preference with a new insulator containing hafnium oxide and thereby ate for revolutionary versus evolutionary change. started upon a new trajectory that allows for gate Gate Raised dielectric thickness scaling without compromise to Sou Moore’s Law has served as a beacon for the Gate rce leakage. Fin semiconductor industry, predicting