NANOCHIP Technology Journal

NANOCHIP Technology Journal

In This Issue

• Thin-Channel Transistors • Enabling Spin-Transfer Torque Magnetic Memory • Enhanced Defect of Interest Monitoring

volume 10, issue 1, 2012 A MESSAGE FROM KATHRYN TA TABLE OF CONTENTS

Senior Director, Albert Einstein once commented that “to raise new questions, new possibilities, 3 Thin-Channel Transistors— SSG Marketing to regard old problems from a new angle…marks real advance in science.” The Dawn of a New Era Silicon Systems Group In this age of mobile consumer electronic devices and “smart” systems for almost every sector of the economy, semiconductor fabrication exemplifies this drive to inquire, experiment, and innovate to anticipate and enable real 9 Scaling Dielectric Gap Fill advances in our technologies. With Flowable Chemical Vapor Deposition This issue of Nanochip illustrates the variety of these technical advances as anticipated limitations to planar scaling beyond the 2x nanometer node spur 13 CMP Applications Arrive at the Gate Stack us to introduce new materials, new integration schemes, lower-temperature Enabling Advanced Transistors processing, and tighter process controls, enabling our customers to achieve greater device speed and energy efficiency, longer service life, and more compact form factors. 18 Enabling Spin-Transfer Torque Magnetic Memory for the 2x nm Node and Beyond In transistors, where leakage poses a key challenge as the gate length scales, the limits on thinning the transistor channel are driving our customers to explore alternative designs, such as FinFETs and ultra-thin body silicon-on- insulator structures. We review the processing challenges unique to each, from new channel materials to novel 24 Through-Silicon Via Technology doping and etch techniques. We also present a new CVD gap-fill process that will be a key enabler of FinFET Enroute to Manufacturing fabrication and of emerging 3D memory designs, using a fluid-like, profile-insensitive fill capable of liner-free integration with the metal films used in logic and memory devices. 29 Enhanced Defect of Interest Monitoring More scalable alternatives to DRAM and Flash are driving such new designs as spin-transfer torque magneto- With Sensitive Inspection and “Intelligent” SEM Review resistive memory. Recent technology advances have addressed the need for atomic-scale control of deposition, etch, and CMP processes, facilitating development of this new memory technology.

Endpoint metrology and dynamic profile control are transforming CMP into an important technology enabler for advanced transistor fabrication and expanding its role in interconnect applications.

We introduce defect review technology that is able to “learn” inspection recipes autonomously while greatly reducing the rate of nuisance defects and improving excursion identification for rapid root-cause determination.

Cover Photo: Design Concept – Harry Whitesell, Photographer – Richard Lewington A MESSAGE FROM KATHRYN TA TABLE OF CONTENTS

Albert Einstein once commented that “to raise new questions, new possibilities, 3 Thin-Channel Transistors— to regard old problems from a new angle…marks real advance in science.” The Dawn of a New Era In this age of mobile consumer electronic devices and “smart” systems for almost every sector of the economy, semiconductor fabrication exemplifies this drive to inquire, experiment, and innovate to anticipate and enable real 9 Scaling Dielectric Gap Fill advances in our technologies. With Flowable Chemical Vapor Deposition This issue of Nanochip illustrates the variety of these technical advances as anticipated limitations to planar scaling beyond the 2x nanometer node spur 13 CMP Applications Arrive at the Gate Stack us to introduce new materials, new integration schemes, lower-temperature Enabling Advanced Transistors processing, and tighter process controls, enabling our customers to achieve greater device speed and energy efficiency, longer service life, and more compact form factors. 18 Enabling Spin-Transfer Torque Magnetic Memory for the 2x nm Node and Beyond In transistors, where leakage poses a key challenge as the gate length scales, the limits on thinning the transistor channel are driving our customers to explore alternative designs, such as FinFETs and ultra-thin body silicon-on- insulator structures. We review the processing challenges unique to each, from new channel materials to novel 24 Through-Silicon Via Technology doping and etch techniques. We also present a new CVD gap-fill process that will be a key enabler of FinFET Enroute to Manufacturing fabrication and of emerging 3D memory designs, using a fluid-like, profile-insensitive fill capable of liner-free integration with the metal films used in logic and memory devices. 29 Enhanced Defect of Interest Monitoring More scalable alternatives to DRAM and Flash are driving such new designs as spin-transfer torque magneto- With Sensitive Inspection and “Intelligent” SEM Review resistive memory. Recent technology advances have addressed the need for atomic-scale control of deposition, etch, and CMP processes, facilitating development of this new memory technology.

Endpoint metrology and dynamic profile control are transforming CMP into an important technology enabler for advanced transistor fabrication and expanding its role in interconnect applications.

We introduce defect review technology that is able to “learn” inspection recipes autonomously while greatly reducing the rate of nuisance defects and improving excursion identification for rapid root-cause determination.

Cover Photo: Design Concept – Harry Whitesell, Photographer – Richard Lewington THIN-CHANNEL TRANSISTOR THIN-CHANNEL ARCHITECTURES DEMYSTIFIED A transistor serves as an on-off switch. An ideal switch should have high current in its on-state and zero current TRANSISTORS in its off-state. In reality, a transistor does leak current in its off-state. As the size of the transistor shrinks, the current The Dawn of a New Era Figure 1

Conventional Planar Transistor KEYWORDS CMOS transistor features scaled following simple rules Thin Channel Transistor Dennard Rule Transistors proposed by IBM’s Robert Dennard to predict changes 1000 Thin-Channel Transistors in physical properties, such as gate length, gate oxide FinFETs thickness, and junction depth needed to achieve higher [1] SOI transistor density and performance. During the ngth (nm)

Le 100 Gate Length 3D Transistors 1990-era personal computing (PC) boom, demand Scaling Stalled

for increased device performance was such that gate Gate

length was actually scaled faster than called for by Thin Channel Dennard’s rules. Further, operating voltage reductions 10 Solution Path specified by Dennard were not followed for system considerations. Taken together, at the turn of the 432 1.5 1 0.80.5 0.35 0.25 0.18 0.13 90 65 45 32 22 14 10 7 century, these two deviations resulted in the alarming Node (nm) forecast that high levels of integrated circuit power This roadblock would have stalled on-state drive current consumption would place a fundamental constraint advances, if not for major technological breakthroughs on the further progression of Moore’s Law. in strain engineering and high-κ metal gates (HKMG). In response, new circuit and transistor technologies However, increasing device packing density according were invented to keep power consumption in check at a to Moore’s Law places renewed pressure on a means of Leakage power continues to be the single biggest challenge system level. The introduction of new materials into the scaling gate lengths below 25nm. For such short channel lengths, low off-state leakage current can be achieved only to sustaining Moore’s Law, driving the need for new transistor represented a major breakthrough. In 2003, if the electric field applied to the transistor gate almost transistor architectures. FinFETs or tri-gate transistors are Intel adopted strain engineering in high-volume completely controls the electrons or holes moving in a new three-dimensional (3D) approach to the problem, manufacturing at the 90nm node to increase electron the channel. This can be achieved if the silicon body of while ultra-thin body silicon-on-insulator (UTB-SOI) and hole mobility. To keep transistor off-state leakage the transistor channel is thin enough (<12nm). extends conventional planar transistor scaling by within acceptable limits, gate length scaling slowed dramatically shrinking the thickness of the silicon layer. at subsequent nodes while progressively increasing The challenge of thinning the transistor channel has Each approach poses significant challenges that are strain levels enabled continuing increases in device sparked distinct approaches amongst semiconductor stimulating advances throughout the fabrication sequence performance. Similarly, the silicon dioxide gate Figure 2 from the types of materials used to patterning, doping, dielectric had reached a thickness at which tunneling Planar CMOSFFinFET UTB-SOI deposition, and etching technologies. Whether FinFETs or leakage currents were unacceptably high. In 2007, Intel UTB-SOI will become the more widely adopted transistor replaced the 40-year-old silicon dioxide gate dielectric G architecture is dependent upon the industry’s preference with a new insulator containing hafnium oxide and thereby ate for revolutionary versus evolutionary change. started upon a new trajectory that allows for gate Gate Raised dielectric thickness scaling without compromise to Sou Moore’s Law has served as a beacon for the Gate rce leakage. Fin semiconductor industry, predicting device density Raised Dra and performance improvements for over 40 years. Today, leakage power continues to be the single biggest in B Complementary metal-oxide semiconductor (CMOS) challenge to sustaining Moore’s Law. Here, we discuss Silicon uried S ST Oxi Subst ilic I O Silicon Su de logic, invented in the 1960s, entered into high-volume the need for new transistor architectures that will rate on Substra xide bstrate production in the 1980s because it enabled lower-power enable tomorrow’s lower-power smartphones, tablets, te circuits while keeping to the cadence of Moore’s Law. and mobile PCs.

3 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Thin-Channel Transistors

THIN-CHANNEL TRANSISTOR in the off-state increases exponentially as does power THIN-CHANNEL ARCHITECTURES DEMYSTIFIED consumption. In 2001, transistor off-state current was A transistor serves as an on-off switch. An ideal switch almost the same as on-state current, which prevented should have high current in its on-state and zero current scaling the channel length in accordance with Dennard’s TRANSISTORS in its off-state. In reality, a transistor does leak current in its rule. Moore’s Law proceeded through gate pitch scaling, off-state. As the size of the transistor shrinks, the current but transistor length scaling had stalled (Figure 1). The Dawn of a New Era Figure 1

Conventional Planar Transistor Figure 1. New transistor CMOS transistor features scaled following simple rules Thin Channel Transistor designs are needed to make Dennard Rule proposed by IBM’s Robert Dennard to predict changes 1000 possible continued gate in physical properties, such as gate length, gate oxide length scaling. thickness, and junction depth needed to achieve higher [1] transistor density and performance. During the ngth (nm)

Le 100 Gate Length 1990-era personal computing (PC) boom, demand Scaling Stalled

for increased device performance was such that gate Gate length was actually scaled faster than called for by Thin Channel Dennard’s rules. Further, operating voltage reductions 10 Solution Path specified by Dennard were not followed for system considerations. Taken together, at the turn of the 432 1.5 1 0.80.5 0.35 0.25 0.18 0.13 90 65 45 32 22 14 10 7 century, these two deviations resulted in the alarming Node (nm) forecast that high levels of integrated circuit power This roadblock would have stalled on-state drive current chip makers (Figure 2). One is to build a 3D FinFET (tri- consumption would place a fundamental constraint advances, if not for major technological breakthroughs gate transistor) in which the channel is a “fin” of silicon on the further progression of Moore’s Law. in strain engineering and high-κ metal gates (HKMG). surrounded on three sides by a gate. A second extends In response, new circuit and transistor technologies However, increasing device packing density according conventional planar scaling, but employs an ultra-thin to Moore’s Law places renewed pressure on a means of were invented to keep power consumption in check at a silicon channel that sits on an insulator, called an ultra- scaling gate lengths below 25nm. For such short channel system level. The introduction of new materials into the thin body silicon-on-insulator or UTB-SOI. lengths, low off-state leakage current can be achieved only transistor represented a major breakthrough. In 2003, if the electric field applied to the transistor gate almost In the late 1990s, Professor Chenming Hu of the Intel adopted strain engineering in high-volume completely controls the electrons or holes moving in manufacturing at the 90nm node to increase electron University of California at Berkeley led an ambitious the channel. This can be achieved if the silicon body of [2,3] and hole mobility. To keep transistor off-state leakage study to determine pathways forward. This pioneering the transistor channel is thin enough (<12nm). within acceptable limits, gate length scaling slowed study demonstrated the feasibility of both UTB-SOI and at subsequent nodes while progressively increasing The challenge of thinning the transistor channel has FinFET structures at gate lengths less than 20nm and, strain levels enabled continuing increases in device sparked distinct approaches amongst semiconductor later, less than 10nm for FinFETs. performance. Similarly, the silicon dioxide gate Figure 2 dielectric had reached a thickness at which tunneling Planar CMOSFFinFET UTB-SOI Figure 2. Comparison of leakage currents were unacceptably high. In 2007, Intel industry-standard planar replaced the 40-year-old silicon dioxide gate dielectric G CMOS architecture with with a new insulator containing hafnium oxide and thereby ate new FinFET and UTB-SOI started upon a new trajectory that allows for gate G ate architectures. Raised dielectric thickness scaling without compromise to Sou Gate rce leakage. Fin Raised Dra Today, leakage power continues to be the single biggest in B challenge to sustaining Moore’s Law. Here, we discuss Silicon uried S ST Oxi Subst ilic I O Silicon Su de the need for new transistor architectures that will rate on Substra xide bstrate enable tomorrow’s lower-power smartphones, tablets, te and mobile PCs.

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 4 Thin-Channel Transistors

The FinFET Approach close-proximity gates. The FinFET design thereby Preserving Narrow Fins In May 2011, Intel announced a production-worthy enables chips to serve the computing continuum from The precisely formed fins undergo many subsequent tri-gate solution for the 22nm technology node, which high-speed servers to ultra-low-power smartphones. thermal treatment, doping, film deposition, and film had proved to have been a formidable manufacturing removal process steps. It is critical that fin dimensions The UTB-SOI Approach challenge requiring a robust manufacturing process, Proponents of the UTB-SOI school of thought often remain unchanged throughout these steps, because any the ability to pattern the fins (width and height) with highlight the relative simplicity of this technology in deviation can adversely affect final device performance. extreme precision, and the process repeatability retaining existing planar structure, minimizing changes Low-temperature processing will be required to prevent and stability to do so for billions of transistors.[4] needed in the manufacturing process flow. oxidation of fin surfaces. Doping of the fins should be Nevertheless, the effort proved worthwhile, yielding done in such a way that no crystal structure damage dramatic low-voltage and low-power benefits. UTB-SOI architecture consists of a thin silicon channel occurs. Additionally, etching processes should precisely FinFET architecture provides greater electrostatic held by an insulator on a silicon substrate. Design and uniformly remove target materials along all surfaces control of the conduction channel through the gate estimates call for a silicon body thickness of 6nm for a of the fin body without consuming the underlying electrode. The current flows in a small silicon fin having channel length of 25nm. This thickness requirement is silicon fin. an approximately rectangular cross-section with three half the fin width of the FinFET architecture (Figure 3). Gate Stack Deposition sides that are covered by the gate. Design estimates Here the current-carrying surface is along one plane only The layered material stack that includes gate insulator call for 12nm fin widths and 24nm fin heights for a due to the continuation of planar CMOS technology and gate electrode is known as the gate stack. The gate channel length of 25nm. The multiple surface channels (unlike the cumulative contribution seen from multiple insulator and metal gate must almost perfectly conform (that carry on-state current) and all sub-surface leakage surfaces on FinFETs). The sub-surface leakage paths paths (that carry off-state current) are in optimally close (off-state current) are in close proximity to the gate to the 3D body of the fin. Atomic layer deposition (ALD) proximity to a gate. A high on-state current results and are under its strong electrostatic control, greatly technology will likely be required to deposit such thin from the cumulative contribution of multiple channel reducing undesired off-state power consumption. The and highly conformal film layers. Also, metals used surfaces. The undesired off-state power consumption UTB-SOI design thereby enables chips that are ideally for nMOS and pMOS must be different to realize the is greatly reduced because of effective control from suited for ultra-low-power devices. performance benefit of the “gate-last” HKMG integration scheme employed today. For future technology nodes, Figure 3 the fin pitch will need to be scaled down considerably Figure 3. Comparison of 40 Channel Length such that little space is left for insulator and metal film Fin Thickness in FinFET estimated channel length, SOI Thickness in UTB-SOI deposition. It is conceivable that on an advanced 7nm 20 required thickness of FinFET node transistor with a fin pitch of 30nm, the combined fins, and SOI thickness in 10 thickness of gate insulator and gate metal layers will be UTB-SOI at future technology 8 in the range of 12nm. nodes. 6 4 Capacitance Reduction

Dimension (nm) Given the thinness of the fins, inadequate silicon is 2 present to permit formation of a recessed structure; hence the source drain contacts must be raised. Raised 1 structures are highly doped to lower their intrinsic 22 14 10 7 resistance and are located in close proximity to the Node (nm) gate, creating unwanted capacitive coupling and power MANUFACTURING FINFET ARCHITECTURE be employed to precisely define these thin, tall silicon drain. New materials that reduce coupling through Here we highlight eight key challenges among the many fins. Two approaches are being pursued in double use of a lower dielectric constant layer between them that arise when implementing FinFETs in production patterning: a litho-etch-litho-etch scheme and a self- (e.g., a low-κ spacer) will be needed. schemes. aligned double patterning scheme. In the latter, the wafer is exposed to two different reticles offset from Forming Channel Extensions Forming Narrow, Uniform Fins one another to achieve a net effect of a smaller feature The extension regions are part of the fin with the same For acceptable performance and leakage characteristics size. It is desired that the etching process produce 3D morphology. Doping processes normally performed of a 20nm transistor, a fin will need to be 10nm wide vertical (90˚ angle) and smooth, void-free surfaces to to lower the resistance of these regions now must with a width uniformity of 1nm. Double patterning can optimize electron transport in on-state current. provide conformal coverage across all three surfaces of

5 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Thin-Channel Transistors

close-proximity gates. The FinFET design thereby Preserving Narrow Fins the fins. If the doping is non-conformal, electrons tend enables chips to serve the computing continuum from The precisely formed fins undergo many subsequent to accumulate in the highly doped region (path of least high-speed servers to ultra-low-power smartphones. thermal treatment, doping, film deposition, and film resistance), leading to carrier crowding that results in removal process steps. It is critical that fin dimensions low on-state current. Current beam-line implantation The UTB-SOI Approach remain unchanged throughout these steps, because any techniques are non-conformal as the sidewalls of the Proponents of the UTB-SOI school of thought often fins receive a single dose while the top surface can highlight the relative simplicity of this technology in deviation can adversely affect final device performance. receive double the dose in the same time. New retaining existing planar structure, minimizing changes Low-temperature processing will be required to prevent technologies, such as plasma-based doping, vapor needed in the manufacturing process flow. oxidation of fin surfaces. Doping of the fins should be done in such a way that no crystal structure damage phase deposition, or atomic layer doping will be needed UTB-SOI architecture consists of a thin silicon channel occurs. Additionally, etching processes should precisely to provide the desired conformal doping. held by an insulator on a silicon substrate. Design and uniformly remove target materials along all surfaces Spacer Formation and Removal estimates call for a silicon body thickness of 6nm for a of the fin body without consuming the underlying A spacer is a dielectric layer located on the sides of channel length of 25nm. This thickness requirement is silicon fin. the gate stack serving multiple roles of electrical half the fin width of the FinFET architecture (Figure 3). isolation, chemical isolation, and dopant implant Here the current-carrying surface is along one plane only Gate Stack Deposition protection for underlayers during transistor formation. due to the continuation of planar CMOS technology The layered material stack that includes gate insulator A silicon nitride film is commonly used for the spacer (unlike the cumulative contribution seen from multiple and gate electrode is known as the gate stack. The gate material, and a lower-temperature process must be surfaces on FinFETs). The sub-surface leakage paths insulator and metal gate must almost perfectly conform developed than the current state-of-the-art. Etching of (off-state current) are in close proximity to the gate to the 3D body of the fin. Atomic layer deposition (ALD) the nitride spacer, an essential process step, now faces and are under its strong electrostatic control, greatly technology will likely be required to deposit such thin a whole new level of complexity in the transition to reducing undesired off-state power consumption. The and highly conformal film layers. Also, metals used 3D architecture. The nitride film must be removed UTB-SOI design thereby enables chips that are ideally for nMOS and pMOS must be different to realize the completely along all three sides of the fin (in one area), suited for ultra-low-power devices. performance benefit of the “gate-last” HKMG integration scheme employed today. For future technology nodes, but must remain on all three sides of the gate stack (in Figure 3 the fin pitch will need to be scaled down considerably an adjacent area) to mask the silicon gate for forming 40 Channel Length such that little space is left for insulator and metal film the raised source and drain contacts using epitaxy. Fin Thickness in FinFET SOI Thickness in UTB-SOI deposition. It is conceivable that on an advanced 7nm Strain Engineering for Higher Mobility 20 node transistor with a fin pitch of 30nm, the combined Virtually all advanced planar transistors today employ

10 thickness of gate insulator and gate metal layers will be some form of strain engineering to enhance carrier 8 in the range of 12nm. mobility. In FinFETs, strain-inducing capping layers have 6 been attempted using silicon nitride films deposited by 4 Capacitance Reduction chemical vapor deposition (CVD). The magnitude and Dimension (nm) Given the thinness of the fins, inadequate silicon is type of strain (e.g., tensile versus compressive) may 2 present to permit formation of a recessed structure; be adjusted by modulating the deposition conditions, hence the source drain contacts must be raised. Raised 1 especially temperature. However, the tight gate and fin structures are highly doped to lower their intrinsic 22 14 10 7 pitch dimensions limit the amount of strain that can be resistance and are located in close proximity to the Node (nm) induced by this approach. A second method involves gate, creating unwanted capacitive coupling and power the use of a silicon-rich solid solution, such as silicon- be employed to precisely define these thin, tall silicon drain. New materials that reduce coupling through germanium (pMOS) or silicon-carbon (nMOS) as fins. Two approaches are being pursued in double use of a lower dielectric constant layer between them source drain regions on the two ends of the channel to patterning: a litho-etch-litho-etch scheme and a self- (e.g., a low-κ spacer) will be needed. aligned double patterning scheme. In the latter, the induce a channel strain. The 3D nature of the fin makes wafer is exposed to two different reticles offset from Forming Channel Extensions this strain transfer from source drain regions to the one another to achieve a net effect of a smaller feature The extension regions are part of the fin with the same channel less efficient than in planar devices. To continue size. It is desired that the etching process produce 3D morphology. Doping processes normally performed scaling, radical approaches in new channel materials, vertical (90˚ angle) and smooth, void-free surfaces to to lower the resistance of these regions now must such as indium-gallium-arsenide, silicon-germanium, optimize electron transport in on-state current. provide conformal coverage across all three surfaces of and pure germanium are actively being researched.

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 6 Thin-Channel Transistors

Forming Silicide Contact for Source and Drain and to retain a good on-state channel current for high the planar CMOS architecture with minimal change in Silicide materials are deposited at the interface between performance. Higher doping can lower the resistance; manufacturing flow. A significant challenge, however, the metal contacts and silicon source drain structures. however, ion beam implantation can cause crystalline lies in manufacturing the substrate as thickness variation They are vital to lowering the interface resistance. The damage to these thin regions, worsening the resistance must be in the vanishingly small range of 0.5nm. This is 3D fin requires that the silicide be conformally deposited problem. Novel doping techniques based on epitaxial a key reason that UTB-SOI technology has not yet been to form a good electrical connection. growth and controlled diffusion will be enabling adopted for high-volume manufacturing. solutions for future nodes. MANUFACTURING UTB-SOI ARCHITECTURE A key difference between FinFET and UTB-SOI designs Four key technology challenges must be overcome for Gate Stack Deposition is in the thickness of thin silicon body. The UTB-SOI UTB-SOI architectures to be adopted in mainstream The gate insulator electrical thickness required will be requires a silicon body two times thinner than that of the production. extremely small, approximately 0.5nm for a 7nm device. FinFET, which leaves FinFET more flexibility to continue Precise control with minimal variability in thickness will scaling. One possible work-around for this issue is Thickness Control of the Thin Silicon Channel be a big challenge to overcome. ALD technology is likely for UTB-SOI to employ back-gate biasing, in which a For a 14nm device, the required silicon thickness is to be required to deliver the needed precision. The metal second gate is built below the buried oxide for greater approximately 5nm and any variation greater than 0.5nm gate electrodes must also be precisely manufactured, electrostatic control and reduced off-state current. will negatively affect on-state current (performance) requiring CVD or ALD technologies in addition to and off-state current (power consumption). A 1nm CONCLUSION physical vapor deposition technologies, to fill small deviation towards thicker silicon channels can result in The industry debate between FinFET and UTB-SOI gaps and maintain good transistor performance. as much as a tenfold increase in power consumption. approaches is an example of the classic dilemma of REVOLUTION VERSUS EVOLUTION IN choosing revolution or evolution. Both approaches can Capacitance Reduction ADVANCED TRANSISTOR ARCHITECTURES be excellent strategies. A revolutionary approach As in the case of finFET architecture, source drain FinFET and UTB-SOI were conceived a decade ago and requires large-scale investment, with greater risks by terminal contacts now have to be raised and are generally both effectively address the long-term quest for low off- radically changing the transistor design and process highly doped to lower their intrinsic resistance. Being state current. Both have demonstrated the ability to scale flow, but it can also bring longer-term yield, performance, raised, they lie in close proximity to the gate, leading down the channel length to less than 25nm (Figure 4). and extendibility advantages. An evolutionary approach to undesired capacitive coupling between the two and reduces risk, required investment, and time-to-market. related power drain. New materials that reduce the Implementing FinFET in high-volume manufacturing coupling through use of a lower dielectric constant layer requires chip makers to integrate complex process REFERENCES between them, such as a low-κ spacer, will be needed. technology solutions in patterning, new materials, [1] R. Dennard, et al., “Design of Ion-Implanted MOSFETs ultra-thin deposition of films, and conformal doping. with Very Small Physical Dimensions,” IEEE Journal Forming Extension Regions for Source-Drain Structures of Solid State Circuits, Vol. SC-9, No. 5, pp. 256-268, The extension regions are small areas at the tips of SOI technology has been in production for many years October 1974. the channel that are in contact with source and drain at IBM and its alliance partners. UTB-SOI is an evolution terminals. They extract current from the channel and of this technology in which the silicon body thickness [2] C. Hu, “Silicon Nanoelectronics for the 21st Century,” pass it to the source and drain. They need to have will radically shrink from 30nm today to a possible Nanotechnology, pp. 113-116, June 1999. low electrical resistance to minimize power losses 5nm in the future. The UTB-SOI approach continues [3] D. Hisamoto, et al., “FinFET—A Self-Aligned Double- Figure 4 Gate MOSFET Scalable to 20nm,” IEEE Transactions on Electron Devices, Vol. 47, No. 12, pp. 2320-2325, Figure 4. On-state current nFET pFET December 2000. for transistors with different Planar (Production) Planar (Production) FinFET (R&D) FinFET (R&D) [4]  architectures based on best UTB-SOI (R&D) UTB-SOI (R&D) “Intel Reinvents Transistors Using New 3-D research data published in 1.8 1.8 Structure,” retrieved 5/4/2011, 1.6 1.6 the literature. 1.4 1.4 http://newsroom.intel.com/community/intel_ 1.2 1.2 newsroom/blog/2011/05/04/intel-reinvents- 1.0 1.0 ent (mA/µm ) ent (mA/µm ) transistors-using-new-3-d-structure. 0.8 0.8 0.6 0.6

On Curr 0.4 On Curr 0.4 0.2 0.2 0 0 10 100 10 100 Channel Length (nm) Channel Length (nm)

7 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Thin-Channel Transistors

and to retain a good on-state channel current for high the planar CMOS architecture with minimal change in AUTHORS performance. Higher doping can lower the resistance; manufacturing flow. A significant challenge, however, Khaled Ahmed is a distinguished member of technical however, ion beam implantation can cause crystalline lies in manufacturing the substrate as thickness variation staff in the Silicon Systems Group at Applied Materials. damage to these thin regions, worsening the resistance must be in the vanishingly small range of 0.5nm. This is He holds his Ph.D. in electrical engineering from North problem. Novel doping techniques based on epitaxial a key reason that UTB-SOI technology has not yet been Carolina State University. growth and controlled diffusion will be enabling adopted for high-volume manufacturing. Balaji Chandrasekaran is a marketing programs manager solutions for future nodes. A key difference between FinFET and UTB-SOI designs in the Silicon Systems Group at Applied Materials. He Gate Stack Deposition is in the thickness of thin silicon body. The UTB-SOI earned his M.S. in materials science and engineering The gate insulator electrical thickness required will be requires a silicon body two times thinner than that of the from Northwestern University and an MBA from the extremely small, approximately 0.5nm for a 7nm device. FinFET, which leaves FinFET more flexibility to continue University of California at Berkeley. Precise control with minimal variability in thickness will scaling. One possible work-around for this issue is Kathryn Ta is a senior director and head of marketing be a big challenge to overcome. ALD technology is likely for UTB-SOI to employ back-gate biasing, in which a for the Silicon Systems Group at Applied Materials. to be required to deliver the needed precision. The metal second gate is built below the buried oxide for greater She received her Ph.D. in chemical engineering from gate electrodes must also be precisely manufactured, electrostatic control and reduced off-state current. the University of California at Berkeley. requiring CVD or ALD technologies in addition to CONCLUSION physical vapor deposition technologies, to fill small Klaus Schuegraf is a corporate vice president and chief The industry debate between FinFET and UTB-SOI gaps and maintain good transistor performance. technology officer of the Silicon Systems Group at approaches is an example of the classic dilemma of Applied Materials. He holds his Ph.D. in electrical REVOLUTION VERSUS EVOLUTION IN choosing revolution or evolution. Both approaches can engineering from the University of California at Berkeley. ADVANCED TRANSISTOR ARCHITECTURES be excellent strategies. A revolutionary approach FinFET and UTB-SOI were conceived a decade ago and requires large-scale investment, with greater risks by ARTICLE CONTACT both effectively address the long-term quest for low off- radically changing the transistor design and process [email protected] state current. Both have demonstrated the ability to scale flow, but it can also bring longer-term yield, performance, down the channel length to less than 25nm (Figure 4). and extendibility advantages. An evolutionary approach reduces risk, required investment, and time-to-market. Implementing FinFET in high-volume manufacturing requires chip makers to integrate complex process REFERENCES technology solutions in patterning, new materials, [1] R. Dennard, et al., “Design of Ion-Implanted MOSFETs ultra-thin deposition of films, and conformal doping. with Very Small Physical Dimensions,” IEEE Journal of Solid State Circuits, Vol. SC-9, No. 5, pp. 256-268, SOI technology has been in production for many years October 1974. at IBM and its alliance partners. UTB-SOI is an evolution of this technology in which the silicon body thickness [2] C. Hu, “Silicon Nanoelectronics for the 21st Century,” will radically shrink from 30nm today to a possible Nanotechnology, pp. 113-116, June 1999. 5nm in the future. The UTB-SOI approach continues [3] D. Hisamoto, et al., “FinFET—A Self-Aligned Double- Figure 4 Gate MOSFET Scalable to 20nm,” IEEE Transactions on Electron Devices, Vol. 47, No. 12, pp. 2320-2325, nFET pFET December 2000. Planar (Production) Planar (Production) FinFET (R&D) FinFET (R&D) [4]  UTB-SOI (R&D) UTB-SOI (R&D) “Intel Reinvents Transistors Using New 3-D 1.8 1.8 Structure,” retrieved 5/4/2011, 1.6 1.6 1.4 1.4 http://newsroom.intel.com/community/intel_ 1.2 1.2 newsroom/blog/2011/05/04/intel-reinvents- 1.0 1.0 ent (mA/µm ) ent (mA/µm ) transistors-using-new-3-d-structure. 0.8 0.8 0.6 0.6

On Curr 0.4 On Curr 0.4 0.2 0.2 0 0 10 100 10 100 Channel Length (nm) Channel Length (nm)

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 8 These challenges are at the forefront of the pursuit of SCALING DIELECTRIC an ultimate gap-fill solution offering good film quality at low thermal budgets. Similar requirements apply to logic FinFET ILD, slit fill for vertical NAND, and DRAM GAP FILL 4F2 buried bit line (Figure 1). A recently developed fluid- With Flowable Chemical Vapor Deposition like, profile-insensitive CVD oxide is showing excellent promise in satisfying these requirements in a variety of applications. KEYWORDS With continued scaling of memory and logic devices, FLOWABLE CVD DEPOSITION Gap Fill though, the combined challenge of smaller feature Flowable CVD deposition occurs through the reaction Interlayer Dielectric size and reduced tolerance for thermal and oxidative of a carbon-free silicon precursor and inorganic reactant Flowable CVD treatments must be addressed. These challenges are gas, resulting in condensation of a low-viscosity film Low-Viscosity Film most evident in interlayer dielectric (ILD) in logic and Re-Entrant Profiles dynamic random access memory (DRAM) for which upon the wafer substrate. During deposition, the film Liner-Free Integration a novel dielectric gap-fill approach is required by flows to the bottom of the gap, producing true bottom- the 2x nm node. up, profile-insensitive film growth. This behavior was In logic, the drive for optimal transistor performance tested using a re-entrant structure shape with a gap motivates the continued use of nitride strain films width of 7nm and total height of 420nm created by that create a re-entrant gap between adjacent gates. depositing silicon dioxide atop a 40nm shallow trench Logic ILD0 has traditionally been filled with high- isolation structure (Figure 2). The carbon-free chemistry density plasma CVD (HDP-CVD) or sub-atmospheric used creates high-density, non-porous silicon dioxide At the 2X nm node and beyond, gap fill becomes a CVD (SACVD). In the case of HDP-CVD, a high-density, and ensures the absence of fixed charge. daunting challenge for conventional chemical vapor inductively coupled plasma enhances the chemical deposition process while chemical and physical etch BLANKET FILM QUALITY STUDIES deposition (CVD) given the combination of smaller feature with high bias maintain an open gap for continued fill. Film composition of flowable CVD was assessed by size, aggressive aspect ratios, re-entrant profiles, and While HDP-CVD remains a workhorse of the industry Fourier transform infra-red spectroscopy (FTIR) and reduced tolerance for thermal and oxidative treatments. for both blanket and gap-fill applications, its dependence A new low-temperature process clears these hurdles atomic emission spectroscopy (AES), while dielectric on line-of-sight for the physical etch restricts its use breakdown (V ) was assessed with a mercury by creating a fluid-like film capable of true bottom-up, bd in high aspect ratio straight and re-entrant structures. profile-insensitive, void-free fill. A high-quality film that probe (Figure 3). All measurements were performed SACVD employs a high partial pressure of ozone to compares favorably with industry-standard high-density after <150˚C oxidative and additional inert ambient achieve thermal deposition of conformal silicon-dioxide plasma CVD silicon dioxide, it offers the additional thermal treatments. at low temperature (<550˚C). Void-free gap fill with a compelling advantage of enabling liner-free integration with conformal film, however, requires a constant taper of metal films commonly used in logic and memory devices. the sidewall. In the case of sidewall angles exceeding Dielectric gap fill is a critical step in manufacturing 89˚ or a re-entrant structure profile, void-free fill cannot Figure 3

semiconductor devices. Chemical vapor deposition (CVD) be achieved with this approach. Spin-on dielectrics have Si-O Stretching FCVD (1085 cm-1) 1E-02 HDP Oxide has historically enabled the void-free fill of pure, dense also been considered for the ILD0 application; however oxides for metal isolation in semiconductors. CVD’s poor film quality, lack of film purity, and severe leakage 1E-04 issues after contact etch have restricted its adoption. excellent oxide quality, high breakdown voltage, and 1E-06 Si-O Rocking (477 cm-1) good substrate adhesion have ensured low leakage and In DRAM, by the 2x nm node, gate pitch scaling in the (A ) Si-O Bending 1E-08 -1 V the absence of parasitic capacitance. These properties periphery forms narrow gaps (<20nm) and high aspect (812 cm ) bd Current also preclude the integration challenges of alternative ratios (>10:1) for ILD1. While reflow of boron- and Intensity (au) 1E-10 solutions, including mobile and fixed charge. CVD phosphorous-doped SACVD glass (BPSG) films has 1E-12 oxides have proven robust in post-processing steps, ensured void-free fill at previous nodes, lower thermal including contact etch, chemical mechanical budget (<700˚C) to address junction leakage challenges 1E-14 4000 3500 3000 2500 2000 1500 1000 500 0 012345678910 planarization (CMP), and wet cleans, securing their elsewhere on the device limits the continued use of Wavelength (cm-1) Field (MV/cm) role in critical gap-fill applications. BPSG films. (a) (b)

9 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Flowable Gap Fill

These challenges are at the forefront of the pursuit of FTIR and AES studies were performed on 5000Å SCALING DIELECTRIC an ultimate gap-fill solution offering good film quality deposits while dielectric breakdown was assessed on at low thermal budgets. Similar requirements apply to 2000Å films. The AES and FTIR demonstrate a pure, logic FinFET ILD, slit fill for vertical NAND, and DRAM stoichiometric Si-O film without detectable carbon or GAP FILL 4F2 buried bit line (Figure 1). A recently developed fluid- nitrogen impurities. A dielectric breakdown test was With Flowable Chemical Vapor Deposition like, profile-insensitive CVD oxide is showing excellent performed on 2000Å blanket wafers and demonstrated promise in satisfying these requirements in a variety of high breakdown voltage (Vbd >8MV) with low applications. leakage (<1nA @ 1MV/cm). These results closely matched industry-standard, high-quality HDP-CVD With continued scaling of memory and logic devices, FLOWABLE CVD DEPOSITION though, the combined challenge of smaller feature silicon dioxide films that were used as a reference. Flowable CVD deposition occurs through the reaction size and reduced tolerance for thermal and oxidative of a carbon-free silicon precursor and inorganic reactant Figure 1 treatments must be addressed. These challenges are most evident in interlayer dielectric (ILD) in logic and gas, resulting in condensation of a low-viscosity film Figure 1. Dielectric dynamic random access memory (DRAM) for which upon the wafer substrate. During deposition, the film gap-fill technology faces a novel dielectric gap-fill approach is required by flows to the bottom of the gap, producing true bottom- unprecedented challenges in the 2x nm node. up, profile-insensitive film growth. This behavior was (a) logic FinFET ILD, (b) slit fill for vertical NAND, In logic, the drive for optimal transistor performance tested using a re-entrant structure shape with a gap 2 motivates the continued use of nitride strain films width of 7nm and total height of 420nm created by and (c) DRAM 4F buried that create a re-entrant gap between adjacent gates. depositing silicon dioxide atop a 40nm shallow trench bit line. Logic ILD0 has traditionally been filled with high- isolation structure (Figure 2). The carbon-free chemistry density plasma CVD (HDP-CVD) or sub-atmospheric used creates high-density, non-porous silicon dioxide (a) (b)(c) CVD (SACVD). In the case of HDP-CVD, a high-density, and ensures the absence of fixed charge. inductively coupled plasma enhances the chemical deposition process while chemical and physical etch BLANKET FILM QUALITY STUDIES Figure 2 with high bias maintain an open gap for continued fill. Film composition of flowable CVD was assessed by Figure 2. (a) Flowable CVD While HDP-CVD remains a workhorse of the industry Fourier transform infra-red spectroscopy (FTIR) and deposition enables partial fill for both blanket and gap-fill applications, its dependence atomic emission spectroscopy (AES), while dielectric and (b) complete fill of features on line-of-sight for the physical etch restricts its use breakdown (Vbd) was assessed with a mercury with re-entrant profiles and in high aspect ratio straight and re-entrant structures. probe (Figure 3). All measurements were performed aggressive aspect ratios. SACVD employs a high partial pressure of ozone to after <150˚C oxidative and additional inert ambient achieve thermal deposition of conformal silicon-dioxide thermal treatments. (a) (b) at low temperature (<550˚C). Void-free gap fill with a Applied Materials internal data conformal film, however, requires a constant taper of the sidewall. In the case of sidewall angles exceeding 89˚ or a re-entrant structure profile, void-free fill cannot Figure 3 be achieved with this approach. Spin-on dielectrics have Si-O Stretching FCVD Figure 3. (a) FTIR spectroscopy (1085 cm-1) 1E-02 HDP Oxide also been considered for the ILD0 application; however confirms the purity of the poor film quality, lack of film purity, and severe leakage 1E-04 flowable CVD oxide; issues after contact etch have restricted its adoption. 1E-06 (b) high breakdown voltage Si-O Rocking (477 cm-1) In DRAM, by the 2x nm node, gate pitch scaling in the (A ) demonstrates superior Si-O Bending 1E-08 -1 V periphery forms narrow gaps (<20nm) and high aspect (812 cm ) bd electrical performance. Current ratios (>10:1) for ILD1. While reflow of boron- and Intensity (au) 1E-10 phosphorous-doped SACVD glass (BPSG) films has 1E-12 ensured void-free fill at previous nodes, lower thermal budget (<700˚C) to address junction leakage challenges 1E-14 4000 3500 3000 2500 2000 1500 1000 500 0 012345678910 elsewhere on the device limits the continued use of Wavelength (cm-1) Field (MV/cm) BPSG films. (a) (b)

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 10 Flowable Gap Fill

Figure 4 Figure 6

Figure 4. STEM-EELS line EELS Atomic Concentration Profile <200°C Oxide Pre <200°C Oxide Post Steam Anneals 100 20nm, >10:1 scan analysis reveals pure Scan Direction W Oxide 90 silicon dioxide film within Substrate O 80 Si No W Oxidation TiN the structure. 70 N No TiN Oxidation 60 W W SiO 50 2 mposition (% ) Co

40 Applied Materials internal data 30 lati ve

Re 20 hydrofluoric acid diluted 100:1 in de-ionized water for 10 Nitride on Substrate No N Detected exposure times ranging from 1 minute to 8 minutes. 0 SEM cross-sections were generated for each sample 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 µm and the height of remaining oxide within the trench was measured from the silicon-pad nitride interface and IN-TRENCH FILM QUALITY STUDIES similar thermal budget used in production today, analysis plotted. A constant recess rate was measured (Figure 5), While blanket properties of deposited films are useful, focused on STEM-EELS for detailed characterization. confirming uniform film properties as a function of depth. the blanket material is typically removed during CMP, STEM-EELS line scan analysis was performed at 0.5nm hence it is important to confirm oxide formation and intervals from the substrate up through narrow (20nm MATERIAL COMPATIBILITY uniform film quality within structures as well. The wide, 200nm deep) trench structures to the top of the Titanium-nitride (TiN) and tungsten (W) are metals in-trench film quality for flowable CVD was assessed film. TEM samples were prepared by focused ion beam commonly used in logic and memory as electrodes, using side-decorated SEMs, scanning transmission milling to a target thickness of 50nm. The areal density contacts, and conductive lines. Both exhibit metal electron microscope electron energy loss spectroscopy and relative atomic concentrations of the targeted oxide growth with low-temperature steam anneal. For (STEM-EELS), and analysis of the recess rate within the electrodes and narrow conductive lines, such as buried structures after CMP removal of the overburden. Before elements (carbon, nitrogen, oxygen, and silicon) were analysis, all deposits were subjected to <150˚C oxidative extracted from the EELS data at each point and recorded bit and word lines employed in advanced DRAM, the and <600˚C thermal treatment in inert ambient. in the profile measurements. Results demonstrate a resistance change resulting from oxidation must be Deposition was tuned to achieve completely void-free pure silicon dioxide film to within detection limits of the restricted to ensure proper device function. The ability gap fill with an overburden of 1500Å or more. test methodology, estimated to be on the order of two to deposit an oxide film directly on a metal surface atomic percent for impurities (Figure 4). without a nitride liner offers great freedom to reduce The flowable CVD film was first characterized by SEM on 35nm x 250nm shallow trench isolation structures. To further test the film quality uniformity as a function integration complexity, implement novel device Decoration with aggressive wet etchant (BOE 6:1, 6”) of depth, flowable CVD was deposited and post-treated architectures, and scale devices to narrower pitch. was applied following wafer cleave to highlight density on shallow trench isolation structure wafers after which The ability to integrate flowable CVD film without variations within the film. As results showed reasonable the overburden was removed by CMP, stopping on pad nitride liner was assessed through high-resolution in-trench film quality comparable to SACVD oxides of nitride. Samples were placed in a circulating bath of transmission electron microscope (TEM) studies of Figure 5 metal oxidation, using a 200kV FEI/Phillips W source

Figure 5. A constant recess 100 TEM with samples prepared by focused ion beam milling. rate of oxide remaining within 0 Physical vapor deposition was used to generate 400Å

sition (nm) -100 shallow trench isolation Po CD = 45nm TiN substrates and 400Å W substrates were generated -200 CD = 70nm cess using metal oxide CVD on TiN substrates. Flowable structures confirmed uniform Re -300 02468 CVD was deposited and <150˚C oxidative and <600˚C film properties as a function Etch Time (min) of depth. CD45 0min 2min 4min 6min 8min thermal treatments in inert ambient were applied. Both TiN and W images demonstrate no change in appearance following flowable CVD deposition and post-treatment (Figure 6). For reference, an additional CD70 W sample was subjected to a 400˚C, 60-minute steam anneal; oxide formation appears clearly on the image (Figure 6), demonstrating the sensitivity of TEM methodology to the presence of oxide. Applied Materials internal data

11 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Flowable Gap Fill

Figure 4 Figure 6

EELS Atomic Concentration Profile <200°C Oxide Pre <200°C Oxide Post Steam Anneals Figure 6. Flowable CVD 100 20nm, >10:1 Scan Direction W Oxide offers potential for liner-free 90 Substrate O integration with W and TiN 80 Si No W Oxidation TiN films. 70 N No TiN Oxidation 60 W W SiO 50 2 mposition (% ) Co

40 Applied Materials internal data 30 lati ve

Re 20 hydrofluoric acid diluted 100:1 in de-ionized water for CONCLUSION 10 Nitride on Substrate No N Detected exposure times ranging from 1 minute to 8 minutes. Flowable CVD is a material that answers the need for 0 SEM cross-sections were generated for each sample profile-insensitive, void-free dielectric gap-fill oxide of 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 µm and the height of remaining oxide within the trench was re-entrant gaps of <7nm width and aspect ratios >50:1. measured from the silicon-pad nitride interface and Carbon-free chemistry creates a pure silicon dioxide similar thermal budget used in production today, analysis plotted. A constant recess rate was measured (Figure 5), whose properties compare favorably with industry- focused on STEM-EELS for detailed characterization. confirming uniform film properties as a function of depth. standard, high-quality HDP-CVD silicon dioxide. The STEM-EELS line scan analysis was performed at 0.5nm low oxidative budget (<150˚C) process flow gives MATERIAL COMPATIBILITY intervals from the substrate up through narrow (20nm flowable CVD the compelling advantage of liner-free Titanium-nitride (TiN) and tungsten (W) are metals wide, 200nm deep) trench structures to the top of the integration compatibility with W and TiN metal films. film. TEM samples were prepared by focused ion beam commonly used in logic and memory as electrodes, milling to a target thickness of 50nm. The areal density contacts, and conductive lines. Both exhibit metal ACKNOWLEDGEMENTS and relative atomic concentrations of the targeted oxide growth with low-temperature steam anneal. For The authors wish to acknowledge the support and elements (carbon, nitrogen, oxygen, and silicon) were electrodes and narrow conductive lines, such as buried guidance of Ajay Bhatnagar and Shankar Venkataraman extracted from the EELS data at each point and recorded bit and word lines employed in advanced DRAM, the of the Gap Fill division of the Dielectric Systems and in the profile measurements. Results demonstrate a resistance change resulting from oxidation must be Modules business unit at Applied Materials. pure silicon dioxide film to within detection limits of the restricted to ensure proper device function. The ability AUTHORS test methodology, estimated to be on the order of two to deposit an oxide film directly on a metal surface Tushar Mandrekar is a global product manager in the atomic percent for impurities (Figure 4). without a nitride liner offers great freedom to reduce Silicon Systems Group at Applied Materials. He holds To further test the film quality uniformity as a function integration complexity, implement novel device masters degrees in physics and materials science from of depth, flowable CVD was deposited and post-treated architectures, and scale devices to narrower pitch. the University of Illinois at Urbana-Champaign. on shallow trench isolation structure wafers after which The ability to integrate flowable CVD film without Jingmei Liang is a senior engineering manager in the the overburden was removed by CMP, stopping on pad nitride liner was assessed through high-resolution Silicon Systems Group at Applied Materials. She earned nitride. Samples were placed in a circulating bath of transmission electron microscope (TEM) studies of her Ph.D. in chemical engineering and materials science Figure 5 metal oxidation, using a 200kV FEI/Phillips W source from the University of Minnesota. TEM with samples prepared by focused ion beam milling. 100 Abhijit Basu Mallick is a process engineer in the Silicon 0 Physical vapor deposition was used to generate 400Å Systems Group at Applied Materials. He received his sition (nm) -100

Po CD = 45nm TiN substrates and 400Å W substrates were generated -200 CD = 70nm Ph.D. in chemistry from Cornell University and was a cess using metal oxide CVD on TiN substrates. Flowable Re -300 post-doctorate scholar at Stanford University. 02468 CVD was deposited and <150˚C oxidative and <600˚C Etch Time (min) Nitin Ingle is a technology director in the Silicon CD45 0min 2min 4min 6min 8min thermal treatments in inert ambient were applied. Systems Group at Applied Materials. He holds his Ph.D. Both TiN and W images demonstrate no change in in chemical engineering from the State University of appearance following flowable CVD deposition and New York in Buffalo. post-treatment (Figure 6). For reference, an additional CD70 W sample was subjected to a 400˚C, 60-minute steam ARTICLE CONTACT [email protected] anneal; oxide formation appears clearly on the image (Figure 6), demonstrating the sensitivity of TEM PROCESS SYSTEM USED IN STUDY methodology to the presence of oxide. Applied Producer® Eterna™ CVD Applied Materials internal data

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 12 Figure 1 CMP APPLICATIONS ARRIVE PMD Spacer

PMD Spacer PMD Spacer Spacer Mask Mask Mask PMD Poly Poly Poly Poly Spacer Stress Liner Spacer Spacer Spacer Stress Liner Stress Liner Stress Liner S D AT THE GATE STACK S D S D S D Enabling Advanced Transistors Incoming Stop in OxideStop on Nitride Poly Open shows the progression of CMP and the resultant gate stack change in a three-platen polishing tool. KEYWORDS The transition from aluminum to copper wiring in BEOL Chemical Mechanical starting at the 130nm node effected a major change Polishing of the incoming oxide film begins on the first Planarization when damascene copper CMP was introduced, soon platen as the uneven surface topography is planed Process Control becoming the industry standard for multi-level inter- down to reach a desired remaining stop-in-film thickness Multi-Zone Polishing connect fabrication. Today, CMP is seeing the determined by a targeted incoming burden for the next Gate CMP next big change as it becomes a transistor-enabling platen polish. On the second platen, the film becomes FinFETs technology. CMP processes now stop directly on the more planar and the oxide film is removed, exposing gate stack, control its height, and play a more defining Contact CMP the nitride film surface, where the process stops owing role in transistor fabrication (Table 1). A growing number of chemical mechanical planarization to the selective nature of the chemistry. Both a highly (CMP) applications are arriving at the transistor gate. They Starting at 45nm, Intel introduced high-κ metal gate selective ceria slurry process or a fixed-abrasive platen play a crucial technology-enabling role in sustaining Moore’s structures (HKMG) in their transistors to sustain process provide the desired oxide-to-nitride rate [1] Law, first in creating flat reference planes for lithography Moore’s Law. Two key planarization applications were selectivity; however, the latter also offers the inherent depth-of-focus resolution and second in polish-back of introduced at that time, namely the dummy gate-open advantage of avoiding dishing in larger trenches.[9] On [2] materials in a damascene mode to form the patterned gate CMP and replacement metal gate CMP processes. the third platen, the films are non-selectively polished stack structures. Accompanying their growing adoption is [3] The advent of FinFETs starting at 22nm will add until the surface of the poly gate is exposed and the the heightened requirement for extremely controlled process a dummy gate planarization step that will be a key nitride film is fully removed. performance in terms of film thickness and uniformity that is technology enabler for the subsequent etching of the being addressed by a portfolio of process control and multi- 3D structures.[4] Advanced DRAM memory devices are The stop-in-film and stop-on-film processes of the first zone polishing-head technologies. employing a planarization process for the gate metal prior two platens are more established in comparison to the Since its introduction in the planarization of multi-level to a recess etch step to form the buried gate structures.[5] process on the third platen, which is relatively new and inter-layer dielectric (ILD) films for isolating aluminum In addition, CMP applications in tungsten contact for challenging in terms of its process requirements. The wiring in the back end of line (BEOL), CMP has steadily local interconnects also stop at the transistor gate. In third process requires an almost 1:1 removal rate between expanded into multiple processes over the last two the future, high-mobility channel materials such as III-V oxide and nitride, a very low removal rate for poly (almost decades. The adoption of shallow trench isolation (STI) materials for nFET and germanium for pFET are likely stop-on-poly), and simultaneously optimizing multiple structures in place of local oxidation of silicon (LOCOS) to be introduced and their incorporation into silicon will parameters for the different materials. In addition, it gave rise to STI CMP, which was soon followed by CMP require a damascene-style process to polish back these must result in very shallow field-oxide dishing and of tungsten films in transistor contacts for higher device novel materials.[6] This article reviews these new CMP minimal poly loss across various gate widths throughout yield. applications and their process challenges. As the the die and the wafer. [7,8] Table 1 industry converges on the gate-last HKMG scheme, the first two of these applications appear poised to From a device standpoint, the process on the third Table 1. CMP applications Then Now and Future become industry standards in the next few years. platen determines the transistor gate height and thus are multiplying as STI CMP STI CMP warrants extreme control of process variation. But the the process takes on ILD 1 (PMD) CMP High-Mobility Channels CMP* DUMMY GATE-OPEN CMP FOR a technology-enabling role. Tungsten CMP Dummy Gate CMP (FinFET)* GATE-LAST HKMG two previous steps require the same degree of control, Copper With the introduction of the gate-last scheme for because the variation originating from them compounds Dummy Gate-Open CMP (HKMG)* Damascene CMP HKMG, the conventional ILD layer 1 CMP changes the variability of the entire process. The thickness Replacement Metal Gate CMP (HKMG)* from a single material (oxide) stop-in-film removal uniformity variation in incoming lots (within die, within Tungsten CMP for Advanced Contacts* to a multi-material removal process, resulting in the wafer, and wafer to wafer) must be tightly controlled at Copper Damascene CMP opening of the dummy poly gate structure. Figure 1 each platen. *Applications coming to the transistor gate stack

13 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Expanding CMP Applications

Figure 1 CMP APPLICATIONS ARRIVE PMD Figure 1. Dummy gate-open CMP sequence through Spacer

PMD Spacer PMD Spacer Spacer Mask Mask Mask PMD Poly polysilicon gate open, ready Poly Poly Poly Spacer Stress Liner Spacer Spacer Spacer Stress Liner Stress Liner Stress Liner S D for polysilicon removal. AT THE GATE STACK S D S D S D Enabling Advanced Transistors Incoming Stop in OxideStop on Nitride Poly Open shows the progression of CMP and the resultant gate On the first and third platens, in-situ endpoint stack change in a three-platen polishing tool. technology using broadband white light enables real- The transition from aluminum to copper wiring in BEOL time monitoring and endpoint control of the remaining starting at the 130nm node effected a major change Polishing of the incoming oxide film begins on the first film thickness. In combination with real-time feedback when damascene copper CMP was introduced, soon platen as the uneven surface topography is planed to the polishing heads, in-situ profile control technology becoming the industry standard for multi-level inter- down to reach a desired remaining stop-in-film thickness on the first and third platens can control within-wafer connect fabrication. Today, CMP is seeing the determined by a targeted incoming burden for the next uniformity. Motor torque endpoint (friction-based next big change as it becomes a transistor-enabling platen polish. On the second platen, the film becomes sensing) on the second platen for accurate stop-on- technology. CMP processes now stop directly on the more planar and the oxide film is removed, exposing nitride can minimize over-polish and reduce dishing. gate stack, control its height, and play a more defining the nitride film surface, where the process stops owing Within the dies, performance is determined by the role in transistor fabrication (Table 1). to the selective nature of the chemistry. Both a highly slurry, pads, or fixed-abrasive web used. Multi-zone Starting at 45nm, Intel introduced high-κ metal gate selective ceria slurry process or a fixed-abrasive platen polishing-head technology achieves the required structures (HKMG) in their transistors to sustain process provide the desired oxide-to-nitride rate center-to-edge wafer uniformity tuning and control. [1] Moore’s Law. Two key planarization applications were selectivity; however, the latter also offers the inherent The combination of endpoint capabilities, process introduced at that time, namely the dummy gate-open advantage of avoiding dishing in larger trenches.[9] On monitoring and control, and multi-zone polishing [2] CMP and replacement metal gate CMP processes. the third platen, the films are non-selectively polished pressure control is crucial for achieving the necessary [3] The advent of FinFETs starting at 22nm will add until the surface of the poly gate is exposed and the precision. a dummy gate planarization step that will be a key nitride film is fully removed. technology enabler for the subsequent etching of the REPLACEMENT METAL GATE CMP FOR 3D structures.[4] Advanced DRAM memory devices are The stop-in-film and stop-on-film processes of the first GATE-LAST HKMG employing a planarization process for the gate metal prior two platens are more established in comparison to the A second CMP step needed in HKMG fabrication is to a recess etch step to form the buried gate structures.[5] process on the third platen, which is relatively new and the metal gate process in which the dummy poly gate In addition, CMP applications in tungsten contact for challenging in terms of its process requirements. The material is replaced by aluminum. Here CMP is an local interconnects also stop at the transistor gate. In third process requires an almost 1:1 removal rate between enabling technology in a damascene mode in which the future, high-mobility channel materials such as III-V oxide and nitride, a very low removal rate for poly (almost the deposited metal is fully polished back to isolate the individual transistor gates. Aluminum metal is materials for nFET and germanium for pFET are likely stop-on-poly), and simultaneously optimizing multiple employed as the gate electrode and has an incoming to be introduced and their incorporation into silicon will parameters for the different materials. In addition, it require a damascene-style process to polish back these topography from the PVD metal gap-fill process into must result in very shallow field-oxide dishing and novel materials.[6] This article reviews these new CMP the gate trenches. The films are planarized and polished minimal poly loss across various gate widths throughout applications and their process challenges. As the back to remove the work function metals and barrier the die and the wafer. industry converges on the gate-last HKMG scheme,[7,8] materials from the field-oxide areas, leaving the the first two of these applications appear poised to From a device standpoint, the process on the third aluminum metal fill in the trenches (Figure 2). become industry standards in the next few years. platen determines the transistor gate height and thus From a device standpoint, aluminum CMP stops on DUMMY GATE-OPEN CMP FOR warrants extreme control of process variation. But the the gate and determines the gate height. Therefore, GATE-LAST HKMG two previous steps require the same degree of control, extreme control of process variation for thickness and With the introduction of the gate-last scheme for because the variation originating from them compounds uniformity is needed within die, within wafer, and wafer HKMG, the conventional ILD layer 1 CMP changes the variability of the entire process. The thickness to wafer. Real-time profile control can be employed to from a single material (oxide) stop-in-film removal uniformity variation in incoming lots (within die, within govern the polishing process at each platen. For the to a multi-material removal process, resulting in the wafer, and wafer to wafer) must be tightly controlled at metal removal, an in-pad eddy-current sensor that opening of the dummy poly gate structure. Figure 1 each platen. senses a signal proportional to the amount of metal

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 14 Expanding CMP Applications

Figure 2 Figure 4

Figure 2. Replacement CMP Stop with Tungsten Structures Etched Work Work Incoming Wafer Thin Tungsten Remaining for BWL Formation metal gate CMP sequence Function Al Function Metal Metal Barrier Barrier Barrier Spacer planarizing incoming Spacer Spacer Barrier PMD Al PMD Al PMD Spacer Spacer aluminum film through Spacer Stress Liner Stress Liner Stress Liner WWW S D S D S D gate isolation. Post-Aluminum Gap Fill Stop in Aluminum Stop on Oxide Source: References 5,10. Barrier

remaining is used and adjusts polishing-head pressure too short a gate and under-polishing can cause too tall a parameter that must be tightly controlled die to die, to control thickness and uniformity. Within-die uniformity a gate, which can affect the current carrying ability of within wafer, and wafer to wafer for consistent is determined by the selection of appropriate slurry and the word line. Post-polish gate height must therefore transistor performance. Hence, the post-CMP remaining polishing pads. be stringently controlled within a range less than 50Å, film thickness (stopping within-film) and uniformity both within wafer and wafer to wafer.[3] control is paramount and real-time profile control Aluminum is a softer metal than copper; consequently technology can be an enabler. defectivity (e.g., scratching) control is more challenging. In-situ endpoint technology with broadband white light The polishing process should not leave aluminum can offer the necessary control. The polysilicon film As in the case of the gate-last HKMG application, a residue or particles in the field oxide and should also be has a high refractive index and high reflected signal novel in-pad sensor measures the eddy-current signal, selective to minimize field-oxide loss. It must also intensity. The broadband light spectrum collected which is proportional to the amount of metal remaining. completely remove the work function and barrier from in-situ metrology can provide fine resolution to This capability has been developed recently for materials in the field while producing low topography accurately stop within the film at the targeted thickness. tungsten[11] and provides a high degree of resolution. from dishing and erosion within the die. A three-platen The combination of endpoint metrology with multi-zone The DRAM industry is researching a transition to 4F2 CMP configuration offers considerable flexibility on polishing pressure can yield a tight within-wafer range cell size, which will employ a buried bit-line architecture consumables and process control to address these in real time. Using pads and slurries that offer high (BBL) in addition to BWL.[12] BBL creates an additional multiple requirements. planarization efficiency achieves the desired within-die application for tungsten CMP with the same set of thickness control. challenges as those noted above. DUMMY GATE CMP FOR FINFETS The transition from planar CMOS transistor designs to GATE CMP FOR BURIED WORD CONTACT CMP FOR LOCAL INTERCONNECTS FinFETs creates a new CMP step in the planarization of LINE DRAM MEMORY In 2009, Intel announced their second-generation dummy gate polysilicon films. In the planar transistor, Recently, the DRAM industry has begun to migrate contacts with local interconnect technology for their the deposited polysilicon film has a flat topography to buried word line (BWL) transistors to gain the 32nm node microprocessor.[13] In this device, the requiring no CMP, but in FinFET designs, the same advantages of reduced parasitic capacitance (in both tungsten contacts are polished down to the transistor deposited film has an uneven surface topography bit line and word line directions), smaller die size, and gate level, determining the gate height (Figure 5). that must be planarized before gate etch. This uneven low-power operation.[10] CMP is an enabling technology These trench-design contacts have lower resistance. topography arises from a prior process in forming the in planarization of the metal gate film prior to the Similar to the gate-last HKMG application, this silicon fins wherein the recesses of the STI oxide film recess etch process in BWL transistor fabrication.[5] application is a damascene process in which tungsten create an underlying topography for the subsequent and the barrier metals are polished back to endpoint on Tungsten or titanium nitride (TiN) films are the leading polysilicon film deposition. oxide (Figure 5). Tight control of thickness and uniformity candidates for the gate. They present an uneven surface variation are paramount to the manufacturability of this The primary value of this CMP application is to create topography following the gap-fill process into the silicon application. As in the BWL application, real-time profile a flat reference plane with depth-of-focus resolution trenches. Forming a flat reference plane with CMP is control can enable the required precision of thickness to enable critical lithography exposure and gate stack critical to enable a precisely controlled etch process and uniformity control. etch (Figure 3). Because it stops on the transistor gate, (Figure 4). This process has a direct impact on the final it controls the gate height. Over-polishing can cause height of the buried metal gate inside the trenches, FUTURE CMP APPLICATIONS IN HIGH-MOBILITY CHANNEL MATERIALS Figure 3 Research is actively being pursued in quantum well field Figure 3. In FinFET fabrication, effect transistors (QWFET), which are seen as promising CMP creates a flat reference candidates for next-generation transistors.[14] These plane with depth-of-focus Poly Poly transistors can enable high-speed performance at very resolution lithography STI STI STI Si Si Si low supply voltages, offering promise of a new era of exposure and gate stack etch. ultra-low-power computing.

15 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Expanding CMP Applications

Figure 4

CMP Stop with Tungsten Structures Etched Figure 4. In BWL transistors, Work Work Incoming Wafer Thin Tungsten Remaining for BWL Formation Function Al Function CMP produces a flat plane Metal Metal Barrier Barrier Barrier Spacer Spacer Spacer Barrier of reference and controlled PMD Al PMD Al PMD Spacer Spacer Spacer Stress Liner Stress Liner Stress Liner WWW incoming film thickness for S D S D S D the subsequent etch process. Post-Aluminum Gap Fill Stop in Aluminum Stop on Oxide Source: References 5,10. Barrier too short a gate and under-polishing can cause too tall a parameter that must be tightly controlled die to die, QWFETs employ high-mobility materials as a a gate, which can affect the current carrying ability of within wafer, and wafer to wafer for consistent replacement for silicon in the transistor channel. III-V the word line. Post-polish gate height must therefore transistor performance. Hence, the post-CMP remaining group materials are being considered for n-type channel be stringently controlled within a range less than 50Å, film thickness (stopping within-film) and uniformity field effect transistors (nFET) due to their exceptionally both within wafer and wafer to wafer.[3] control is paramount and real-time profile control high electron mobility and germanium is being technology can be an enabler. considered for p-type channel field effect transistors In-situ endpoint technology with broadband white light (pFET) due to its high hole mobility relative to silicon.[15] can offer the necessary control. The polysilicon film As in the case of the gate-last HKMG application, a CMP is expected to be an enabling technology in the has a high refractive index and high reflected signal novel in-pad sensor measures the eddy-current signal, heterogeneous integration of these new materials onto intensity. The broadband light spectrum collected which is proportional to the amount of metal remaining. silicon substrates. from in-situ metrology can provide fine resolution to This capability has been developed recently for accurately stop within the film at the targeted thickness. tungsten[11] and provides a high degree of resolution. Figure 5 2 The combination of endpoint metrology with multi-zone The DRAM industry is researching a transition to 4F nMOS pMOS Figure 5. Contact CMP for polishing pressure can yield a tight within-wafer range cell size, which will employ a buried bit-line architecture local interconnects polishes W [12] W in real time. Using pads and slurries that offer high (BBL) in addition to BWL. BBL creates an additional WW tungsten down to gate level, planarization efficiency achieves the desired within-die application for tungsten CMP with the same set of setting gate height. thickness control. challenges as those noted above. GATE CMP FOR BURIED WORD CONTACT CMP FOR LOCAL INTERCONNECTS LINE DRAM MEMORY In 2009, Intel announced their second-generation Recently, the DRAM industry has begun to migrate contacts with local interconnect technology for their Source: Reference 13. to buried word line (BWL) transistors to gain the 32nm node microprocessor.[13] In this device, the advantages of reduced parasitic capacitance (in both tungsten contacts are polished down to the transistor IMEC (Interuniversity Microelectronics Centre) is bit line and word line directions), smaller die size, and gate level, determining the gate height (Figure 5). presently developing a possible pFET flow for integration [6] low-power operation.[10] CMP is an enabling technology These trench-design contacts have lower resistance. with a CMP process. In pFET fabrication, the active in planarization of the metal gate film prior to the Similar to the gate-last HKMG application, this silicon areas formed by the STI process are recess recess etch process in BWL transistor fabrication.[5] application is a damascene process in which tungsten etched to enable epitaxial growth of germanium in its and the barrier metals are polished back to endpoint on place (the replacement channel), as shown in Figure 6. Tungsten or titanium nitride (TiN) films are the leading oxide (Figure 5). Tight control of thickness and uniformity candidates for the gate. They present an uneven surface Figure 6 variation are paramount to the manufacturability of this topography following the gap-fill process into the silicon Figure 6. A CMP process is application. As in the BWL application, real-time profile SiO2 trenches. Forming a flat reference plane with CMP is being developed to integrate control can enable the required precision of thickness Si critical to enable a precisely controlled etch process and uniformity control. germanium channels into

(Figure 4). This process has a direct impact on the final SiO2 silicon. FUTURE CMP APPLICATIONS IN height of the buried metal gate inside the trenches, Si HIGH-MOBILITY CHANNEL MATERIALS Research is actively being pursued in quantum well field SiO2 Ge effect transistors (QWFET), which are seen as promising Si candidates for next-generation transistors.[14] These Poly Poly transistors can enable high-speed performance at very SiO2 Ge STI STI STI Si Si Si low supply voltages, offering promise of a new era of Si ultra-low-power computing. Source: Reference 6.

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 16 Expanding CMP Applications

The overgrowth of germanium outside the trench must [5] Chipworks Report, “Samsung K4B2G0846D-HCH9 be removed by CMP to maintain a flat reference plane 32nm 2Gbit DDR3 SDRAM,” Jan. 2011. ENABLING SPIN-TRANSFER and define the pattern. A similar scheme is conceivable [6] P. Ong, “CMP of Ge for High-Mobility Channels,” for III-V materials grown in the nFET regions. International Conference on Planarization/CMP Requirements for this CMP application include chemistry Technology (ICPT), Nov. 14-17, 2010. TORQUE MAGNETIC development for polish, selective stop-on-oxide slurry [7] “TSMC Adds High-κ Metal Gate Low-Power Process behavior, cleaning chemistry post-polish, accurate to 28nm Road Map,” TSMC, retrieved 08/24/2009. MEMORY endpoint capability to prevent over- and under-polishing, [8] http://www.eetimes.com/electronics-news/4212271/ and extremely low defectivity. The application is at IBM--fab-club--switches-high-k-camps. for the 2x nm Node and Beyond the transistor gate stack level, requiring tight process control as emphasized above, which will be enabled [9] J. Diao, “ILD0 CMP: Technology Enabler for High-κ by in-situ platen endpoint technology and multi-zone Metal Gate in High Performance Logic Devices,” polishing technology. Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI, pp. 247-250, July 11-13, CONCLUSION 2010. CMP now plays a pivotal role in sustaining Moore’s [10] T. Schloesser, “6F2 Buried Word Line DRAM Cell for Law. CMP applications enable advanced transistor 40nm and Beyond,” Electron Devices Meeting, IEEE fabrication with HKMG, FinFET, advanced contacts for International, pp. 1-4, Dec. 15-17, 2008. local interconnect, and high-mobility channel materials [11] in advanced logic, and BWL structures in advanced Applied Materials Reflexion GT Product Launch Technical Briefing: http://www.appliedmaterials.com/ DRAM. In transistor fabrication, CMP must now meet Satisfying evolving functionality and form factor desires sites/default/files/ReflexionGTW-tech-briefing_0.pdf. specifications for thickness and uniformity that are of the burgeoning mobile consumer devices market will notably stricter than have previously been applied to [12] H. Chung, “Novel 4F2 DRAM Cell with Vertical Pillar place challenging demands on the integrated circuits that such applications. Process control technologies that Transistor (VPT),” Solid-State Device Research enable them, including demands for memory that performs offer real-time monitoring and control at the platen Conference (ESSDERC), 2011 Proceedings of the faster, has larger capacity, and uses less power. These level will therefore play a much more central role in the European, pp. 211-214, Sept. 12-16, 2011. demands are stimulating pursuit of an “ultimate solution” to replace current Flash and random access memory (RAM). coming years than ever before. [13] P. Packan, et al., “High Performance 32nm Logic Technology Featuring 2nd Generation High-κ + Among emerging technologies, spin-transfer torque (STT) REFERENCES Metal Gate Transistors,” Electron Devices Meeting, magneto-resistive RAM shows great promise. Recent [1]  K. Mistry, “A 45nm Logic Technology with High-κ IEEE International, slide 24, Dec. 7-9, 2009, advances in processes throughout the fabrication sequence + Metal Gate Transistors, Strained Silicon, 9 Cu http://download.intel.com/technology/architecture- can meet the stringent requirements imposed by the new Interconnect Layers, 193nm Dry Patterning, and silicon/32nm/2009_32nm_Logic_Presentation.pdf. materials and architecture in this new technology and can 100% Pb-free Packaging,” IEDM Technical Digest, help make production-scale implementation viable. [14] R. Chau, “III-V on Silicon for Future High Speed and pp. 247–250, 2007. Ultra-Low-Power Digital Applications: Challenges For 40 years, integrated circuit feature geometries have [2] J.M. Steigerwald, “Chemical Mechanical Polish: The and Opportunities,” Proceedings CS-MANTECH been steadily shrinking, consistent with the prediction Enabling Technology,” International Electron Devices Dig., p. 1-4, 2008. known as Moore’s Law. This trend has driven the evolution of every aspect of semiconductor technology Meeting, IEEE International, pp. 1-4, Dec. 15-17, 2008. [15] S.M. Sze, “High-Speed Semiconductor Devices,” in pursuit of faster and more sophisticated performance, [3] “Intel Reinvents Transistors Using New 3-D Wiley, New York, 1990. greater storage capacity and endurance, lower power, Structure,” retrieved 5/4/2011, AUTHORS and less cost. In memory technology, volatile dynamic http://newsroom.intel.com/community/intel_ Balaji Chandrasekaran is a marketing programs manager random access memory (DRAM) and non-volatile newsroom/blog/2011/05/04/intel-reinvents- in the Silicon Systems Group at Applied Materials. He complementary metal-oxide semiconductor (CMOS) transistors-using-new-3-d-structure. holds his M.S. in materials science and engineering Flash memory devices have successfully scaled over from Northwestern University and an MBA from the [4] Y. Moon, “Chemical Mechanical Polishing for Front- multiple technology nodes, with Flash proliferating University of California at Berkeley. End-of-Line Integration in 22nm Technology and throughout consumer and commercial electronics, such Beyond,” International Conference on Planarization/ ARTICLE CONTACT as cell phones, digital cameras, solid-state devices, CMP Technology (ICPT), pp. 183-189, Nov. 2009. [email protected] wireless communications, and medical products.

17 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. [5] Chipworks Report, “Samsung K4B2G0846D-HCH9 32nm 2Gbit DDR3 SDRAM,” Jan. 2011. ENABLING SPIN-TRANSFER [6] P. Ong, “CMP of Ge for High-Mobility Channels,” International Conference on Planarization/CMP Technology (ICPT), Nov. 14-17, 2010. TORQUE MAGNETIC [7] “TSMC Adds High-κ Metal Gate Low-Power Process to 28nm Road Map,” TSMC, retrieved 08/24/2009. MEMORY [8] http://www.eetimes.com/electronics-news/4212271/ IBM--fab-club--switches-high-k-camps. for the 2x nm Node and Beyond [9] J. Diao, “ILD0 CMP: Technology Enabler for High-κ Metal Gate in High Performance Logic Devices,” Flash memory comes in two forms: NOR and NAND. KEYWORDS Advanced Semiconductor Manufacturing Conference The former can be likened to a computer’s memory, Magneto-Resistive RAM (ASMC), 2010 IEEE/SEMI, pp. 247-250, July 11-13, while the latter is similar to a hard disk. In response to STT-MRAM 2010. high demand for increased capacity in recent years, Emerging Memory [10] T. Schloesser, “6F2 Buried Word Line DRAM Cell for NAND has scaled more aggressively as it is a simpler Magnetic Films 40nm and Beyond,” Electron Devices Meeting, IEEE structure. However, in spite of such adaptations as International, pp. 1-4, Dec. 15-17, 2008. multi-level cells and three-dimensional (3D) transistor stacking, leading-edge Flash technology is facing [11] Applied Materials Reflexion GT Product Launch mounting challenges of limited endurance, high power Technical Briefing: http://www.appliedmaterials.com/ Satisfying evolving functionality and form factor desires consumption in write mode, and slow write speed. sites/default/files/ReflexionGTW-tech-briefing_0.pdf. of the burgeoning mobile consumer devices market will DRAM also faces speed and power disadvantages and, [12] 2 place challenging demands on the integrated circuits that H. Chung, “Novel 4F DRAM Cell with Vertical Pillar further, is incompatible with embedded applications enable them, including demands for memory that performs Transistor (VPT),” Solid-State Device Research that help reduce power usage and speed response time. Conference (ESSDERC), 2011 Proceedings of the faster, has larger capacity, and uses less power. These Static RAM (SRAM) fares even worse, with power European, pp. 211-214, Sept. 12-16, 2011. demands are stimulating pursuit of an “ultimate solution” usage and leakage issues.[1] In addition, signal-noise to replace current Flash and random access memory (RAM). [13] P. Packan, et al., “High Performance 32nm Logic ratio, alpha-immunity, variability, and size will challenge Among emerging technologies, spin-transfer torque (STT) Technology Featuring 2nd Generation High-κ + SRAM as it scales further. Power consumption is one magneto-resistive RAM shows great promise. Recent Metal Gate Transistors,” Electron Devices Meeting, of the top issues affecting mobile and data center advances in processes throughout the fabrication sequence IEEE International, slide 24, Dec. 7-9, 2009, applications while memory performance is becoming can meet the stringent requirements imposed by the new http://download.intel.com/technology/architecture- the key bottleneck limiting system performance as silicon/32nm/2009_32nm_Logic_Presentation.pdf. materials and architecture in this new technology and can applications become more data-centric and less help make production-scale implementation viable. [14] R. Chau, “III-V on Silicon for Future High Speed and computational. Ultra-Low-Power Digital Applications: Challenges For 40 years, integrated circuit feature geometries have EMERGING MEMORY TECHNOLOGY and Opportunities,” Proceedings CS-MANTECH been steadily shrinking, consistent with the prediction Dig., p. 1-4, 2008. known as Moore’s Law. This trend has driven the During the past decade, several new and more scalable evolution of every aspect of semiconductor technology RAM technologies (e.g., ferroelectric, magnetic, phase- [15] S.M. Sze, “High-Speed Semiconductor Devices,” change) have been under development as potential Wiley, New York, 1990. in pursuit of faster and more sophisticated performance, greater storage capacity and endurance, lower power, successors to Flash, DRAM, and SRAM. Of these, a AUTHORS and less cost. In memory technology, volatile dynamic form of magneto-resistive RAM (MRAM) known as Balaji Chandrasekaran is a marketing programs manager random access memory (DRAM) and non-volatile spin-transfer torque, or STT-MRAM, appears to have in the Silicon Systems Group at Applied Materials. He complementary metal-oxide semiconductor (CMOS) fewer limitations than the others, offering non-volatility, holds his M.S. in materials science and engineering Flash memory devices have successfully scaled over extended scalability, excellent endurance (exceeding from Northwestern University and an MBA from the 15 multiple technology nodes, with Flash proliferating 10 cycles) at lower power, and fast read and write University of California at Berkeley. throughout consumer and commercial electronics, such speeds.[2-5] Further, its physical size gives it a major ARTICLE CONTACT as cell phones, digital cameras, solid-state devices, advantage over current SRAM. Figure 1 is a diagrammatic [email protected] wireless communications, and medical products. representation of an STT-MRAM cell.

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 18 Emerging STT-MRAM

Figure 1 STT-MRAM employs electron spin associated with To be viable, STT-MRAM must clearly demonstrate that magnetism. An electric current from an underlying CMOS it can migrate to smaller and denser memory size with Figure 1. STT-MRAM cell 6F2 transistor is polarized by aligning the spin direction of lower power consumption as the underlying CMOS structure is simpler and electrons passing through the magnetic tunnel junction logic technology scales down. DRAM and SRAM are on more compact than a Bit Line (MTJ) at the core of the bit cell (Figure 2). The spin track to scale to 20nm, with well-known device function conventional MRAM cell. MTJ transforms the state of the MTJ from anti-parallel (1) and cost parity. For STT-MRAM to be competitive with to parallel (0) and vice versa, with current flowing in these well-established technologies, it must demonstrate opposite directions. The MTJ stack consists of a top functional scalability to 10nm. Research by the hard electrode, a (ferromagnetic) free layer where information disk drive industry and others[5] has confirmed that a Gate is stored, a tunneling insulator layer, fixed ferromagnetic 10nm-sized magnetic material can perform well as a reference layers, and a bottom electrode. Current running Source Drain memory storage element from the perspectives of through the reference layer polarizes its electrons, signal to noise and reliability. Incorporating this Silicon Substrate which then affect those of the free layer, leading to the technology into next-generation memory will, however, Source: Reference 1. parallel and anti-parallel configurations. Writing occurs require pervasive innovation in integrated circuit when the spin-polarized current changes the magnetic fabrication, including implementing perpendicular Figure 2 orientation of the data storage layer; the resistance STT-MRAM, which has been proven to operate at lower difference of this layer is used for reading. Applying the Figure 2. Current running Current “0” current density.[7] spin-polarized current vertically through the MTJ through the fixed layer of the Bit Line overcomes a major drawback of conventional MRAM, First presented by Toshiba in 2007,[8] perpendicular STT MTJ polarizes the electrons, MTJ which is the increase in switching current as the MTJs offer significant advantages over in-plane MTJs. in turn affecting those of the [6] technology scales down. Particularly important are the effective thermal energy free layer to produce parallel barrier and thermal stability created by perpendicular and anti-parallel configurations. Selection Transistor As the CMOS transistor has evolved from a planar Word Line structure to a 3D one, the drivability of a transistor in anisotropy and much lower switching current that Source Line small geometry has exceeded 1mA/µm in a logic circuit, enables smaller, circular cells that are easier to fabricate where µm represents the gate width of 1µm. These than elongated ones. Moreover, dipole field interaction “1” findings have been widely reported in the literature, can be reduced between adjacent cells in high-density Bit Line especially for high-κ/metal gate CMOS. Figure 3 shows layouts.[9] Free Layer the write current as a function of STT-RAM cell area, Barrier FABRICATION CHALLENGES Fixed Layer from which one can project that if current density of STT-MRAM fabrication poses challenges ranging from 1.4MA/cm2 is scaled down to approximately 20nm, material complexity of the structure to process 6.4µA will be required for programming a 20nm by Word Line integration considerations. As shown in Figure 4, 20nm STT-MRAM cell. However, as memory arrays many ultra-thin layers of materials with widely varying Source Line operate with random individual access and most of the characteristics are present in the device. Interface Source: Reference 2. inactive transistors are in the off state during the access engineering will be crucial to successfully combining stage, the transistor off current is also very important Figure 3 for array operation. For a lower off current transistor, these materials by achieving a satisfactory balance the on current will be correspondingly reduced. Hence, between surface roughness and good magnetic Figure 3. STT-MRAM write 500 [10] DMTJ reducing STT-MRAM cell programming current density properties. current usage demonstrates J ~1.4MA/cm2 c0 further by a factor of 2-5 will increase device margin the technology’s scalability. 400 Figure 4 and functionality, while lowering overall cost. Bit Line Wire W, Cu (50nm) 300 Because it uses a current running through the cell, the Electrode/Capping Layer ent (µ A) Ta (30nm) Free Layer AlO/SiN (50nm) required writing current through the smaller MTJ Tunneling Layer 200 CoFeB (1-3nm) ite Curr decreases (Figure 3), in turn reducing power consumption MgO (~1nm) Fixed Layer

Wr CoFeB (5nm) as the device becomes smaller. In addition, STT-MRAM Ru (~1nm) Coupling Layer 100 CoFeB (5nm) Spacer Layer uses only 1.2V internally and can therefore operate on IrMn (10nm) Ferromagnetic Layer a single 1.5V battery as opposed to DRAM and Flash NiFe (6nm) Antiferromagnetic Layer 0 Ta (10nm) 0.010.020.03 that need charge pumps to satisfy their higher voltage Bu er Layer Device Area (µm2) W SiO Contact Source: Reference 1. requirements (e.g., Flash requires 10-12V for writing). Isolation

19 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Emerging STT-MRAM

STT-MRAM employs electron spin associated with To be viable, STT-MRAM must clearly demonstrate that Deposition and etching processes will have to achieve magnetism. An electric current from an underlying CMOS it can migrate to smaller and denser memory size with virtually atomic-scale process control to ensure transistor is polarized by aligning the spin direction of lower power consumption as the underlying CMOS extreme uniformity and negligible surface roughness. electrons passing through the magnetic tunnel junction logic technology scales down. DRAM and SRAM are on For example, tunneling barrier uniformity is crucial for (MTJ) at the core of the bit cell (Figure 2). The spin track to scale to 20nm, with well-known device function high tunnel magneto-resistance (MR) and depends transforms the state of the MTJ from anti-parallel (1) and cost parity. For STT-MRAM to be competitive with primarily on the roughness of the bottom electrode.[11] to parallel (0) and vice versa, with current flowing in these well-established technologies, it must demonstrate Given the extreme thinness of the layers, etching must opposite directions. The MTJ stack consists of a top functional scalability to 10nm. Research by the hard employ ultra-clean processes to avoid re-deposition of electrode, a (ferromagnetic) free layer where information disk drive industry and others[5] has confirmed that a by-products or residue as this could lead to shorting. is stored, a tunneling insulator layer, fixed ferromagnetic 10nm-sized magnetic material can perform well as a Cell profile control must be extremely exact to achieve reference layers, and a bottom electrode. Current running memory storage element from the perspectives of consistency across large arrays. through the reference layer polarizes its electrons, signal to noise and reliability. Incorporating this which then affect those of the free layer, leading to the Several characteristics of the magnetic films in the technology into next-generation memory will, however, parallel and anti-parallel configurations. Writing occurs stack pose further challenges. They are thin and require pervasive innovation in integrated circuit when the spin-polarized current changes the magnetic susceptible to corrosion; hence effective passivation fabrication, including implementing perpendicular orientation of the data storage layer; the resistance is of great importance to protect them from penetra- STT-MRAM, which has been proven to operate at lower difference of this layer is used for reading. Applying the tion or diffusion of such process chemicals as oxygen, current density.[7] spin-polarized current vertically through the MTJ chlorine, and bromine, which can alter the structure overcomes a major drawback of conventional MRAM, First presented by Toshiba in 2007,[8] perpendicular STT and properties of the films to reduce the MR effect. The which is the increase in switching current as the MTJs offer significant advantages over in-plane MTJs. magnetic moments of magnetic films depend strongly [6] technology scales down. Particularly important are the effective thermal energy on the domains (grains) and grain boundaries of these As the CMOS transistor has evolved from a planar barrier and thermal stability created by perpendicular materials, as these factors affect programing current. structure to a 3D one, the drivability of a transistor in anisotropy and much lower switching current that In addition, magnetic switching (or coupling) between small geometry has exceeded 1mA/µm in a logic circuit, enables smaller, circular cells that are easier to fabricate the fixed layer and the free layer through the tunneling where µm represents the gate width of 1µm. These than elongated ones. Moreover, dipole field interaction oxide separating them is greatly reduced by the bound- findings have been widely reported in the literature, can be reduced between adjacent cells in high-density aries of the grains. Signal-to-noise ratio also degrades especially for high-κ/metal gate CMOS. Figure 3 shows layouts.[9] as grain boundary increases or the number of grains in the write current as a function of STT-RAM cell area, a given area decreases below a certain threshold. As FABRICATION CHALLENGES from which one can project that if current density of STT-MRAM cell size scales down, noise levels or signal STT-MRAM fabrication poses challenges ranging from 1.4MA/cm2 is scaled down to approximately 20nm, inconsistency across the array increases, with these material complexity of the structure to process 6.4µA will be required for programming a 20nm by variations becoming relatively larger. integration considerations. As shown in Figure 4, 20nm STT-MRAM cell. However, as memory arrays many ultra-thin layers of materials with widely varying From the integration standpoint, STT-MRAM processes operate with random individual access and most of the characteristics are present in the device. Interface (typically <350˚C) have the advantage over other inactive transistors are in the off state during the access engineering will be crucial to successfully combining embedded memory technologies employing relatively stage, the transistor off current is also very important for array operation. For a lower off current transistor, these materials by achieving a satisfactory balance low temperatures and hence are compatible with CMOS [12] the on current will be correspondingly reduced. Hence, between surface roughness and good magnetic back-end-of-line (BEOL) thermal budgets. However, [10] reducing STT-MRAM cell programming current density properties. a holistic approach should be adopted, taking into further by a factor of 2-5 will increase device margin Figure 4 and functionality, while lowering overall cost. Bit Line Wire W, Cu (50nm) Figure 4. SST-RAM Because it uses a current running through the cell, the Electrode/Capping Layer comprises a complicated Ta (30nm) Free Layer required writing current through the smaller MTJ AlO/SiN (50nm) CoFeB (1-3nm) Tunneling Layer materials system. decreases (Figure 3), in turn reducing power consumption MgO (~1nm) Fixed Layer CoFeB (5nm) as the device becomes smaller. In addition, STT-MRAM Ru (~1nm) Coupling Layer CoFeB (5nm) Spacer Layer uses only 1.2V internally and can therefore operate on IrMn (10nm) Ferromagnetic Layer a single 1.5V battery as opposed to DRAM and Flash NiFe (6nm) Antiferromagnetic Layer Ta (10nm) that need charge pumps to satisfy their higher voltage Bu er Layer W SiO Contact requirements (e.g., Flash requires 10-12V for writing). Isolation

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account the total thermal budget allocated to post-MTJ Ultra-thin deposition of ultra-pure metals as well as density to ensure strong performance after chemical processing, to protect against adverse effects. For metal oxides, metal nitrides, binary alloys, and magnetic mechanical planarization (CMP), reactive ion etch, and example, thermal fluctuation of magnetization can be materials has been made possible by RF sputtering, an wet cleans. And, lastly, they must be extremely pure caused by subsequent high-temperature processing; adaptation of conventional physical vapor deposition (PVD) to ensure that no fixed charges are created, which are exposing the wafer to physical stresses can also induce that enables virtually damage-free processing. RFPVD detrimental to device reliability. The new flowable CVD altered magnetic properties as a result of changes in employs lower power levels than conventional PVD, film is comparable in these respects to high-quality, grain boundaries and interface properties. which reduces the risk of plasma damage while enabling industry-standard high-density plasma CVD silicon exacting control of thickness, stoichiometry, and dioxide. While beyond the scope of this article, broader deposition rate (on the order of 0.1-2Å/sec) for layers challenges involve achieving low current density and High-temperature etching (150-250˚C), developed less than 10Å thick. Low-temperature deposition also high reliability in array operation. Besides increasing and proven for high-κ/metal gate applications, is also offers the advantage of producing smoother surface power consumption for large arrays, high current being applied to such materials as magnesium oxide, morphology. Rotating the wafer during deposition density exacerbates electrical stress and reduces ruthenium, cobalt-iron-boron, palladium, and platinum- transistor lifetime. Another consideration will be can improve within-wafer uniformity to the required manganese used in STT-MRAM structures. Non-halide- provision of magnetic shielding during assembly and 0.5 percent range. Surface roughness can be further based chemistries generally used in high-temperature testing to protect pre-magnetized cells from external reduced by rotating the wafer while exposing it to etching do not adversely affect magnetic films and magnetic fields. a mild argon sputter. the tunneling dielectric as do the chlorine and fluorine With its ability to create highly uniform and chemistries typical of lower-temperature etch regimes. APPLICABLE PROCESS TECHNOLOGIES conformal films with atomic level control, atomic layer These high-temperature chemistries combined with Fortunately, recent advances in unit and integration deposition (ALD) has become an important thin films precise plasma energy control throughout the entire processes, as well as ongoing development work, deposition process. This method uses pulses of gas to stack etching sequence can create a smooth-walled and address many of the challenges cited above. deposit material one atomic layer at a time. ALD can residue-free STT-MRAM cell. Plasma pulsing is also Figure 5 be enhanced with the application of plasma energy being studied as a means of refining this performance. Figure 5. A prototype that promotes attraction of the required species to the Low-temperature annealing processes are also required. STT-MRAM chip exhibits wafer surface and accelerates the reaction (deposition Minimizing the thermal budget while sustaining the re-entrant profile for cycle) while also improving film uniformity and quality. minimum reaction temperatures for quality interfaces which flowable CVD film In STT-MRAM, plasma-enhanced ALD (PE-ALD) offers and proper material crystalline structures, in particular, offers void-free, complete a good low-temperature approach for depositing thin necessitates low-temperature (<400˚C) processes bottom-up gap fill. spacer and passivation layers without adverse reactions with fast and accurate control. Rapid thermal processing to underlying metals. In-situ annealing of the ALD film 20nm technology now accommodates processes at to achieve proper crystalline structure complements temperatures as low as 150˚C, with transmission the uniformity of the deposition process in achieving pyrometry enabling closed-loop monitoring of wafer the uniformity requirement for thin (<1nm) films in the temperatures as low as 75˚C and multi-point STT-RAM cell stack. measurement capability helping to improve die-to-die As features become more densely packed, the gaps and wafer-to-wafer repeatability. between electrical components become narrower, CMP is becoming a more frequent and challenging aspect ratios greater, and re-entrant profiles more process in advanced integrations, such as FinFETs and common (Figure 5). This continuous challenge for STT-MRAM, where devices are directly exposed to the scaling dielectric gap fill from each node to the next has CMP process. As features become smaller and more driven innovation in chemical vapor deposition (CVD) fragile, preservation of device topography through to produce a fluid-like, profile-insensitive film that can precision planarization end-pointing is crucial to be deposited at low temperatures, consistent with successful device performance. Addressing this reduced thermal budgets at advanced nodes. Beyond requirement, in-situ, high-resolution sensors now enable achieving complete gap fill, dielectric films must satisfy closed-loop, real-time thickness control during Source: Reference 1. additional requirements to be integrated into a device. planarization by means of incremental changes to They must have a high breakdown voltage to ensure polishing conditions in multiple zones of the polishing electrical robustness. They must also possess good film head.

21 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Emerging STT-MRAM

Ultra-thin deposition of ultra-pure metals as well as density to ensure strong performance after chemical IMPLEMENTING FABRICATION metal oxides, metal nitrides, binary alloys, and magnetic mechanical planarization (CMP), reactive ion etch, and Depositing the SST-MRAM film stack and creating materials has been made possible by RF sputtering, an wet cleans. And, lastly, they must be extremely pure the memory cell structure can be readily adapted to adaptation of conventional physical vapor deposition (PVD) to ensure that no fixed charges are created, which are process clustering. Using Figure 4 as a reference, it that enables virtually damage-free processing. RFPVD detrimental to device reliability. The new flowable CVD would be possible to integrate on one platform the employs lower power levels than conventional PVD, film is comparable in these respects to high-quality, complete deposition sequence for the entire stack with which reduces the risk of plasma damage while enabling industry-standard high-density plasma CVD silicon a pre-treatment process for reducing surface roughness exacting control of thickness, stoichiometry, and dioxide. on the incoming wafer, as well as between successive deposition rate (on the order of 0.1-2Å/sec) for layers depositions. In addition, process monitoring, such High-temperature etching (150-250˚C), developed less than 10Å thick. Low-temperature deposition also as optical spectroscopy and wafer surface particle and proven for high-κ/metal gate applications, is also offers the advantage of producing smoother surface inspection, can be integrated into the system to being applied to such materials as magnesium oxide, morphology. Rotating the wafer during deposition enhance manufacturing quality. ruthenium, cobalt-iron-boron, palladium, and platinum- can improve within-wafer uniformity to the required manganese used in STT-MRAM structures. Non-halide- As for cell formation, similar clustering could combine 0.5 percent range. Surface roughness can be further based chemistries generally used in high-temperature low-temperature spacer/passivation PE-ALD with reduced by rotating the wafer while exposing it to etching do not adversely affect magnetic films and high-temperature etching. Multiple etch technologies, a mild argon sputter. the tunneling dielectric as do the chlorine and fluorine as described above, can be integrated onto the same With its ability to create highly uniform and chemistries typical of lower-temperature etch regimes. platform for etching complicated stacks with accurate conformal films with atomic level control, atomic layer These high-temperature chemistries combined with control and high productivity. Here also, integration of deposition (ALD) has become an important thin films precise plasma energy control throughout the entire monitoring technologies optimizes process performance. deposition process. This method uses pulses of gas to stack etching sequence can create a smooth-walled and Besides end-pointing of etch processes, in-situ deposit material one atomic layer at a time. ALD can residue-free STT-MRAM cell. Plasma pulsing is also monitoring of critical dimensions and devices after be enhanced with the application of plasma energy being studied as a means of refining this performance. etching and passivation layer deposition can be installed directly on the chambers. that promotes attraction of the required species to the Low-temperature annealing processes are also required. wafer surface and accelerates the reaction (deposition Minimizing the thermal budget while sustaining CONCLUSION cycle) while also improving film uniformity and quality. minimum reaction temperatures for quality interfaces DRAM and Flash are facing serious limitations beyond In STT-MRAM, plasma-enhanced ALD (PE-ALD) offers and proper material crystalline structures, in particular, the 20nm technology node, prompting new approaches a good low-temperature approach for depositing thin necessitates low-temperature (<400˚C) processes to memory design, such as STT-MRAM. While the spacer and passivation layers without adverse reactions with fast and accurate control. Rapid thermal processing material complexity and 3D architecture of this new to underlying metals. In-situ annealing of the ALD film technology now accommodates processes at structure pose challenges, many recent advances in to achieve proper crystalline structure complements temperatures as low as 150˚C, with transmission deposition, etch, and related integration processes offer the uniformity of the deposition process in achieving pyrometry enabling closed-loop monitoring of wafer device manufacturers the means by which to bring this the uniformity requirement for thin (<1nm) films in the temperatures as low as 75˚C and multi-point technology to production using proven cluster-tool STT-RAM cell stack. measurement capability helping to improve die-to-die platforms. As features become more densely packed, the gaps and wafer-to-wafer repeatability. between electrical components become narrower, CMP is becoming a more frequent and challenging aspect ratios greater, and re-entrant profiles more process in advanced integrations, such as FinFETs and common (Figure 5). This continuous challenge for STT-MRAM, where devices are directly exposed to the scaling dielectric gap fill from each node to the next has CMP process. As features become smaller and more driven innovation in chemical vapor deposition (CVD) fragile, preservation of device topography through to produce a fluid-like, profile-insensitive film that can precision planarization end-pointing is crucial to be deposited at low temperatures, consistent with successful device performance. Addressing this reduced thermal budgets at advanced nodes. Beyond requirement, in-situ, high-resolution sensors now enable achieving complete gap fill, dielectric films must satisfy closed-loop, real-time thickness control during additional requirements to be integrated into a device. planarization by means of incremental changes to They must have a high breakdown voltage to ensure polishing conditions in multiple zones of the polishing electrical robustness. They must also possess good film head.

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REFERENCES [9] Y. Huai, “Spin-Transfer Torque MRAM (STT-MRAM): [1] A. Driskill-Smith, “Latest Advances and Future Challenges and Prospects,” AAPPS Bulletin, Vol. 18, THROUGH-SILICON Prospects of STT-RAM,” Non-Volatile Memories No. 6, pp. 33-40, Dec. 2008. Workshop, University of California, San Diego, [10] C.S. Kim, et al., “Thickness and Temperature Effects April 11–13, 2010. on Magnetic Properties and Roughness of L1 -ordered VIA TECHNOLOGY 0 [2] F. Tabrizi, “The Future of Scalable STT-RAM as a FePt Films,” IEEE Transactions on Magnetics, Vol. 46, Enroute to Manufacturing Universal Embedded Memory,” retrieved October 7, No. 6, pp. 2282-2285, 2010. 2011, [11] M. Yoshikawa, et al., “Tunnel Magnetoresistance http://www.eetimes.com/design/embedded/ Over 100% in MgO-Based Magnetic Tunnel Junction 4026000/The-future-of-scalable-STT-RAM-as-a- Films with Perpendicular Magnetic L1 -FePt universal-embedded-memory. 0 Electrodes,” IEEE Transactions on Magnetics, Vol. 44, [3] X. Dong, et al., “Circuit and Microarchitecture No. 11, pp. 2573–2576, 2008. Evaluation of 3D Stacking Magnetic RAM (MRAM) [12] K. Lee and S.H. Kang, “Development of Embedded as a Universal Memory Replacement,” Proceedings STT-MRAM for Mobile System-on-Chips,” of the 45th Annual Design Automation Conference, IEEE Transactions on Magnetics, Vol. 47, No. 1, Anaheim, California, June 2008. pp. 131-136, January 2011. [4] X. Dong, et al., “Leveraging 3D PCRAM Technologies [13] F. Tang, et al., “Atomic Layer Deposition of MgO to Reduce Checkpoint Overhead for Future Exascale for High-κ Capping Layers,” 11th International Systems,” Proceedings of the Conference on High Conference on Atomic Layer Deposition, Cambridge, Performance and Analysis, Portland, Oregon, MA, June 26-29, 2011. November 2009. AUTHORS [5] C.J. Lin, et al., “45nm Low-Power CMOS Er-Xuan Ping is a managing director in the Silicon Logic-Compatible Embedded STT-MRAM Utilizing Systems Group at Applied Materials. He holds his Ph.D. a Reverse-Connection 1T/1MTJ Cell,” International in electrical engineering from Iowa State University. Electron Devices Meeting, IEEE International, pp. 279-282, Dec. 2009. Gill Lee is a principal member of technical staff in the Silicon Systems Group at Applied Materials. He earned [6] S.A. Wolf, et al., “The Promise of Nanomagnetics his M.S. in materials science from Pohang University of and Spintronics for Future Logic and Universal Science and Technology, Korea. In recent years, semiconductor devices have been under Memory,” Proceedings of the IEEE, Vol. 98, No. 12, intensifying pressure to deliver more functionality at lower ARTICLE CONTACT pp. 2155-2168, 2010. power and greater speed in smaller dimensions as consumer [email protected] [7] D.C. Worledge, et al., “Switching Distributions electronics have become increasingly complex and more and Write Reliability of Perpendicular Spin Torque compact. Through-silicon via (TSV) technology has been MRAM,” International Electron Devices Meeting, under development to satisfy these demands by offering IEEE International, pp. 296-299, Dec. 2010. designers more freedom, and improved power and form factor efficiencies through three-dimensional (3D) [8] M. Nakayama, et al., “Spin Transfer Switching in interconnect (IC) stacking. Characterized and optimized TbCoFe/CoFeB/MgO/ CoFeB/TbCoFe Magnetic TSV unit processes and integration schemes are now Tunnel Junctions with Perpendicular Magnetic demonstrating their readiness for manufacturing. Anisotropy,” Proceedings of the 52nd Annual Conference on Magnetism and Magnetic Materials, The basic principle behind 3D ICs using TSVs is that the Journal of Applied Physics, Vol. 103, Issue 7, vias replace off-chip, two-dimensional peripheral buses pp. A710-1-A710-3, 2008. that are millimeters in length with micron-scale vertical buses. The full potential of this advance is realized when chip designers implement new design architectures that use 3D IC with TSVs for routing power, ground, and signal

23 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. [9] Y. Huai, “Spin-Transfer Torque MRAM (STT-MRAM): Challenges and Prospects,” AAPPS Bulletin, Vol. 18, No. 6, pp. 33-40, Dec. 2008. THROUGH-SILICON

[10] C.S. Kim, et al., “Thickness and Temperature Effects on Magnetic Properties and Roughness of L1 -ordered VIA TECHNOLOGY 0 FePt Films,” IEEE Transactions on Magnetics, Vol. 46, Enroute to Manufacturing No. 6, pp. 2282-2285, 2010.

[11] M. Yoshikawa, et al., “Tunnel Magnetoresistance Over 100% in MgO-Based Magnetic Tunnel Junction lines. Micron-scale TSVs enable high-density inter-die KEYWORDS connectivity, leading to high-bandwidth operation. The Through-Silicon Via Films with Perpendicular Magnetic L10-FePt Electrodes,” IEEE Transactions on Magnetics, Vol. 44, first few TSV applications are in dynamic random access 3D Interconnect No. 11, pp. 2573–2576, 2008. memory (DRAM) memory stacks, logic-memory stacks, Via-Middle and field-programmable gate arrays (FPGAs)—shipment Via-Reveal [12] K. Lee and S.H. Kang, “Development of Embedded of the world’s first interposer-based highest capacity STT-MRAM for Mobile System-on-Chips,” FPGA was announced in September 2011.[1] In memory IEEE Transactions on Magnetics, Vol. 47, No. 1, devices, for example, flash memories show steady density pp. 131-136, January 2011. increases aligned with Moore’s Law,[2] enabled by double [13] F. Tang, et al., “Atomic Layer Deposition of MgO patterning of lithographic features. DRAM devices are for High-κ Capping Layers,” 11th International more challenging to scale than flash memories, and Conference on Atomic Layer Deposition, Cambridge, greater density is obtained not only by lithography MA, June 26-29, 2011. scaling, but by 3D stacking of memory die. This 3D AUTHORS approach satisfies both performance and form factor [3,4] Er-Xuan Ping is a managing director in the Silicon needs for future end products. Systems Group at Applied Materials. He holds his Ph.D. In microprocessors, the drive to continuously increase in electrical engineering from Iowa State University. frequency has been tempered by practical issues arising Gill Lee is a principal member of technical staff in the from the need to manage leakage, stand-by current, and Silicon Systems Group at Applied Materials. He earned power dissipation at the chip and system levels. The his M.S. in materials science from Pohang University of enhanced performance of computers with multi-core Science and Technology, Korea. In recent years, semiconductor devices have been under processors is often hobbled by memory latency and intensifying pressure to deliver more functionality at lower bandwidth.[5] 3D integration can dramatically improve ARTICLE CONTACT power and greater speed in smaller dimensions as consumer power loss and inductance by creating a denser, lower [email protected] electronics have become increasingly complex and more latency, higher bandwidth bus between memory and compact. Through-silicon via (TSV) technology has been processor. under development to satisfy these demands by offering In scaling device node from 45nm to 28nm to 20nm designers more freedom, and improved power and form to 14nm, not all functional blocks need to be scaled. factor efficiencies through three-dimensional (3D) Instead of scaling the entire chip, the portion that needs interconnect (IC) stacking. Characterized and optimized to be scaled can be manufactured as a separate chip, TSV unit processes and integration schemes are now leaving other functional blocks relatively untouched. demonstrating their readiness for manufacturing. These dis-integrated functional blocks can then span The basic principle behind 3D ICs using TSVs is that the across multiple smaller die interconnected with TSVs. vias replace off-chip, two-dimensional peripheral buses TSV SCHEMES that are millimeters in length with micron-scale vertical Currently, via-middle and via-last TSV schemes are buses. The full potential of this advance is realized when being widely adopted at logic/foundry and memory chip designers implement new design architectures that makers. The choice between the two is driven largely use 3D IC with TSVs for routing power, ground, and signal by device design considerations. In general, devices

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necessitating high TSV interconnection require smaller VIA-MIDDLE TSV Figures 2 and 3 illustrate performance of current TSV dimension. Such applications are better served In the via-middle flow, TSVs are created from the technologies for several of the steps in the process by the via-middle flow in which the TSVs are created device side of a full-thickness wafer during processing sequence. in a wafer fab immediately following transistor and right after contact formation. The via-middle scheme Early in TSV process development, post-ECD copper contact formation and before the formation of back- described in this article for 3D IC stacking is also used overburden could be 0.5-0.75 of the TSV diameter, end-of-line (BEOL) damascene interconnects. Typically, for TSVs in 2.5D interposer applications. i.e., several microns thick. Such added stress tended the vias are 5-10µm in diameter and 50-100µm deep, In the via-last process scheme, front-end-of-line device to cause excessive wafer bowing, which could induce with a nominal aspect ratio of 8-10:1. The International processing can proceed as usual. TSVs are created in the breakage or create difficulties in subsequent processing, Technology Roadmap for Semiconductors calls for vias especially for CMP. Thick copper overburden also back-end wafer line at a wafer fab or at an outsourced with a 2-3µm diameter, 20-50µm depth in a few years. increases the cost of copper CMP. More recent ECD assembly and test facility. Maintaining an aspect ratio less than 12:1 allows a wider exhibits enhanced bottom-up fill, a wide process window, Figure 1 shows the typical process steps involved in and more robust process window. The wafer temperature and overburden of less than 2µm on a 5µm via. This the via-middle, via-reveal, and via-last TSV flows. This is in the same range as that of BEOL films, typically process reduces the required thickness of the seed layer article presents an overview of the via-middle and 350-400˚C. Via-middle TSVs offer the most flexibility and lowers CMP costs. Careful selection of the CMP companion via-reveal processes. Via-last uses modified in layout, design, and via density. Provided post-TSV process and slurry is important to ensure clean copper processes on wafers temporarily bonded to carriers. processing planarity is good, interconnect wires from and barrier removal, freedom from corrosion of the Hence, the process temperature must not exceed 200˚C M1 through Mx may be permitted to go above them. copper in the via or the barrier metal on the sidewall, to preserve adhesion of temporary bonding materials. Table 1 details the processes in the via-middle flow. and absence of divots or attack in the oxide lining the Figure 1 inner circumference of the via. Typically between ECD and CMP steps, the copper is Figure 1. TSV process flows Via-Middle Via-Last for via-middle, via-reveal, annealed at approximately 400˚C in a forming gas (3% Part 1. Form Vias from Front Side Form Vias from Back Side and via-last schemes. in MOL or BEOL Part 2. Backside Via Reveal After Thinning

· TSV Via Etch, Strip · Edge Trim · Edge Trim and Clean · Temporary Bonding · Temporary Bonding · CVD Dielectric Liner · Grinding · Grinding · Barrier/Seed · CMP Si · CMP Si · ECD Cu Fill, Anneal · Dry Si Recess Etch · Low Temp Nitride/Oxide · CMP Cu/Barrier/Dielectric (expose Cu pillar) · Via Etch, Strip, Clean · Low Temp Nitride/Oxide · Low Temp Oxide Liner · CMP Oxide/Nitride · Oxide Bottom Open and Clean Carrier Carrier · Barrier/Seed · ECD Cu · CMP Cu/Barrier/Dielectric Table 1

Table 1. Process steps Process Step Purpose Key Requirements comprising the via-middle Resist Coat and Lithography Exposure Create pattern. Resist thickness, exposure quality. TSV scheme. Etch rate, profile/depth, selectivity (resist to Dielectric and silicon etch to dielectric and silicon), undercut, non-uniformity TSV Etch create vias. across wafer. Figure 3 All-in-one etch. Resist Strip and Wet Clean Clean vias. Post-etch residue removal. Barrier/Seed 25% Fill 50% Fill 75% Fill 100% Fill Step coverage, mechanical properties, leakage, Electrical isolation. breakdown voltage, and dielectric constant. Dielectric Oxide Liner Deposition Cu to bulk Si capacitance. Process Temperature ~400˚C. 2500Å to 1.5µm based on application. Copper diffusion barrier/seed Barrier/Seed Deposition Barrier properties and step coverage. for electroplating. Electrochemical Deposition (ECD) Conducting plug. Void-free fill, copper quality, and stability. Anneal Stabilize film, control protrusions. Copper material properties. Chemical Mechanical Planarization (CMP) Form copper plug. Flatness, topography. (a) (b)(c) Applied Materials internal data

25 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Manufacture-Ready TSV

VIA-MIDDLE TSV Figures 2 and 3 illustrate performance of current hydrogen) environment for 20-30 minutes to stabilize In the via-middle flow, TSVs are created from the technologies for several of the steps in the process its microstructure and film composition. All subsequent device side of a full-thickness wafer during processing sequence. processes, such as BEOL damascene processing and in a wafer fab immediately following transistor and final anneal, must be at or below this temperature to Early in TSV process development, post-ECD copper contact formation and before the formation of back- minimize protrusion and avoid the risk of dielectric overburden could be 0.5-0.75 of the TSV diameter, end-of-line (BEOL) damascene interconnects. Typically, cracking and inter-metal shorts. i.e., several microns thick. Such added stress tended the vias are 5-10µm in diameter and 50-100µm deep, to cause excessive wafer bowing, which could induce VIA-REVEAL TSV with a nominal aspect ratio of 8-10:1. The International breakage or create difficulties in subsequent processing, Vias created in the middle of line must be exposed Technology Roadmap for Semiconductors calls for vias especially for CMP. Thick copper overburden also from the backside in a process known as ‘via-reveal’ or with a 2-3µm diameter, 20-50µm depth in a few years. increases the cost of copper CMP. More recent ECD ‘backside contact.’ The process takes place on a device Maintaining an aspect ratio less than 12:1 allows a wider exhibits enhanced bottom-up fill, a wide process window, wafer that has been bonded face down to a carrier and more robust process window. The wafer temperature and overburden of less than 2µm on a 5µm via. This and then thinned by a grinding process. The adhesive is in the same range as that of BEOL films, typically process reduces the required thickness of the seed layer coating, carrier-wafer-to-device-wafer bonding, and wafer grinding introduces cross-wafer silicon thickness 350-400˚C. Via-middle TSVs offer the most flexibility and lowers CMP costs. Careful selection of the CMP non-uniformity (Figure 4). Provided the post-grind in layout, design, and via density. Provided post-TSV process and slurry is important to ensure clean copper thickness non-uniformity is radially symmetric, silicon processing planarity is good, interconnect wires from and barrier removal, freedom from corrosion of the CMP can improve the thickness profile. CMP polish M1 through Mx may be permitted to go above them. copper in the via or the barrier metal on the sidewall, heads with multi-zone-tuning capability can effectively Table 1 details the processes in the via-middle flow. and absence of divots or attack in the oxide lining the reduce both total thickness variation across the wafer inner circumference of the via. Figure 1 and surface roughness. Pre- and post-CMP silicon clean Typically between ECD and CMP steps, the copper is can be used to remove contamination, residue, and Via-Middle Via-Last annealed at approximately 400˚C in a forming gas (3% edge defects on the bonded wafer pair. Part 1. Form Vias from Front Side Form Vias from Back Side in MOL or BEOL Part 2. Backside Via Reveal After Thinning Figure 2

· TSV Via Etch, Strip · Edge Trim · Edge Trim Step-Coverage on Sidewall Thickness Scaling for Figure 2. Sidewall oxide and Clean · Temporary Bonding · Temporary Bonding High Aspect Ratio TSV (11:1) Medium Aspect Ratio TSV (6:1) · CVD Dielectric Liner · Grinding · Grinding conformality and scaling · Barrier/Seed 0.38µm 4µmx44µm 10µmx60µm · CMP Si · CMP Si 1.8µm 450nm in via-middle TSVs. · ECD Cu Fill, Anneal · Dry Si Recess Etch · Low Temp Nitride/Oxide · CMP Cu/Barrier/Dielectric (expose Cu pillar) · Via Etch, Strip, Clean · Low Temp Nitride/Oxide · Low Temp Oxide Liner 0.35µm 1.4µm 430nm · CMP Oxide/Nitride · Oxide Bottom Open and Clean Carrier Carrier · Barrier/Seed 0.28µm · ECD Cu 1.07µm 330nm · CMP Cu/Barrier/Dielectric Table 1

0.23µm 1.02µm 319nm Process Step Purpose Key Requirements Resist Coat and Lithography Exposure Create pattern. Resist thickness, exposure quality. Etch rate, profile/depth, selectivity (resist to 0.2µm Sidewall 1µm 0.3µm Dielectric and silicon etch to dielectric and silicon), undercut, non-uniformity Applied Materials internal data TSV Etch create vias. across wafer. Figure 3 All-in-one etch. Resist Strip and Wet Clean Clean vias. Post-etch residue removal. Barrier/Seed 25% Fill 50% Fill 75% Fill 100% Fill Figure 3. Progressive Step coverage, mechanical properties, leakage, copper ECD in 10:1 aspect Electrical isolation. breakdown voltage, and dielectric constant. Dielectric Oxide Liner Deposition ratio TSV showing Cu to bulk Si capacitance. Process Temperature ~400˚C. 2500Å to 1.5µm based on application. (a) enhanced bottom-up Copper diffusion barrier/seed fill with low copper over- Barrier/Seed Deposition Barrier properties and step coverage. for electroplating. burden in the field region, Electrochemical Deposition (ECD) Conducting plug. Void-free fill, copper quality, and stability. (b) close-up of complete fill, Anneal Stabilize film, control protrusions. Copper material properties. and (c) post-CMP appearance. Chemical Mechanical Planarization (CMP) Form copper plug. Flatness, topography. (a) (b)(c) Applied Materials internal data

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Figure 4 CONCLUSION Figure 4. Silicon CMP profile CMP Profile Control Improves WIW Silicon NU% CMP Profile Control Improves WTW Silicon NU% Via-middle and via-last integration schemes have 80 proven practical in creating high-density TSVs. Process control improves within- Post-CMP Profile-1 (Not Optimized) Pre-CMP Profile (After Grind) Post-CMP Profile-2 (Optimized) wafer (WIW) and wafer-to- 12 windows have been characterized for etch, CVD, PVD, Post-CMP Profile-3 (Optimized) 75 wafer (WTW) uniformity. ECD, and CMP to demonstrate successful via-middle 10 70 and backside via-reveal processes. Unit process

d (µm) 8 co-optimization and collaboration across the industry ickness (µm) ve 65 6 Th eco-system with wafer support systems (bonding/ emo 60 Si R thinning) is transitioning this technology from 4 Post-CMP Profile (Fine Polish) Device Si 55 development to production as an enabler of smaller, 2 faster, more functionally sophisticated, and more 0 50 energy-efficient consumer and industrial electronics.[6] -150 -100 -50 050 100 150 -150 -100 -50 050 100 150 Distance from Wafer Center (mm) Distance from Wafer Center (mm) ACKNOWLEDGEMENTS The authors wish to acknowledge the contributions of Figure 5 the technical staff from the etch, CVD, PVD, ECD, and

Figure 5. Via-reveal processes CVD Nitride/Oxide CMP business units, as well as the integration, process, CMP Si (Post-Grind) Recess Etch Passivation CMP Oxide with silicon recess etch. and analytical expertise of the staff of the Maydan Si Overburden Oxide Technology Center in Sunnyvale, California. Exposure Nitride (Pillar Height) REFERENCES [1] Kirk Saban, “Xilinx Stacked Silicon Interconnect Cu Technology Delivers Breakthrough FPGA Capacity, TSV Bandwidth, and Power Efficiency,” WP380 (v1.1),

Oxide/Liner Xilinx, October 21, 2011. Silicon FEOL/BEOL [2] G.E. Moore, “Cramming More Components into Bump/Pillar Adhesive Integrated Circuits,” Electronics, 38, No. 8, pp. 114- Carrier (Glass or Silicon) 117, 1965.

[3] M. Koyanagi, “Roadblocks in Achieving Three- Dimensional LSI,” Proc. 8th Symposium on Future Figure 6 Figure 5 details the via-reveal process sequence. The Electron Devices, pp. 50-60, 1989.

backside grind and silicon CMP stops short of the via, [4] Figure 6. SEM images of FOV = 5µm FOV = 100µm P. Ramm, et al., “Interchip-Via Technology for Vertical via-reveal results show which remains encased within the thinned silicon wafer. System Integration,” Proc. IEEE Int. Interconnect production-worthiness of Silicon recess etch exposes the via, without damaging Technology Conference, pp. 160-162, 2001. -Etch the via-middle oxide liner that encases it (penetration the process. st [5] K. Bernstein, et al., “Interconnects in the Third Po of the oxide would damage the titanium or tantalum Dimension: Design Challenges for 3D ICs,” Proc. barrier, or the copper fill). Low-temperature nitride and Design Automation Conference, 2007. FOV = 5µm FOV = 100µm oxide dielectric layers are then deposited for isolation and passivation. The nitride serves as a copper diffusion [6] Banqui Wu, et al., 3D IC Stacking Technology, barrier and etch stop for oxide CMP. Dielectric CMP McGraw-Hill Companies, Inc., New York, 2011. -CMP

st planarizes the resultant pillar structure and exposes Po the copper vias. The pillars are isolated from each other and mechanically supported by deposited dielectrics Applied Materials internal data between them, which serve as isolation for the subsequent micro-bump process. Examples of via- reveal on 5x50µm TSVs shown in Figure 6 demonstrate the production-worthiness of this scheme.

27 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Manufacture-Ready TSV

Figure 4 CONCLUSION AUTHORS CMP Profile Control Improves WIW Silicon NU% CMP Profile Control Improves WTW Silicon NU% Via-middle and via-last integration schemes have Niranjan Kumar is a product marketing manager in 80 proven practical in creating high-density TSVs. Process the Silicon Systems Group at Applied Materials. He Post-CMP Profile-1 (Not Optimized) Pre-CMP Profile (After Grind) Post-CMP Profile-2 (Optimized) 12 windows have been characterized for etch, CVD, PVD, holds his bachelors of technology degree from IIT Post-CMP Profile-3 (Optimized) 75 ECD, and CMP to demonstrate successful via-middle Kanpur, India, and certificate degree coursework from 10 70 and backside via-reveal processes. Unit process Stanford University, both in electrical engineering. d (µm) 8 co-optimization and collaboration across the industry ickness (µm) ve 65 Sesh Ramaswami is senior director, strategy, in 6 Th eco-system with wafer support systems (bonding/ emo the Silicon Systems Group at Applied Materials. He 60 Si R thinning) is transitioning this technology from 4 Post-CMP Profile (Fine Polish) earned his M.S. in chemical engineering from Syracuse Device Si 55 development to production as an enabler of smaller, 2 University and MBA from San Jose State University. faster, more functionally sophisticated, and more 0 50 energy-efficient consumer and industrial electronics.[6] Rao Yalamanchili is the head of the TSV Etch Products -150 -100 -50 050 100 150 -150 -100 -50 050 100 150 group at Applied Materials. He received his Ph.D. in Distance from Wafer Center (mm) Distance from Wafer Center (mm) ACKNOWLEDGEMENTS metallurgical engineering from the University of Utah. The authors wish to acknowledge the contributions of Figure 5 the technical staff from the etch, CVD, PVD, ECD, and Manuel Hernandez is a process engineering manager in CVD Nitride/Oxide CMP business units, as well as the integration, process, the Gap Fill division at Applied Materials. He holds his CMP Si (Post-Grind) Recess Etch Passivation CMP Oxide and analytical expertise of the staff of the Maydan M.S. in materials science and engineering from Stanford University. Si Overburden Oxide Technology Center in Sunnyvale, California. Exposure Nitride (Pillar Height) REFERENCES Nagarajan Rajagopalan is a senior member of technical [1] Kirk Saban, “Xilinx Stacked Silicon Interconnect staff in the Dielectric Systems and Modules business Cu Technology Delivers Breakthrough FPGA Capacity, unit at Applied Materials. He earned his Ph.D. in TSV Bandwidth, and Power Efficiency,” WP380 (v1.1), metallurgy from the Indian Institute of Science,

Oxide/Liner Xilinx, October 21, 2011. Bangalore, India. Silicon FEOL/BEOL [2] G.E. Moore, “Cramming More Components into Anthony C-T Chan is a TSV technology manager for Bump/Pillar the Metal Deposition division at Applied Materials. He Adhesive Integrated Circuits,” Electronics, 38, No. 8, pp. 114- Carrier (Glass or Silicon) 117, 1965. received his Ph.D. in surface physics from Rensselaer Polytechnic Institute. [3] M. Koyanagi, “Roadblocks in Achieving Three- Dimensional LSI,” Proc. 8th Symposium on Future Bob Linke is a process integration manager in the Semitool business unit at Applied Materials. He holds Figure 5 details the via-reveal process sequence. The Electron Devices, pp. 50-60, 1989. his B.S. in chemical engineering from the University of backside grind and silicon CMP stops short of the via, [4] P. Ramm, et al., “Interchip-Via Technology for Vertical Missouri – Rolla. which remains encased within the thinned silicon wafer. System Integration,” Proc. IEEE Int. Interconnect Silicon recess etch exposes the via, without damaging Technology Conference, pp. 160-162, 2001. Zhihong Wang is a senior manager in the CMP division the via-middle oxide liner that encases it (penetration at Applied Materials. He earned his Ph.D. in chemical [5] K. Bernstein, et al., “Interconnects in the Third of the oxide would damage the titanium or tantalum engineering from the Massachusetts Institute of Dimension: Design Challenges for 3D ICs,” Proc. barrier, or the copper fill). Low-temperature nitride and Technology. Design Automation Conference, 2007. oxide dielectric layers are then deposited for isolation John Dukovic is a distinguished member of technical and passivation. The nitride serves as a copper diffusion [6] Banqui Wu, et al., 3D IC Stacking Technology, staff in the CTO office of the Silicon Systems Group at barrier and etch stop for oxide CMP. Dielectric CMP McGraw-Hill Companies, Inc., New York, 2011. Applied Materials. He received his Ph.D. in chemical planarizes the resultant pillar structure and exposes engineering from the University of California at Berkeley. the copper vias. The pillars are isolated from each other and mechanically supported by deposited dielectrics ARTICLE CONTACT between them, which serve as isolation for the [email protected] subsequent micro-bump process. Examples of via- reveal on 5x50µm TSVs shown in Figure 6 demonstrate the production-worthiness of this scheme.

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 28 Figure 1

Typical Nuisance ENHANCED DEFECT OF Critical DOI

INTEREST MONITORING atio n False With Sensitive Inspection and “Intelligent” SEM Review Alarm Rate

KEYWORDS As semiconductor fabrication technology advances In-Line below 45nm, two dominant trends make in-line wafer Separ Optical Attributes Defectivity inspection more challenging: an increase in the number Process Control of nuisances (“false defects”) and a decrease in size 90 65 45 32 22 Design Rule SEM and signal of DOI. As a result, we see a reduction in Wafer Inspection Review the number of true defect types represented in the However, as design rules shrink and DOI become ADR post-SEM review pareto, which reduces the ability to smaller, the capability of optical inspection tools to monitor the process efficiently and influences the separate the nuisance from true defects is limited statistical process control (SPC) quality. The International (Figure 1) and the fab must choose between high Technology Roadmap for Semiconductors (ITRS)[1] has sensitivity with high nuisance rates or compromised highlighted the increasing need for detecting small, sensitivity (Figure 2). Optimizing inspection sensitivity yield-limiting defects at high capture rate and the ability will enable detection and monitoring of new DOI types; to separate these defects from nuisance at low cost however, the high nuisance rate will increase the volume of ownership, specifically the need to find small but of defect review (Figure 3). yield-relevant defects under a vast amount of nuisance As part of process monitoring, inspection results are defects. sampled for defect review and classification by SEM Now a more comprehensive and robust wafer-level images. The objective of this review is to identify each in-line yield monitoring system enables better data type of defect and to remove the nuisance. The high quality for further analysis. The system comprises inspection nuisance rate results in lower DOI count inspection optimized for DOI detection and automatic in the classification pareto (Figure 4), which reduces SEM review (automatic defect redetection – ADR) monitoring reliability. Sampling more defects improves optimized for nuisance filtering to enable true-only the number of true defects, but incurs additional manual classification. This new approach employs the current classification work, which will grow significantly as the inspection fab toolset and the same amount of labor, nuisance rate rises. As semiconductor design rules shrink, optical inspection but results in a much richer DOI pareto and makes it tools are challenged to separate between true and false Figure 4 possible to identify excursions of DOI types that could defects owing to the lower signal from real defects while not previously be monitored. Traditional Method Alternative Option noise levels remain almost constant. The resulting high rate Nuisance Operator of false defects jeopardizes the creation of a true defect DOI REPRESENTATION IN PARETO Population Classified Defects s pareto. Traditionally, inspection tool recipes were optimized Inspection tools are required to provide a wafer map s Operator to provide defect maps with a low (~10%) false rate, but depicting the locations of suspected defects with the Classified Defects Nuisance goal of maximizing sensitivity to DOI while maintaining Nuisance ed Defect as defects of interest (DOI) shrink this detection sensitivity ed Defect Nuisance Nuisance Nuisance low nuisance rate. This is crucial to minimize Nuisance view must be compromised. A new approach optimizes the view Nuisance Nuisance Re Re True recipe for sensitivity, introducing new challenges for SEM classification effort (typically performed manually Defects True True True True True review tools. A complementary advance in review technology based on SEM images). In the past, this requirement True True True Defects Defects Defects Defects Defects Defects Defects True enhances process monitoring, reveals new defect types in was easily met, inspection recipes were optimized for 90 65 45 32 22 90 65 45 32 22 the pareto, and improves the ability to identify excursions maximal sensitivity, and nuisance rate was maintained Design Rule Design Rule for low magnitude DOI. at less than 10% of the suspected defects. (a) (b)

29 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Automatic Defect Redetection

Figure 1 Figure 2

Typical Nuisance Nuisance Figure 1. DOI and nuisance ENHANCED DEFECT OF Critical DOI DOI signal trends and their effect Inspection Threshold Inspection Threshold on inspection nuisance. INTEREST MONITORING atio n To Maintain 10% Nuisance To Maintain 10% Nuisance False Figure 2. As technology Alarm Rate With Sensitive Inspection and “Intelligent” SEM Review progresses, inspection must choose between sensitivity and nuisance rate. As semiconductor fabrication technology advances below 45nm, two dominant trends make in-line wafer Separ Optical Attributes inspection more challenging: an increase in the number of nuisances (“false defects”) and a decrease in size 90 65 45 32 22 Design Rule Technology and signal of DOI. As a result, we see a reduction in the number of true defect types represented in the However, as design rules shrink and DOI become Figure 3 post-SEM review pareto, which reduces the ability to smaller, the capability of optical inspection tools to monitor the process efficiently and influences the separate the nuisance from true defects is limited Sensitivity − Nuisance Trade-O Figure 3. Inspection results show a trade-off between statistical process control (SPC) quality. The International (Figure 1) and the fab must choose between high Optimized for DOI Detection Optimized for Low Nuisance Rate Technology Roadmap for Semiconductors (ITRS)[1] has sensitivity with high nuisance rates or compromised maximal sensitivity and highlighted the increasing need for detecting small, sensitivity (Figure 2). Optimizing inspection sensitivity low nuisance rate. When yield-limiting defects at high capture rate and the ability will enable detection and monitoring of new DOI types; the recipe is optimized for to separate these defects from nuisance at low cost however, the high nuisance rate will increase the volume maximal sensitivity, several of ownership, specifically the need to find small but of defect review (Figure 3). defect types are detected yield-relevant defects under a vast amount of nuisance that are missed when the As part of process monitoring, inspection results are defects. recipe is optimized for low sampled for defect review and classification by SEM nuisance rate. Now a more comprehensive and robust wafer-level images. The objective of this review is to identify each in-line yield monitoring system enables better data type of defect and to remove the nuisance. The high quality for further analysis. The system comprises inspection nuisance rate results in lower DOI count Pitting Scratch Hole Extra Defocus Shallow SEM NV Pattern Extra inspection optimized for DOI detection and automatic in the classification pareto (Figure 4), which reduces Pattern SEM review (automatic defect redetection – ADR) monitoring reliability. Sampling more defects improves optimized for nuisance filtering to enable true-only the number of true defects, but incurs additional manual classification. This new approach employs the current classification work, which will grow significantly as the inspection fab toolset and the same amount of labor, nuisance rate rises. but results in a much richer DOI pareto and makes it Figure 4 possible to identify excursions of DOI types that could not previously be monitored. Traditional Method Alternative Option Figure 4. (a) High nuisance rate reduces the number DOI REPRESENTATION IN PARETO Nuisance Operator Population Classified Defects of true defects in the

Inspection tools are required to provide a wafer map s s classification pareto. depicting the locations of suspected defects with the Operator Classified (b) Maintaining a constant Defects Nuisance goal of maximizing sensitivity to DOI while maintaining Nuisance ed Defect ed Defect Nuisance number of true defects Nuisance Nuisance low nuisance rate. This is crucial to minimize Nuisance view Nuisance view Nuisance requires additional review

Re True Re classification effort (typically performed manually Defects True True True True True and classification manual based on SEM images). In the past, this requirement True True True Defects Defects Defects Defects Defects Defects Defects True work. was easily met, inspection recipes were optimized for 90 65 45 32 22 90 65 45 32 22 maximal sensitivity, and nuisance rate was maintained Design Rule Design Rule at less than 10% of the suspected defects. (a) (b)

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 30 Automatic Defect Redetection

AUTOMATIC SEM REVIEW CONCEPT Two inherent advantages of the SEM over optical The ability to monitor excursions for each DOI type was Traditionally, SEM review is performed on a sample of inspection tools enable this filtering: also tested by examining SPC charts of each defect type the inspection results. The images are then manually over the 19 wafers. Results demonstrate a dramatic • Higher resolution—SEM pixel size is significantly classified for DOI/nuisance and for the different DOI improvement in the ability to monitor excursions, smaller types. When the inspection nuisance rate is high, especially for rarely occurring DOI (Figure 8). Early a major part of the classification work is spent on • Reduced underlayer visibility—contrary to the excursion detection enables the fab to react promptly nuisances. SEM automatic defect redetection (ADR) optical tool, only the top layers are visible by before the source of the excursion significantly affects can filter out most of the nuisances, allowing manual SEM imaging, which efficiently separates top yield. classification effort to be devoted to true defects, layer defects from lower layer defects (usually binning them according to different DOI types. considered nuisance and detected when the A greater number of defects can thus be reviewed for top layer is transparent to the inspection tool the same investment of labor (Figure 5). wavelength) Figure 8 Figure 5 Defocus Shallow Extra Pattern Figure 5. True and nuisance Post-Inspection Results Post-Filtering Results Traditional Traditional distribution per wafer before Nuisance Nuisance 10 New Flow 30 New Flow DOI DOI and after SEM ADR filtering. 250 250 s s

d d 20 200 200 5 150 150 # of Defect # of Defect 10

100 100

Defects Inspecte Defects Inspecte 0 0 50 50 Lot1 Lot1 Lot1 Lot2 Lot2 Lot2 Lot3 Lot3 Lot3 Lot4 Lot4 Lot4 Lot5 Lot5 Lot5 Lot6 Lot6 Lot6 Lot6 Lot1 Lot1 Lot1 Lot2 Lot2 Lot2 Lot3 Lot3 Lot3 Lot4 Lot4 Lot4 Lot5 Lot5 Lot5 Lot6 Lot6 Lot6 Lot6 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W6 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W6 Lot/Wafer Lot/Wafer 0 0 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 (a) (b) Wafers Wafers CONCLUSION Figure 6 Figure 6 demonstrates the enhanced results and labor- Shrinking design rules make separating true from saving effectiveness of the SEM ADR when the SEM nuisance defects detected by optical inspection tools Figure 6. New ADR method ADR Set to Stop at 60 True was set to review defects until it reached a constant, ever more challenging. To address this challenge set to 60 true defects keeps Nuisance predefined number (60) of true defects in each run without adding to the fab burden, new inspection and classification effort constant. DOI 60 (versus the traditional fixed number of total reviewed review methods employ SEM-inherent advantages

50 defects). for automatic review and nuisance filtering. The new s method revealed DOI types in the pareto that were 40 Results undetected by traditional production flow. Moreover, 30 Analysis was performed on <45nm node features using ue Defect

Tr the new method is also more sensitive to excursions in 20 19 wafers from different lots. Each wafer was inspected the defect type count. These two enhancements in 10 and reviewed twice, first using the “traditional” approach (inspection recipe optimized for low nuisance, review defect monitoring can cost-effectively improve fab 0 yield-management capabilities by using the existing W1 W3 W5 W7 W9 W11W13 W15W17 W19 of 60 locations) and then using the new approach Wafers (inspection recipe optimized for maximum sensitivity, toolset and not requiring additional labor. automatic review until 60 true defects were detected by ACKNOWLEDGEMENTS Table 1 SEM). DOI were manually classified (60 images for each The authors wish to acknowledge the collaboration of Table 1. Comparison of method). Table 1 summarizes the comparative results. Remo Kirsch and Ulrich Zeiske of GLOBALFOUNDRIES Defect traditional and new Defect Reviewed DOI in this work. Method Manually The results demonstrate that the new method improves by SEM Types approaches for types of Classified SPC for different DOI types by making available to REFERENCES DOI that can be monitored. the fab an enhanced data set on which to base the [1] “2010 Update, International Technology Roadmap Traditional 60 (fixed per wafer) 60 3 monitoring process. DOI types that could not be for Semiconductors,” Semiconductor Industry New 180 (average) 60 6 monitored before now appear in numbers that allows Association, http://www.itrs.net/Links/2010ITRS/ stable monitoring (Figure 7). Home2010.htm.

31 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc. Automatic Defect Redetection

Two inherent advantages of the SEM over optical The ability to monitor excursions for each DOI type was Figure 7 also tested by examining SPC charts of each defect type inspection tools enable this filtering: Defect Pareto Figure 7. Traditional 60 over the 19 wafers. Results demonstrate a dramatic Traditional defects review versus ADR • Higher resolution—SEM pixel size is significantly New Flow improvement in the ability to monitor excursions, 30 smaller set to 60 true defects shows especially for rarely occurring DOI (Figure 8). Early 25 the new DOI types revealed

• Reduced underlayer visibility—contrary to the excursion detection enables the fab to react promptly s 20 by the new approach. optical tool, only the top layers are visible by before the source of the excursion significantly affects 15 Defect

SEM imaging, which efficiently separates top yield. 10 layer defects from lower layer defects (usually 5 considered nuisance and detected when the 0 top layer is transparent to the inspection tool Pitting Scratch Hole Extra DefocusShallow SEM NV Pattern Extra wavelength) Pattern Figure 8 Figure 5 Defocus Shallow Extra Pattern Figure 8. (a) SPC chart Post-Inspection Results Post-Filtering Results Traditional Traditional for DOI Defocus and Nuisance Nuisance 10 New Flow 30 New Flow (b) Shallow Extra Pattern DOI DOI 250 250 s s illustrates that the excursions

d d 20 200 200 were identified only by using 5 the new flow. 150 150 # of Defect # of Defect 10

100 100

Defects Inspecte Defects Inspecte 0 0 50 50 Lot1 Lot1 Lot1 Lot2 Lot2 Lot2 Lot3 Lot3 Lot3 Lot4 Lot4 Lot4 Lot5 Lot5 Lot5 Lot6 Lot6 Lot6 Lot6 Lot1 Lot1 Lot1 Lot2 Lot2 Lot2 Lot3 Lot3 Lot3 Lot4 Lot4 Lot4 Lot5 Lot5 Lot5 Lot6 Lot6 Lot6 Lot6 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W6 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W1 W2 W3 W6 Lot/Wafer Lot/Wafer 0 0 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 (a) (b) Wafers Wafers CONCLUSION AUTHORS Figure 6 demonstrates the enhanced results and labor- Shrinking design rules make separating true from Liran Yerushalmi is a marketing manager in the PDC saving effectiveness of the SEM ADR when the SEM nuisance defects detected by optical inspection tools Group at Applied Materials. He earned his MBA in was set to review defects until it reached a constant, ever more challenging. To address this challenge business management from Tel Aviv University, Israel. predefined number (60) of true defects in each run without adding to the fab burden, new inspection and Saar Shabtay is an application development manager in (versus the traditional fixed number of total reviewed review methods employ SEM-inherent advantages the PDC Group at Applied Materials. He holds his B.S. defects). for automatic review and nuisance filtering. The new in physics from Ben Gurion University, Israel. method revealed DOI types in the pareto that were Results undetected by traditional production flow. Moreover, Analysis was performed on <45nm node features using Mirko Beyer is a senior application engineer in the PDC the new method is also more sensitive to excursions in 19 wafers from different lots. Each wafer was inspected group at Applied Materials, supporting the Dresden and reviewed twice, first using the “traditional” approach the defect type count. These two enhancements in Logic Account team. defect monitoring can cost-effectively improve fab (inspection recipe optimized for low nuisance, review Oren Goshen is a product specialist in the PDC Group at yield-management capabilities by using the existing of 60 locations) and then using the new approach Applied Materials. He received his B.A. in mathematics toolset and not requiring additional labor. (inspection recipe optimized for maximum sensitivity, from Ben Gurion University, Israel. automatic review until 60 true defects were detected by ACKNOWLEDGEMENTS SEM). DOI were manually classified (60 images for each The authors wish to acknowledge the collaboration of ARTICLE CONTACT method). Table 1 summarizes the comparative results. Remo Kirsch and Ulrich Zeiske of GLOBALFOUNDRIES [email protected] The results demonstrate that the new method improves in this work. Adapted from Metrology, Inspection and Process Control SPC for different DOI types by making available to REFERENCES for Microlithography XXV, Proc. of SPIE Vol. 7971 79712M-1- the fab an enhanced data set on which to base the [1] “2010 Update, International Technology Roadmap 79712M-8. © 2011 SPIE. monitoring process. DOI types that could not be for Semiconductors,” Semiconductor Industry monitored before now appear in numbers that allows Association, http://www.itrs.net/Links/2010ITRS/ stable monitoring (Figure 7). Home2010.htm.

Applied Materials, Inc. Applied Materials, Inc. Nanochip Technology Journal Volume 10, Issue 1, 2012 32 Notes

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