Method for Brazing Interconnect Pins to Metallic Pads

Europaisches Patentamt J) European Patent Office © Publication number: 0 198 354 Office europeen des brevets A2

© Designated Contracting States: @ Inventor: Churchwell, Robert William DE FR GB IT 10 Merritt Avenue Highland New York 12528(US) Inventor: Flaitz, Philip Lee R.D. No. 3, Shennandoah Road Hopewell Junction New York 12533(US) Inventor: Humenik, James Noel 319 Pulling Road La Grangeville New York 12540(US)

A method for use in brazing an interconnect pin to a portion of metallization pattern (e.g. a pad) existing on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, is disclosed. The invention relates to a method for brazing brazing, various elemental constituents of the braz- interconnect pins to metallic pads formed on a ing alloy migrate into the pad and form inter- brittle dielectric substrate, such as a multi-layered metallic compounds therein which greatly increase ceramic (MLC) substrate. the stress occurring within the pad. Third, the braze A multi-chip integrated circuit package employ- often becomes embrittled when it reacts with other ing the well-known "flip-chip" technique utilizes a materials to which the MLC substrate is exposed multi-layer ceramic substrate (MLC) --constructed during its fabrication. of a plurality of laminated ceramic layers. All the In any event, the tensile stress resulting from individual chips are mounted to the top layer of the the braze additively combines with the stress re- MLC substrate. A pre-defined metallization pattern sulting from the thermal coefficient mis-match, be- lies on each ceramic layer within the substrate. tween the pad and the MLC substrate, to produce Metallization patterns on certain layers act as volt- the total tensile stress exerted on the substrate. A age reference planes and also provide power to the ceramic layer is quite weak in tension. Further- individual chips. Metallization patterns on other lay- more, this total stress is greatest around the edges ers route signals between individual chips. Elec- of the pad. Consequently, at the edges, the total trical connections to individual terminals of each tensile stress exerted onto the MLC substrate often chip and/or between separate layers are made disadvantageously reaches a level sufficiently high through well-known vertical interconnects called to fracture the ceramic situated directly under the "vias". Interconnect pins are bonded to metallic pad. This fracturing can cause the interconnect pin pads situated on the bottom surface of the MLC and the pad to mechanically separate from the substrate and thereby connected to appropriate substrate, thereby ruining the integrated circuit metallization patterns existing within the substrate. package. These interconnect pins route electrical signals be- The art has taught that this tensile stress can tween a multi-chip integrated circuit package and be reduced by two techniques. First, as disclosed external devices. in N. Ainsie et al, "Au/Sn/Ag Braze Alloy", IBM One well known technique of mounting an in- Technical Disclosure Bulletin, Vol. 21, No. 8, Janu- terconnect pin to such a metallic pad involves ary 1979, page 3117, and in N. Ainsle et al, coating the pad and the pin with a protective metal- "Au/Sn/Ag Braze Alloy", IBM Technical Disclosure lic layer that serves as a diffusion barrier, and Bulletin, Vol. 21, No. 8, January 1979, page 3118, thereafter coating the pad and the head of the pin the brazing alloy can be changed to one which with an appropriate brazing alloy, and then brazing imparts a relatively low value of stress to a metallic the pin to the pad. Unfortunately, this technique pad. While this appears to be a theoretically simple often produces stress between the pad and the and ideal solution, it is often extremely difficult to underlying ceramic substrate that can lead to frac- implement in practice. First, a multi-chip integrated tures in the ceramic situated directly beneath the circuit package contains a pre-determined thermal pad. hierarchy, i.e. certain components of the package - This stress originates from two sources: from such as solder joints between individual chips and the interface between the metallic pad and the the MLC substrate -must melt before other com- MLC substrate, and from the brazed joint itself. ponents. This ensures that a chip can be heated to Specifically, the MLC substrate is rather brittle and a temperature which will only weaken the solder has a thermal coefficient of expansion different joint between it and the MLC substrate and enable from that of the pad. Consequently, due to the the chip to be removed from the substrate without thermal expansion mis-match at the interface be- damaging other portions of the package. Conse- tween the pad and the MLC substrate, the ceramic quently, the operating temperatures of the chosen situated directly beneath the pad is placed in con- brazing alloy must fall within certain prescribed siderable stress. ranges in this hierarchy. Second, both the pad and In addition, the brazed joint imparts consider- the interconnect pin are generally fabricated using able tensile stress to the pad which is directed an underlying alloy having a multi-layered metallic through the pad to the underlying MLC substrate. coating. Unfortunately, various elemental constitu- Although the predominant mechanism causing this ents (particularly tin) of the brazing alloy will often phenomenon is not completely known, it appears migrate into one or more of the layers comprisng that several factors are at least partially responsi- the pin and/or the pad and form inter-metallic com- ble. First, there is a thermal expansion mis-match pounds which greatly increase the tensile stress between the braze and the pad. Second, during occurring therein. To prevent this, an appropriate metallic diffusion barrier is applied over both the The advantages offered by the invention are pin and the pad before applying the brazing alloy. mainly that the tensile stress, occuring at the inter- Although such diffusion barriers exist for many face between a metallic pad and the bottom sur- brazing alloys, appropriate barriers do not exist for face of an MLC substrate and resulting from braz- others. Lastly, different brazing alloys become ing, is reduced to a value which is less than that overly ductile or overly elastic when brazed and required to fracture the substrate and that the need are thus unsuitable to bond an interconnect pin to a to change the brazing alloy is eliminated. metallic pad. Hence, choosing a different brazing A strong minimally resistive brazed joint be- alloy generally requires that the metallurgy of tween the pad and the pin is provided and the many, if not all, of the interconnects (i.e. the sepa- mechanical strength of both the MLC substrate and rate metallurgies comprising the so-called intercon- the interface between the pad and the dielectric nect hierarchy) existing within the MLC substrate substrate is increased. be completely re-assessed and possibly re-de- Lastly, a simple method that is easy to imple- signed. Thus, once the metallurgy of all the inter- ment in a production environment is provided by connects has been determined which of necessity the invention. includes selecting an appropriate brazing alloy, These advantages are achieved in accordance substrate manufacturers are quite reluctant to with the teachings of the present invention by Hmtt- change this alloy. ing the contact of the brazing alloy with the pad Second, each metallic pad can be divided into such that the brazed joint between the pin and the separate non-overlapping wettable segments each pad exists primarily in the center of the pad. surrounded by a non-wettable area. The brazing In particular, we have discovered that brazing alloy would only adhere to the wettable areas. This an interconnect pin to a metallic pad causes the technique produces a bond consisting of many tensile stress occurring at the edge of a pad to be individual brazed joints in which each joint extends greatest whenever the brazed joint is allowed to over a very small area. Inasmuch as the cross- extend to an edge of the pad. sectional area of each joint is very small, each of Consequently, in accordance with the preferred these joints is quite weak. In addition, as the pad is embodiment of the present invention, a braze re- divided into a greater number of increasingly small- stricting dielectric layer is applied over the bottom er wettable segments, the effective cross-sectional surface of the MLC substrate and all the pads prior area occupied by all the brazed joints becomes to applying the brazing alloy. The braze restricting significantly less than that of the pad. Hence, the layer is formed with appropriate annular openings. electrical resistance of the entire bond between the Each opening covers a closed peripheral portion, interconnect pin and the pad correspondingly in- generally annularly shaped, of each associated creases. Furthermore, this technique is very dif- pad. Each opening also provides a closed contain- ficult and cumbersome to implement in practice. ment wall, which extends around and above the This technique is described, in connection with a pad, to hold the brazing alloy. Each circular con- solder bond, in R. W. Noth, "Solder Bond", IBM tainment wall is concentrically aligned with its asso- Technical Disclosure Bulletin, Vol. 17, No. 8, Janu- ciated pad and exposes an area, of each pad, ary 1975, page 2214. having a smaller diameter than that of the entire Hence, a need exists in the art for a method, pad. Consequently, when the brazing alloy is ap- suitable for use in brazing an interconnect pin to a plied over the braze restricting layer, this alloy will metallic pad, which will lower the tensile stress be restrained by the containment walls from com- between the pad and an adjacent dielectric (e.g. ing into contact with any edge of any of the pads. MLC) substrate, occurring during a brazing opera- Thus, the brazed joint for that pad will not extend tion, while eliminating any need to change the to the edge of that pad. This advantageously brazing alloy and simultaneously permitting a lowers the tensile stress occurring at the interface strong, reliable, minimally resistive brazed joint to between the pad and the MLC substrate to a value, form between the interconnect pin and the pad. at the edge of the pad, below that required to The invention as claimed solves the problem of fracture the substrate. Advantageously, the main providing a method for use in brazing an intercon- mechanism for interconnect pin failures then be- nect pin to a portion of metallization pattern, situ- comes the shank of the pin and not the pin/pad ated on a brittle dielectric substrate, such as an interface. MLC substrate, which produces a reliable bond In accordance with a feature of the invention, between the metallization pattern and the pin. the braze restricting layer should advantageously be a compressive layer. Such a layer is comprised of dielectric material having a lower thermal coefficient of expansion than the MLC substrate. Use of known brazing alloy, then brought into contact with a compressive layer, as taught by B. Schwartz each other and thereafter brazed. As a result, once "Making High Strength Ceramics", IBM Technical brazing has occurred, the brazed joint 12, as Disclosure Bulletin, Vol. 11, No. 7, December 1968, shown, extends to edges 25 of pad 20. page 848, places the bottom surface of the MLC Unfortunately, this prior art technique produces substrate in a state of compression. Ceramic ma- considerable tensile stress at the edges of the pad. terial is considerably stronger in compression than This stress, in turn, may cause the ceramic located in tension. Hence, we have found that use of a directly beneath the pad, i.e. in the vicinity of compressive braze restricting layer partially offsets interface 28 situated between the pad and the the tensile stress imparted to the MLC substrate by substrate, to fracture. As a result, the interconnect the braze. Consequently, use of a compressive pin and its brazed pad may mechanically separate dielectric braze restricting layer advantageously from the substrate and thereby ruin the integrated strengthens the bottom surface of the ceramic sub- circuit package. Specifically, dielectric substrate 30 strate and in particular the interface between the is rather brittle and has a thermal coefficient of pad and the ceramic. expansion different from that of pad 20. Conse- The invention is described in detail below in quently, a significant thermal expansion coefficient conjunction with the drawing, in which: mis-match exists at interface 28 between pad 20 FIG. 1 depicts a cross-sectional view of an and dielectric substrate 30 which, in turn, places interconnect pin bonded to a metallic pad on a that portion of the dielectric substrate situated di- dielectric substrate by a technique well known rectly beneath the pad in stress. This mismatch in the art; and worsens once the pad is coated with the metallic FIG. 2 depicts a cross-sectional view of an protective layer and then brazed. As a result, dur- interconnect pin bonded to a metallic pad on a ing brazing the substrate is placed in considerable dielectric substrate in accordance with the tension. The tensile stress is greatest at edges 25 teachings of the present invention. of pad 20. A ceramic layer is weak in tension. Consequently, the tensile stress occurring at an _Applicants' inventive method for brazing an in- edge of the pad often reaches a level sufficient to terconnect pin to a region of a metallization pattern fracture the substrate situated beneath the pad. is applicable in fabricating any apparatus where a Disadvantageously, this fracturing may cause both dielectric layer serves as the substrate for the interconnect pin 10 and pad 20, to which this pin is metallization pattern and a thermal expansion mis- brazed, to separate from the substrate. match exists at the interface between the metal- We have discovered that the tensile stress lization pattern and the dielectric layer. For exam- occurring at the interface between a metallic pad - ple such a dielectric layer exists as the bottom (e.g. pad 20) and a dielectric substrate (e.g. sub- layer of a MLC substrate used in a "flip-chip" strate 30), as a result of brazing a interconnect pin multi-chip package or as the substrate for a metal- to the pad, is greatest whenever the brazed joint - lization pattern (traces and pads) in a printed circuit (e.g. brazed joint 13) is allowed to extend to an board. Hence, to simplify the ensuring discussion, edge of the pad. any such dielectric layer will be collectively re- Consequently, in accordance with the princi- ferred to as a dielectric substrate. ples of the present invention, we limit the contact FIG. 1 depicts a cross-sectional view of inter- of the brazing alloy with a pad such that the brazed connect pin 10 brazed to a region of a metallization joint between a pin and the pad exists primarily in pattern (illustratively circularly shaped pad 20) situ- the center of the pad and does not extend to any ated on a dielectric substrate by a technique well edges of the pad. In particular, we have found that known in the art. Here, as shown, metallic pad 20 the tensile stress imparted by the brazed joint to a is first conventionally fabricated on surface 33 of pad, and transmitted therethrough to the underlying dielectric substrate 30. This surface could be the dielectric substrate, is greatest at the edge of the bottom surface of an MLC susbtrate. Thereafter, braze and increases nearly exponentially with dis- the pad is coated with a metallic protective - tance away from the center of the braze and to- (diffusion barrier) layer (not shown). This material wards its edge. Moreover, the stress imparted to used for this protective layer is determined by the the dielectric substrate by the pad itself is greatest metallurgies of pad 20 and interconnect pin 10, and at the edges of the pad and also increases nearly the brazing alloy. In order to mount the pin to the exponentially with distance away from the center of pad, both pad 20 and head 12 of pin 10 are first the pad and towards its edges. Since these stress- completely coated (wetted) with a suitable well- es add to form the total stress exerted by the pad onto dielectric substrate 20, the brazing alloy need only be kept a small distance away from all the mis-aligned (offset) with respect to each other, and edges of the pad to provide a substantial reduction hence some slight deviations in the width of this in tensile stress occurring along the edges - annular portion are bound to occur around the - (perimeter) of the pad. This advantageously per- periphery of opening 55. As long as these de- mits the brazed joint to extend over a significant viations are kept small, no adverse results will portion of the pad and thereby form a strong reli- occur. able contact having minimal electrical resistance Opening 55 has walls 58. These walls --illustra- while minimizing any additional tensile stress im- tively shown as being inwardly sloping for pur- parted by the brazed joint to the edge of any pad. poses of illustration but need not be in actuality -- As a result of our inventive method, the main completely encircle opening 55 and form a closed mechanism for pin failures advantageously be- containment vehicle extending around and above comes the shank of the interconnect pin. These pad 60. When the brazing alloy is applied within failures can be easily remedied by merely replac- opening 55 of braze restricting layer 50, this alloy ing the pin. is totally confined within the containment vehicle FIG> 2 depicts a cross-sectional view of inter- and is thereby prevented from contacting edges 65 connect pin 70 bonded to circularly shaped pad 60 of pad 60. Hence, once head 72 of interconnect pin on dielectric substrate 40, in accordance with the 70 is brazed to pad 60, brazed joint 73 advanta- teachings of the present invention. Here, as shown, geously does not extend to edges 65 of pad 60. As metallic pad 60, similar to pad 20 shown in FIG. 1, a result, the stress imparted to pad 60 by brazed is bonded to surface 43 of dielectric substrate 40 joint 73 does not reach the edges of the pad, using any one of many well-known techniques. where the stress occurring within the pad reaches Braze restricting dielectric layer 50 is situated over a relatively large maximum value. Since the stress both dielectric substrate 40 and all the pads lo- occurring within pad 60 decreases nearly exponen- cated thereon. As explained in detail later, the tially as a function of distance away from the edge braze restricting layer can be applied either co- of the pad and towards its center, a relatively low incident with or subsequent to the fabrication of the stress region within pad 60 begins at a small dielectric substrate. Layer 50 can be any dielectric distance "r" away from edge 65. As such, the total layer compatible with dielectric substrate 40. How- stress, imparted by the additive combination of the ever for reasons that will shortly become clear, stress produced by brazed joiht 73 and directed braze restricting layer 50 should preferably be a through pad 60 and the stress occurring within pad compressive layer and, as such, fabricated from a 60 by virtue of the thermal expansion coefficient dielectric material having a lower thermal coeffi- mis-match between the pad and dielectric sub- cient of expansion than that of the dielectric substrate 40, advantageously remains below the value strate. required to fracture dielectric substrate 40. This is In addition, braze restricting layer 50 has a particularly true at edges 71 of brazed joint 73 number of circular openings, each of which is con- where the stress imparted by the brazed joint centrically aligned over a corresponding pad. Inas- reaches a maximum value. In practice, excellent much as all the openings are structurally identical, results have been achieved if opening 55 encircles for purposes of simplicity FIG. 2 only shows one an area that is approximately 80% of the total such opening, opening 55, and the following dis- surface area of pad 60. Clearly, this percentage is cussion will be limited to specifically discussing not critical; however, to ensure adequate bond opening 55. strength and minimal electrical contact resistance In particular, opening 55, has a smaller diam- between interconnect pin 70 and pad 60, this per- eter than that of pad"60. As such, braze restricting centage should be kept as high as possible. As layer 50 overlaps a closed annularly shaped pe- such, this percentage will be governed, in part, by ripherally located portion of pad 60 and exposes the magnitude of any expected clamping forces the remaining centrally located portion of the pad. that will be applied to the interconnect pin. This annularly shaped over-lapped portion com- Moreover, both dielectric substrate 40 and the prises circular edge 65 of pad 60 and that periph- interface between pad 60 and the substrate can be eral area of the pad contained within an distance advantageously strengthened if braze restricting "r" measured inward from edge 65. Ideally, if di- layer 50 is a compressive layer. In particular, if electric layer 50 is properly aligned with substrate braze restricting layer 50 has a lower thermal co- 40, then the width ("r") of the over-lapped annularly efficient of expansion than the substrate, then this a shaped area should be the same all around the state of compression, thereby partially ofsetting the pad. However, in practice, the center of opening 55 tensile stress imparted to the substrate by the pad and the center of pad 60 are likely to be slightly itself and the brazed joint. A suitable compressive layer can be fabricated by slightly altering the braze restricting layer could also be deposited from composition of the materials used for fabricating a re-flowed slurry and then appropriately etched to dielectric substrate 40 to yield a dielectric material form all the annular openings. Alternatively, the having a lower coefficient of thermal expansion openings could alternatively be formed, in the re- than the substrate. flowed layer, through patterning. Specifically, a The arrangement shown in FIG. 2 can be man- suitable barrier would be placed over the pad, the ufactured using any of the three methods: co-fired pad would then be re-flowed and thereafter the pad and co-fired braze restricting layer, co-fired barrier would be removed. If the viscosity of the pad and post-fired braze restricting layer, and post- molten braze restricting layer was sufficiently high, fired pad and post-fired braze restricting layer. then the barrier would not be needed. Additionally, to increase the strength of the pad and lower its a. Co-fired Pad and Co-fired Braze Restricting Lay- composite thermal expansion coefficient, a metal, er - such as molybdenum or kovar, having a low coefficient of thermal expansion could also be post-fired Here, pad 60 can be any metallic pad suitable onto the pad. for a desired dielectric substrate and can be fabricated using a suitable metamc paste which con- c. Post-fired Pad and Post-fired Braze Restricting tains appropriate well-known adhesives or other Layer - metals which will co-sinter with the substrate. Braze restricting layer 50 is implemented using To apply post-fired pads to the dielectric - a "green sheet" made of the same dielectric ma- (MLC) substrate, a number of "green sheet" ele- terial as that of the dielectric substrate or prefer- ments are first laminated together and then fired to ably, for a compressive effect, a dielectric material form the dielectric substrate. Thereafter, the pads having a lower thermal expansion coefficient' than are applied to the substrate using any thin film the material comprising the dielectric substrate. All technique (such as ion plating, magnetron sputter- the openings, e.g. opening 55, in braze restricting ing and the like) which provides high adhesion and layer 50 are formed by appropriately punching out low stress between the pad and a the dielectric the green sheet. Once all these openings are substrate. Inasmuch as the metal used in the pads formed, then they are all filled with a fugitive paste does not need to co-sinter with the ceramic in the prior to laminating this dielectric layer with other dielectric substrate, the pad can be fabricated out "green sheet" layers comprising dielectric sub- of a variety of alloys such as Ti/Cu/Ni, Ti/Cu/Mo/Ni, strate 40 (in the case of an MLC substrate). There- Cr/Cu/Ni, Cr/Cu/Mo/Ni and many other metallic after, the laminated structure is sintered. The fu- combinations. The post-fired braze restricting layer gitive paste maintains the annular shape of each is then fabricated using any of the techniques opening during lamination and subsequent burnout described above in connection with the co-fired of the MLC substrate during sintering. pad and post-fired braze restricting layer. Although a preferred embodiment has been b. Co-fired Pad and Post-fired Braze Restricting shown and described above, many other embodi- Layer - ments containing the teachings of the present invention can be readily devised by those skilled in The pad is essentially the same as that de- the art. scribed above in connection with the co-fired pad and co-fired braze restricting layer. However, here, the entire surface of the dielectric substrate, includ- ing the pads, is coated with dielectric material, 1. Method for brazing interconnect pins to metallic which forms the braze restricting layer, after the pads formed on a brittle dielectric substrate, char- dielectric substrate has been fired (sintered). This acterized by the steps of: dielectric material is then selectively etched away or patterned to produce the openings. forming a dielectric layer (50) on the surface (43) of Specifically, braze restricting layer 50 can be said substrate (40), said dielectric layer comprising manufactured using any one of several techniques. a plurality of openings (55) wherein each of said First, this layer can be sputtered quartz or a glass openings being concentrically aligned with a cor- layer that has been previosuly deposited, over sur- responding pad (60) and is smaller than the cor- face 43 of dielectric substrate 40, by chemical responding pad so as to overlap a closed periph- vapor deposition and thereafter etched back from eral portion thereof and thereby define a closed the center of the pads to form all the openings. The wall (58) to contain brazing material; seating a head (72) of an interconnect pin (70) in a said dielectric substrate (40) and a layer of conduc- corresponding one of said openings; and tive paste to define said pattern of pads (60); bonding the head of said pin to said pad by braz- sintering said laminated structure; ing material contained within said closed wall. 2. The method of claim 1 further characterized by depositing the dielectric material over a surface of the step of fabricating said dielectric layer (50) said laminated structure to define said dielectric from a dielectric material having a lower coefficient layer (50); and of thermal expansion than that of said dielectric substrate. removing selected portions of said dielectric layer, 3. The method of claim 2 characterized in that subsequent to sintering, in order to define said plurality of openings. the forming step includes the step of aligning the 7. The method of claim 6 characterized in that dielectric layer with the dielectric substrate such that each of said openings overlaps a peripheral said selected portions are removed either through annularly shaped portion of each corresponding patterning or etching. pad and exposes a central portion of each cor- 8. The method of claim 7 characterized in that responding pad. 4. The method of claim 3 characterized in that the said forming step further includes the step of post- forming step comprises the steps of: firing a protective metallic layer onto said pad (60) prior to brazing said pin (70) to said pad. forming a multi-layered laminated structure com- 9. The method of claim 8 characterized in that prising at least a first green sheet element to form said dielectric substrate (40), a layer of conductive said forming step further includes the step of post- paste defining said pads (60), and a second green firing a metallic layer onto said pad (60) wherein sheet element impregnated with said dielectric ma- said metallic layer has a lower thermal coefficient terial to form said dielectric layer (50); and of expansion that that of said pad. 10. The method of claim 3 characterised in that the sintering said laminated structure. forming step comprises the steps of: 5.The method of claim 4 characterised in that the forming step includes the steps of: firing at least a first green sheet element to form said dielectric substrate(40), removing material from said second green sheet to form said plurality of openings (55); and applying said pattern of pads (60) over said first fired green sheet element filling said openings with a fugitive paste prior to laminating said second green sheet to another lay- depositing the dielectric material over said pattern er and sintering said laminated structure. and said first fired green sheet element to define 6. The method of claim 3 characterized by includ- said dielectric layer (50); and ing the steps of: removing selected portions of said dielectric layer, forming a multi-layered laminated structure com- in order to define said plurality of openings (55). prising at least a first green sheet element to form