l,1DMAaCE OaFOO G3GiJA400O a

2Kx8 2048 x 8- STATIC RAM

• Fully Static Operation; No Clocks, • Two Line Control, CE Controls Power- Refresh or Latches Down, OE Controls Output Buffers — Eliminates Bus Contention ■ EPROM Compatible Pinout ■ 150 ns Maximum Access Time

■ Industry Standard 244-Pin Package ■ Auto Power-Down

The Intel® 2K x 8 is a 16,384-bit static RAM organized as 2048 words by 8 . It employs fully static cir- cuitry which eliminates the need for cllocks, refresh, or address setup and hold times. The auto power- down feature cuts power consumption when the device is disabled. The 24-pin industry standard pinout allows easy upgrades to 4Kx 8 static RAMs and compatibility to the 2732 4K x 8 and 2764 8K x 8 EPROMs in 28-pin sites. The two line control simplifies decoding and elimi- nates any possibility of bus contention.

TRUTH TABLE PIN NAMES Z`€ WE 51 MODE OUTPUT POWER A,—A,, ADDRESS INPUTS H X X NOT SELECT HIGH Z STANDBY Cr. CHIP ENABLE L H H SELECTED HIGH Z ACTIVE SE OUTPUT ENABLE L H L READ ACTIVE ACTIVE WE WRITE ENABLE L L X WRITE HIGH Z ACTIVE D,—D, INPUT/OUTPUT Vcc POWER (+5V) GND GROUND

LOGIC PIN SYMBOL CONFIGURATION COMPATIBLE PINOUTS 2Kx8 SRAM 2Kx8 SRAM 4Kx8 SRAM 8Kx8 SRAM 8Kx8 EPROM

NC C1 ~8 ] Vcc NC 28 Vcc Vno 28 Ao Do A, NC C 2 27 ] WE A„ 27 WE A1x 27 A, A, [ 3 NC A, AZ D, 24 Vcc 26 ] 26 NC A, 26 23 A 4 25 ] A, 4 25 As As s C As 25 Aa As A, 02 As 2 A, AsC 5 24 ] A, As 24 A, A, 5 24 A, A, 212231 E A, 6 23 A, As 03 C ] A„ A, 23 Al, 6 23 A, 20 ~ A, [ 7 22 ]0 -E A, 22 A, 7 22 As D, A, 19 A, Az C 8 21 7 A,o A, 21 A,o A, 8 21 A, A, 18 Z€ A, C 9 20 ]-CE A, 20 A, 9 20 Ds As A, 17 D, Ao C 10 19 3D, A, 19 D, A, 10 19 D, 16 DoC 11 18 ] D, D, A, D, Ds 18 De Do 11 18 A„ D, 15 Ds D,C 12 17 ] D, D, 17 Ds D, 12 17 D7 D, 14 D, D,C 13 16 ] D, D, 16 D, D, 13 16 OE WE CE GND 13 03 GNDC 14 15 ] D, GND 15 D, GND 14 15

Figure 1. 2K x 8 Pin Diagram Figure 2. Compatible Pinouts

1-72 intele ADVANCE OGJG'OO G°3RE4O oOM

4Kx8 4096 x 8-BIT STATIC RAM

• Fully Static Operation; No Clocks, • Two Line Control, a Controls Power- Refresh or Latches Down, OE Controls Output Buffers — ■ EPROM Compatible JEDEC Standard Eliminates Bus Contention Pinout ■ ■ 2764 Compatible 28-Pin Package — 150 ns Maximum Access Time Allows Easy Upgrade To 8K x 8 SRAM Without Jumpers ■ Auto Power-Down

The Intel® 4K x 8 is a 32,768-bit static RAM organized as 4096 words by 8 bits. It employs fully static cir- cuitry which eliminates the need for clocks, refresh, or address setup and hold times. The auto power- down feature cuts power consumption when the device is disabled. The 28-pin JEDEC standard pinout allows easy upgrades to 8Kx8 static RAMs and compatibility to the 2732 4K x 8 and 2764 8K x 8 EPROMs — without jumpers. The two line control simplifies decoding and eliminates any possibility of bus contention.

TRUTH TABLE PIN NAMES aE WE CE MODE OUTPUT POWER Ail—An I ADDRESS INPUTS H X X NOT SELECT HIGH Z STANDBY Cr. CHIP ENABLE L H H SELECTED HIGH Z ACTIVE S€ OUTPUT ENABLE L H L READ ACTIVE ACTIVE WE WRITE ENABLE L L X WRITE HIGH Z ACTIVE D,—D, DATA INPUT/OUTPUT V,, POWER (+5V) OND GROUND

LOGIC PIN COMPATIBLE PINOUTS SYMBOL CONFIGURATION 4K x8 4Kx8 SRAM 8Kx8 SRAM 8Kx8 EPROM

A, NC 1 28 Vcc NCC 1 287Vcc VPoC 1 28 p Vcc A, Do NC 2 27 M/É A„C2 27]WE Ai C 2 27 P—G—M A, D, A, 3 26 NC A, C3 26]NC A, C3 26 ]NC A, A, 4 25 ~4 A,C 4 257A. A, C 4 25 DA, A. D, A, 5 24 A, A,C5 24]A, A5 C 5 24 7 A, As D, A, 6 23 A, C 6 23 ] A„ A. C 6 23 7A„ A, 7 22 A, C 7 22 DOE A, C 22 A, 7 7aE D. A, 8 21 C8 21 DA,, 8 21 A, A,o Az A, C A,o A, 13 20 t'E A,C9 207C€ A, C 9 20 7 ~ A. D5 Ao 10 19 D, Ao C 10 19 —10 Ao C 10 19 7D, A, 0, 11 D, 18 D, Do C 11 18 7 D, Do C 11 18 ] D, A,o D, 12 17 0, D, C 12 17 DD, D, C 12 17 D D5 A,, D, D, 13 16 04 D, C 13 16 D D. D, C 13 16 7D. OE WE CE GND 14 15 D, GNDC 14 15 DD, GNDC 14 15 7 D, Y Y Y Figure 1. 4K x 8-Pin Diagram Figure 2. Compatible Pinouts

1-73

intel® 2732 32K (4K x 8) UV ERASABLE PROM

• Fast Access Time: • Output Enable for MCS•85TM and MCS• — 390 ns Max. 2732.4 86TM Compatibility — 450 ns Max. 2732 — 550 ns Max. 2732.6 • Low Power Dissipation: • industry Standard Pinout — JEDEC — 150 mA Max. Active Current Approved — 35 mA Max Standby Current

• Pin Compatible to Intel's EPROM Family: 2716, 2732A, 2764 • Single +5V ± 5% Power Supply

The Intel® 2732 is a 32,768-bit erasable and electrically programmable read-only memory (EPROM). The 2732 operates from a single 5-volt power supply, has a standby mode, and features an output enable control. The total pro- gramming time for all bits is three and a half minutes. The 2732 family with an access time up to 390 ns enhances microprocessor system performance. This family, in conjunction with the 250 ns 2732A family, solves the problem of WAIT states due to slow memories. An important 2732 feature is the separate output control, Output Enable (OE) from the Chip Enable control (CE). The OE control eliminates bus contention in multiiple bus microprocessor systems. Intel's Application Note AP-72 describes the microprocessor system implementation of the OE and CE controls on Intel's 2716 and 2732 EPROMs. AP-72 is available from Intel's Literature Department. The 2732 has a standby mode which reduces the power dissipation without increasing access time. The maximum active current is 150 mA, while the maximum standby current is only 35 mA, a 75% savings. The standby mode is achieved by applying a TTL-high signal to the CI_' input.

2732 2732A MODE SELECTION PIN CONFIGURATION PIN CONFIGURATION PINS CE OE/Vpp VCC OUTPUTS (9-11,13-171 24 24 VCc MODE 081 (201 124) 23 23 Al Read VIL VIL +5 DOUT 22 22 Ag Standby VIH Don't Care +5 High Z 21 21 A11 20 20 ÓE/Vrr Program VIL Vpp +5 DIN 19 113 4,0 Program Verify VIL VIL +5 DOUT 18 10 CÉ Program Inhibit VIH Vpp +5 High Z 17 17 g 16 16 O, 15 1!i Oy 14 14 04 13 13 o, DIAGRAM

DATA OUTPUTS VCC ~ 00-07 GND 1 ' 1 ' .. VPP c—

OE ~ VC AND PIN NAMES ~ CE LOGIC OUTPUT BUFFERS

V.GATING A0-A,, ADDRESSES A0-A71 DECODER —. ADDRESS CHIP ENABLE a INPUTS 01 OUTPUT ENABLE 32,768-BIT ECODERX 00 -07 OUTPUTS CELL MATRIX

2-7 2732

PROGRAMMING The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section. ABSOLUTE MAXIMUM RATINGS* 'COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause Temperature Under Bias -10°C to +80°C permanent damage to the device. This is a stress rating only and functional Storage Temperature -65°C to +125°C operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. All Input or Output Voltages with Exposure to absolute maximum rating conditions for extended periods Respect to Ground +6V to -0.3V may affect device reliability.

D.C. AND OPERATING CHARACTERISTICS TA = 0°C to 70° C, Vcc = +5V ± 5%

READ OPERATION

Limits Symbol Parameter Min. Typ.l11 Max. Unit Conditions lu1 Input Load Current (except /Vpp) 10 µA VIN = 5.25V lu2 611/Vpp Input Load Current 10 µA VIN = 5.25V

ILO Output Leakage Current 10 µA VOUT = 5.25V Icci Vcc Current (Standby) 15 35 mA CE = VIH, OE = VIL Icc2 Vcc Current (Active) 85 150 mA OE = CE = VIL VIL Input Low Voltage -0.1 0.8 V VIH Input High Voltage 2.0 Vcc+1 V VOL Output Low Voltage 0.45 V IOL = 2.1 mA VOH Output High Voltage 2.4 V IOH = -400µA

Note: 1. Typical values are for TA == 25°C and nominal supply voltages

TYPICAL CHARACTERISTICS

Icc CURRENT a TO OUTPUT DELAY (tcE) CE TO OUTPUT DELAY (tcE) VS. TEMPERATURE VS. CAPACITANCE VS. TEMPERATURE 100 500 500 90

80 400 400 70 _ II° IVE CURRENT) a v._ 60 — VCC = 5V 300 á ▪ 50 '300 S' 40 ▪ 1 200 (STANDBY CURRENT) 30 Cc) CE = 100 200 20 Vcc = 5V 100

10 Tq= 25C V 0 10 20 30 40 50 60 70 BO 1030 100 200 300 400 500 600 700 800 00 10 20 30 40 50 60 70 80 C1 TEMPERATURE (°C) (pF) TEMPERATURE PC(

2-8 2732

A.C. CHARACTERISTICS

TA = 0°C to 70°C, VCC = +5V ± 5%

2732.4 Limits 2732 Limits 2732.6 Limits (ns) (ns) (ns) Symbol Parameter Test Min. Max. Min. Max. Min. Max. Conditions

tAcc Address to Output Delay 390 450 550 CE= OE= VIL

tcE CE to Output Delay 390 450 550 OE= VIL toE Output Enable to Output Delay 120 120 120 CÉ=VIL

tDF Output Enable High to Output Float 0 100 0 100 0 100 CE= VIL

Output Hold from Addresses, CE or o 0 0 CE= CE = VIL OE, Whichever Occurred First

CAPACITANCE 01 TA= 25°C, f=1MHz A.C. TEST CONDITIONS

Symbol Parameter 'Typ. Max. Unit Conditions Output Load: 1 TTL gate and CL = 100pF CINt Input Capacitance Input Rise and Fall Times: <_ 2Ons Except OE/Vpp 4 6 pF VIN = OV Input Pulse Levels: 0.8V to 2.2V Timing Measurement Reference Level: CIN2 OE/Vpp Input Inputs 1V and 2V Capacitance 20 pF VIN = OV Outputs 0.8V and 2V COUT Output Capacitance 12 pF VOUT = OV

A.C. WAVEFORMS [2]

ADDRESSES ADDRESSES VALID

CE 1

tDF ]a]

tOH lot

HIGH 2 HIGH Z OUTPUT VALID OUTPUT

NOTES: 1. THIS PARAMETER IS ONLY SAMPLED AND IS NOT 100% TESTED. 2. ALL TIMES SHOWN IN PARENTHESES ARE MINIMUM TIMES AND ARE NSEC UNLESS OTHERWISE SPECIFIED. 3. OE MAY BE DELAYED UP TO tAC-- tOE AFTER THE FALLING EDGE OF CE WITHOUT IMPACT ON tACC. 4. tDF IS SPECIFIED FROM a OR CE, WHICHEVER OCCURS FIRST.

2-9 2732

ERASURE CHARACTERISTICS puts are in a high impedance state, independent of the OT input. The erasure characteristics of the 2732 are such that erasure begins to occur when exposed to light with Output OR-Tieing wavelengths shorter than approximately 4000 Angstroms Because EPROMs are usually used in larger memory ar- (A). It should be noted that sunlight and certain types of rays, Intel has provided a 2 line control function that ac- fluorescent lamps have wavelengths in the 3000-4000A commodates this use of multiple memory connections. range. Data show that constant exposure to room level The two line control function allows for:. fluorescent lighting could erase the typical 2732 in a) the lowest possible memory power dissipation, and approximately 3 years, while it would take approximately 1 b) complete assurance that output bus contention will week to cause erasure when exposed to direct sunlight. If not occur. the 2732 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels are To most efficiently use these two control lines, it is available from Intel which should be placed over the 2732 recommended that CE (pin 18) be decoded and used as window to prevent unintentional erasure. the primary device selecting function, while CE (pin 20) be made a common connection to all devices in the ar- The recommended erasure procedure (see Data Catalog) ray and connected to the READ line from the system for the 2732 is exposure to shortwave ultraviolet light control bus. This assures that all deselected memory which has a wavelength of 2537 Angstroms (9). The into• devices are in their low power standby mode and that grated dose (I.e., UV intensity X exposure time) for the output pins are only active when data is desired from a particular memory device. erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 PROGRAMMING (See Programming Instruction Section minutes using an ultraviolet lamp with a 12000 1.4W/cm2 for Waveforms.) power rating. The 2732 should be placed within 1 inch of Initially, and after each erasure, all bits of the 2732 are in the lamp tubes during erasure. Some lamps have a filter the "1" state. Data is introduced by selectively program- on their tubes which should be removed before erasure. ming "0's" into the desired bit locations. Although only "0's" will be programmed, both "l's" and "0's" can be DEVICE OPERATION presented in the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure. The five modes of operation of the 2732 are listed in Table 1. A single 5V power supply is required in the read The 2732 is in the programming mode when the OE/Vpp mode. All inputs are TTL levels except for UE/Vpp during input is at 25V. It is required that a 0.1µF capacitor be programming. In the program mode the OE/Vpp input is placed across OE/Vpp and ground to suppress spurious pulsed from a TTL level to 25V. voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data TABLE 1. Mode Selection inputs are TTL. When the address and data are stable, a 50msec, active PINS CE oEMpp Vcc OUTPUTS MODE . (18) (20) (24) (9.11,13.17) low, TTL program pulse is applied to the CE input. A program pulse must be applied at each address location to Read +5 VIL VIL DOUT be programmed. You can program any location at any Standby VIN Don't Care +5 High Z time — either individually, sequentially, or at random. The Program VIL Vpp +5 DIN program pulse has a maximum width of 55msec. The 2732 must not be programmed with a DC signal applied to the Program Verity VIL VIL +5 DUUT CE input. Program Inhibit VIN Vpp +5 High Z Programming of multiple 2732s in parallel with the same data can be easily accomplished due to the simplicity of Read Mode the programming requirements. Like inputs of the paralleled 2732s may be connected together when they The 2732 has two control functions, both of which must are programmed with the same data. A low level TTL pulse be logically satisfied in order to obtain data at the out- applied to the CE input programs the paralleled 2732s. puts. Chip Enable (GTE) is the power control and should be used for device selection. Output Enable (OE) is the Program Inhibit output control and should be used to gate data to the Programming of multiple 2732s in parallel with different output pins, independent of device selection. Assuming data is also easily accomplished. Except for CE, all like that addresses are stable, address access time (tAcc) is inputs (including OE) of the parallel 2732s may be equal to the delay from CE to output (tCE). Data is common. A TTL level program pulse applied to a 2732's available at the outputs 12Ons (tOE) after the falling edge CE input with OE/Vpp at 25V will program that 2732. A of OE assuming that CE has been low and addresses high level CE input inhibits the other 2732s from being have been stable for at least tACC — toE• programmed. Standby Mode Program Verify The 2732 has a standby mode which reduces the active A verify should be performed on the programmed bits to power current by 75%, from 150mA to 35mA. The 2732 determine that they were correctly programmed. The is placed in the standby mode by applying a TTL high verify is accomplished with OE/Vpp and CE at VIL. Data signal to the CE input. When in standby mode, the out- should be verified toy after the falling edge of CE.

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