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L7: Memory Basics and Timing L7:L7: MemoryMemory BasicsBasics andand TimingTiming Acknowledgement: Nathan Ickes, Rex Min J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective” Prentice Hall, 2003 (Chapter 10) L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1 MemoryMemory ClassificationClassification && MetricsMetrics Non-Volatile Read-Write Memory Read-Write Read-Only Memory Memory (ROM) Random Non-Random EPROM Access Access Mask-Programmed E2PROM SRAM FIFO FLASH DRAM LIFO Key Design Metrics: 1. Memory Density (number of bits/µm2) and Size 2. Access Time (time to read or write) and Throughput 3. Power Dissipation L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2 MemoryMemory ArrayArray ArchitectureArchitecture 2L-K Bit Line Storage Cell Row Decode AK 2L-K row AK+1 Word Line by Mx2K column AL-1 cell array K M.2 Sense Amps/Driver Amplify swing to rail-to-rail amplitude A 0 Column Decode AK-1 Selects appropriate word (i.e., multiplexor) Input-Output (M bits) L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3 LatchLatch andand RegisterRegister BasedBased MemoryMemory Positive Latch Negative Latch Register Memory Negative latch Positive latch D Q D Q D Q Q 0 1 M Q Q G G D D 1 0 Clk CLK CLK Works fine for small memory blocks (e.g., small register files) Inefficient in area for large memories – density is the key metric in large memory circuits How do we minimize cell size? L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4 StaticStatic RAMRAM (SRAM)(SRAM) CellCell (The(The 66--TT Cell)Cell) BL BL WL WL WL VDD M2 M4 Q Q M Q Q M5 6 M1 M3 Write: set BL and BL to 0 and VDD or VDD and 0 and then enable WL (i.e., BL BL set to VDD) Read: Charge BL and BL to VDD and then enable WL (i.e., set to VDD). Sense a small change in BL or BL State held by cross-coupled inverters (M1-M4) Retains state as long as power supply turned on Feedback must be overdriven to write into the memory L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 5 InteractingInteracting withwith aa MemoryMemory DeviceDevice Write enable Address Row Decoder Write Tri-state Driver Logic Chip Enable Pins … enable Memory Matrix Data Pins in out If enable=0 … Read out = Z Logic Write enable Sense Amps/Drivers Output Enable If enable =1 Column Decoder out = in Output Enable gates the chip’s tristate driver Address pins drive row and column decoders Write Enable sets the memory’s read/write mode Data pins are bidirectional and shared by reads and writes Chip Enable/Chip Select acts as a “master switch” L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6 MCM6264CMCM6264C 8k8k xx 88 StaticStatic RAMRAM Same (bidirectional) data bus On the outside: used for reading and writing 13 Address Chip Enables (E1 and E2) E1 must be low and E2 must be Chip Enables E1 high to enable the chip E2 8 MCM6264C Data Write Enable (W) Write Enable W DQ[7:0] When low (and chip is enabled), the values on the data bus are Output Enable G written to the location selected by the address bus Output Enable (G) On the inside: When low (and chip is enabled), the data bus is driven with the value of the selected memory A2 DQ[7:0] location A3 E1 A4 … Memory matrix E2 A5 256 rows A7 32 Column A8 A9 Row Decoder A11 W … G Pinout Sense Amps/Drivers Column Decoder A0 A1 A6 A12 A10 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7 ReadingReading anan AsynchronousAsynchronous SRAMSRAM Address Address Valid Access time (from address valid) E1 Access time (from enable low) G Bus enable time Bus tristate time (Tristate) Data Data Valid E2 assumed high (enabled), W =1 (read mode) Read cycle begins when all enable signals (E1, E2, G) are active Data is valid after read access time Access time is indicated by full part number: MCM6264CP-12 Æ 12ns Data bus is tristated shortly after G or E1 goes high L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 8 AddressAddress ControlledControlled ReadsReads Address Address 1 Address 2 Address 3 Access time (from address valid) Contamination time E1 G Bus enable time Bus tristate time Data Data 1 Data 2 Data 3 E2 assumed high (enabled), W =1 (read mode) Can perform multiple reads without disabling chip Data bus follows address bus, after some delay L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 9 WritingWriting toto AsynchronousAsynchronous SRAMSRAM Address Address Valid Address setup time Address hold time E1 Write pulse width W Data setup time Data hold time Data Data Valid E2 and G are held high Data latched when W or E1 goes high (or E2 goes low) Data must be stable at this time Address must be stable before W goes low Write waveforms are more important than read waveforms Glitches to address can cause writes to random addresses! L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 10 SampleSample MemoryMemory InterfaceInterface LogicLogic Write cycle Read cycle Clock/E1 G W Address Address for write Address for read Data Data for write Data read Write occurs here, Data can be Drive data bus only when E1 goes high latched here when clock is low VCC FPGA E2 Ensures address and ext_chip_enable Clock E1 are stable for writes ext_write_enable Control W SRAM FSM ext_output_enable Prevents bus (write, read, reset) G contention int_data Write data D Q Data[7:0] Minimum clock period Read data Q D is twice memory ext_data Address Address[12:0] access time D Q ext_address L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 11 MultiMulti--CycleCycle Read/WriteRead/Write (less(less aggressive,aggressive, recommendedrecommended timing)timing) clk V DD E2 E1 W_b Control W FSM G_b SRAM (write, read, reset) G data_oen data_sample int_data write_data D Q Data[7:0] read_data Q D ext_data address_load address Address[12:0] D Q ext_address write completes read, address is stable address/data stable Data latched into FPGA write states 1-3 read states 1-3 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12 SimulationSimulation fromfrom PreviousPrevious SlideSlide write completes read, address is stable address/data stable Data latched into FPGA write states 1-3 read states 1-3 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 13 VerilogVerilog forfor SimpleSimple MultiMulti--CycleCycle AccessAccess module memtest (clk, reset, G_b, W_b, address, ext_address, write_data, read_data, ext_data, read, // Sequential always block for state assignment write, state, data_oen, address_load, data_sample); input clk, reset, read, write; assign ext_data = data_oen ? int_data : 8'hz; output G_b, W_b; output [12:0] ext_address; always @ (posedge clk) reg [12:0] ext_address; begin input [12:0] address; if (!reset) state <= IDLE; input [7:0] write_data; else state <= next; output [7:0] read_data; reg [7:0] read_data; G_b <= G_b_int; inout [7:0] ext_data; W_b <= W_b_int; reg [7:0] int_data; data_oen <= data_oen_int; output [2:0] state; if (address_load) ext_address <= address; reg [2:0] state, next; if (data_sample) read_data <= ext_data; output data_oen, address_load, data_sample; if (address_load) int_data <= write_data; reg G_b, W_b, G_b_int, W_b_int, address_load, data_oen, data_oen_int, data_sample; end wire [7:0] ext_data; // note that address_load and data_sample are not parameter IDLE = 0; // registered signals parameter write1 = 1; parameter write2 = 2; parameter write3 = 3; parameter read1 = 4; parameter read2 = 5; parameter read3 = 6; 1/4 2/4 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 14 VerilogVerilog forfor SimpleSimple MultiMulti--CycleCycle AccessAccess // Combinational always block for next-state // computation write2: begin always @ (state or read or write) begin next = write3; W_b_int = 1; data_oen_int =1; G_b_int = 1; Setup the end address_load = 0; write3: begin data_oen_int = 0; Default values next = IDLE; data_sample = 0; data_oen_int = 0; case (state) end IDLE: if (write) begin read1: begin next = write1; next = read2; address_load = 1; G_b_int = 0; data_oen_int = 1; data_sample = 1; end end else if (read) begin read2: begin next = read1; next = read3; address_load = 1; end G_b_int = 0; read3: begin end next = IDLE; else next = IDLE; end write1: begin default: next = IDLE; next = write2; endcase W_b_int = 0; end data_oen_int =1; endmodule end 3/4 4/4 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15 TestingTesting MemoriesMemories Common device problems Bad locations: rare for individual locations to be bad Slow (out-of-spec) timing(s): access incorrect data or violates setup/hold Catastrophic device failure: e.g., ESD Missing wire-bonds/devices (!): possible with automated assembly Transient Failures: Alpha particles, power supply glitch Common board problems Stuck-at-Faults: a pin shorted to VDD or GND Open Circuit Fault: connections unintentionally left out Open or shorted address wires: causes data to be written to incorrect locations Open or shorted control wires: generally renders memory completely inoperable Approach Device problems generally affect the entire chip, almost any test will detect them Writing (and reading back) many different data patterns can detect data bus problems Writing unique data to every location and then reading it back can detect address bus problems L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 16 AnAn ApproachApproach An idea that almost works 1. Write 0 to location 0 2. Read location 0, compare value read with 0 3. Write 1 to location 1 4. Read location 1, compare value read with 1 5. … What is
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