L7:L7: MemoryMemory BasicsBasics andand TimingTiming

Acknowledgement: Nathan Ickes, Rex Min

J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective” Prentice Hall, 2003 (Chapter 10)

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1 MemoryMemory ClassificationClassification && MetricsMetrics

Non-Volatile Read-Write Memory Read-Write Read-Only Memory Memory (ROM)

Random Non-Random EPROM Access Access Mask-Programmed E2PROM

SRAM FIFO FLASH

DRAM LIFO

Key Design Metrics: 1. Memory Density (number of bits/µm2) and Size 2. Access Time (time to read or write) and Throughput 3. Power Dissipation

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2 MemoryMemory ArrayArray ArchitectureArchitecture

2L-K Bit Line Storage Cell Row Decode

AK 2L-K row AK+1 Word Line by Mx2K column

AL-1 cell array

K M.2 Sense Amps/Driver Amplify swing to rail-to-rail amplitude

A 0 Column Decode AK-1 Selects appropriate word (i.e., multiplexor) Input-Output (M bits)

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3 LatchLatch andand RegisterRegister BasedBased MemoryMemory

Positive Latch Negative Latch Register Memory

Negative latch Positive latch D Q D Q D Q Q 0 1 M Q Q G G D D 1 0 Clk

CLK CLK

ƒ Works fine for small memory blocks (e.g., small register files) ƒ Inefficient in area for large memories – density is the key metric in large memory circuits

How do we minimize cell size?

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4 StaticStatic RAMRAM (SRAM)(SRAM) CellCell (The(The 66--TT Cell)Cell)

BL BL WL WL WL VDD M2 M4 Q Q M Q Q M5 6

M1 M3 Write: set BL and BL to 0 and VDD or VDD and 0 and then enable WL (i.e., BL BL set to VDD) Read: Charge BL and BL to VDD and then enable WL (i.e., set to VDD). Sense a small change in BL or BL ƒ State held by cross-coupled inverters (M1-M4) ƒ Retains state as long as power supply turned on ƒ Feedback must be overdriven to write into the memory

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 5 InteractingInteracting withwith aa MemoryMemory DeviceDevice

Write enable Address Row Decoder Write Tri-state Driver Logic Chip Enable

Pins … enable Memory Matrix Data Pins in out If enable=0 … Read out = Z Logic Write enable Sense Amps/Drivers Output Enable If enable =1 Column Decoder out = in

„ Output Enable gates the chip’s tristate driver „ Address pins drive row and column decoders „ Write Enable sets the memory’s read/write mode „ Data pins are bidirectional and shared by reads and writes „ Chip Enable/Chip Select acts as a “master switch”

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6 MCM6264CMCM6264C 8k8k xx 88 StaticStatic RAMRAM

„ Same (bidirectional) data bus On the outside: used for reading and writing 13 Address „ Chip Enables (E1 and E2) † E1 must be low and E2 must be Chip Enables E1 high to enable the chip E2 8 MCM6264C Data „ Write Enable (W) Write Enable W DQ[7:0] † When low (and chip is enabled), the values on the data bus are Output Enable G written to the location selected by the address bus „ Output Enable (G) On the inside: † When low (and chip is enabled), the data bus is driven with the value of the selected memory A2 DQ[7:0] location A3 E1

A4 … Memory matrix E2 A5 256 rows A7 32 Column A8 A9 Row Decoder A11 W … G Pinout Sense Amps/Drivers Column Decoder A0 A1 A6 A12 A10

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7 ReadingReading anan AsynchronousAsynchronous SRAMSRAM

Address Address Valid Access time (from address valid) E1 Access time (from enable low) G Bus enable time Bus tristate time (Tristate) Data Data Valid E2 assumed high (enabled), W =1 (read mode)

„ Read cycle begins when all enable signals (E1, E2, G) are active „ Data is valid after read access time † Access time is indicated by full part number: MCM6264CP-12 Æ 12ns „ Data bus is tristated shortly after G or E1 goes high

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 8 AddressAddress ControlledControlled ReadsReads

Address Address 1 Address 2 Address 3 Access time (from address valid) Contamination time E1

G Bus enable time Bus tristate time Data Data 1 Data 2 Data 3

E2 assumed high (enabled), W =1 (read mode)

„ Can perform multiple reads without disabling chip

„ Data bus follows address bus, after some delay

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 9 WritingWriting toto AsynchronousAsynchronous SRAMSRAM

Address Address Valid Address setup time Address hold time E1 Write pulse width W Data setup time Data hold time Data Data Valid E2 and G are held high

„ Data latched when W or E1 goes high (or E2 goes low) † Data must be stable at this time † Address must be stable before W goes low

„ Write waveforms are more important than read waveforms † Glitches to address can cause writes to random addresses!

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 10 SampleSample MemoryMemory InterfaceInterface LogicLogic

Write cycle Read cycle Clock/E1 G W Address Address for write Address for read Data Data for write Data read

Write occurs here, Data can be „ Drive data bus only when E1 goes high latched here when clock is low VCC FPGA E2 † Ensures address and ext_chip_enable Clock E1 are stable for writes ext_write_enable Control W SRAM FSM ext_output_enable † Prevents bus (write, read, reset) G contention int_data Write data D Q Data[7:0] † Minimum clock period Read data Q D is twice memory ext_data Address Address[12:0] access time D Q ext_address

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 11 MultiMulti--CycleCycle Read/WriteRead/Write (less(less aggressive,aggressive, recommendedrecommended timing)timing)

clk V DD E2 E1 W_b Control W FSM G_b SRAM (write, read, reset) G data_oen data_sample int_data write_data D Q Data[7:0]

read_data Q D ext_data address_load address Address[12:0] D Q ext_address

write completes read, address is stable

address/data stable Data latched into FPGA

write states 1-3 read states 1-3

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12 SimulationSimulation fromfrom PreviousPrevious SlideSlide

write completes

read, address is stable

address/data stable Data latched into FPGA

write states 1-3 read states 1-3

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 13 VerilogVerilog forfor SimpleSimple MultiMulti--CycleCycle AccessAccess

module memtest (clk, reset, G_b, W_b, address, ext_address, write_data, read_data, ext_data, read, // Sequential always block for state assignment write, state, data_oen, address_load, data_sample); input clk, reset, read, write; assign ext_data = data_oen ? int_data : 8'hz; output G_b, W_b; output [12:0] ext_address; always @ (posedge clk) reg [12:0] ext_address; begin input [12:0] address; if (!reset) state <= IDLE; input [7:0] write_data; else state <= next; output [7:0] read_data; reg [7:0] read_data; G_b <= G_b_int; inout [7:0] ext_data; W_b <= W_b_int; reg [7:0] int_data; data_oen <= data_oen_int; output [2:0] state; if (address_load) ext_address <= address; reg [2:0] state, next; if (data_sample) read_data <= ext_data; output data_oen, address_load, data_sample; if (address_load) int_data <= write_data; reg G_b, W_b, G_b_int, W_b_int, address_load, data_oen, data_oen_int, data_sample; end

wire [7:0] ext_data; // note that address_load and data_sample are not parameter IDLE = 0; // registered signals parameter write1 = 1; parameter write2 = 2; parameter write3 = 3; parameter read1 = 4; parameter read2 = 5; parameter read3 = 6; 1/4 2/4

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 14 VerilogVerilog forfor SimpleSimple MultiMulti--CycleCycle AccessAccess

// Combinational always block for next-state // computation write2: begin always @ (state or read or write) begin next = write3; W_b_int = 1; data_oen_int =1; G_b_int = 1; Setup the end address_load = 0; write3: begin data_oen_int = 0; Default values next = IDLE; data_sample = 0; data_oen_int = 0; case (state) end IDLE: if (write) begin read1: begin next = write1; next = read2; address_load = 1; G_b_int = 0; data_oen_int = 1; data_sample = 1; end end else if (read) begin read2: begin next = read1; next = read3; address_load = 1; end G_b_int = 0; read3: begin end next = IDLE; else next = IDLE; end write1: begin default: next = IDLE; next = write2; endcase W_b_int = 0; end data_oen_int =1; endmodule end 3/4 4/4

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15 TestingTesting MemoriesMemories

„ Common device problems † Bad locations: rare for individual locations to be bad † Slow (out-of-spec) timing(s): access incorrect data or violates setup/hold † Catastrophic device failure: e.g., ESD † Missing wire-bonds/devices (!): possible with automated assembly † Transient Failures: Alpha particles, power supply glitch „ Common board problems

† Stuck-at-Faults: a pin shorted to VDD or GND † Open Circuit Fault: connections unintentionally left out † Open or shorted address wires: causes data to be written to incorrect locations † Open or shorted control wires: generally renders memory completely inoperable „ Approach † Device problems generally affect the entire chip, almost any test will detect them † Writing (and reading back) many different data patterns can detect data bus problems † Writing unique data to every location and then reading it back can detect address bus problems

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 16 AnAn ApproachApproach

„ An idea that almost works 1. Write 0 to location 0 2. Read location 0, compare value read with 0 3. Write 1 to location 1 4. Read location 1, compare value read with 1 5. … „ What is the problem? † Suppose the memory was missing (or output enable was disconnected)

Address 0123

Data 0 0 1 1 2 2 2 2

Control WriteRead Write Read Write Read Write Read

Data bus is undriven but wire capacitance briefly maintains the bus state: memory appears to be ok!

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 17 AA SimpleSimple MemoryMemory TesterTester

„ Write to all locations, then read back all • Write 0 to address 0 locations • Write 1 to address 1 • … † Separates read/write to the same location • Write (n mod 256) to address n with reads/writes of different data to • Read address 0, compare with 0 different locations • Read address 1, compare with 1 • … † (both data and address busses are changed • Read address n, compare with (n mod 256) between read and write to same location) To normal • write 8-LSB’s of address memory interface to location specified by address • Increment counter Comparator = last address?

• Reset counter Counter Enable memory • Read address • Report success test SRAM

Matched? = last address? • Compare data read with 8-LSB’s • Report failure of Does not Data Control

• Increment counter match? Address

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 18 SynchronousSynchronous SRAMSRAM MemoriesMemories

„ Clocking provides input synchronization and encourages more reliable operation at high speeds

Row Decoder Write Write Enable Logic Chip Enable

… Memory Address matrix Pins Data Pins … Read Sense Amps/Drivers Logic Output Enable Column Decoder

long “flow-through” combinational path creates difference between read and high CLK-Q delay write timings creates wasted cycles (“wait states”)

R1 R2 W3 R4 W5 CE WE CLK

Address A1 A2 A3 A4 A5

Data Q1 Q2 D3 Q4 D5

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 19 ZBTZBT EliminatesEliminates thethe WaitWait StateState

„ The wait state occurs because: † On a read, data is available after the clock edge † On a write, data is set up before the clock edge

„ ZBT (“zero bus turnaround”) memories change the rules for writes † On a write, data is set up after the clock edge (so that it is read on the following edge) † Result: no wait states, higher memory throughput

R1 R2 W3 R4 W5 CE WE CLK Address A1 A2 A3 A4 A5

Data Q1 Q2 D3 Q4 D5

Write to A3 Data D3 Write to A5 Data D5 requested loaded requested loaded

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 20 PipeliningPipelining AllowsAllows FasterFaster CLKCLK

„ Pipeline the memory by registering its output † Good: Greatly reduces CLK-Q delay, allows higher clock (more throughput) † Bad: Introduces an extra cycle before data is available (more latency) ZBT Row Decoder Write Write Enable Logic Chip Enable

… Memory Address matrix As an example, see Pins Data Pins the CY7C147X ZBT … Read Synchronous SRAM Sense Amps/Drivers Logic Output Enable Column Decoder

pipeliningpipelining registerregister

R1 R2 W3 R4 W5 CE WE CLK

Address A1 A2 A3 A4 A5

Q Q D Q D Data one-cycle 1 2 3 4 5 latency... (ZBT write to A3)(ZBT write to A5)

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 21 EPROMEPROM CellCell –– TheThe FloatingFloating GateGate TransistorTransistor

20 V 0 V 5 V [Rabaey03]

10 V 5 V 20 V 5 V 0 V 2.5 V 5 V

S D S D S D

Avalanche injection Removing programming Programming results in voltage leaves charge trapped higher VT.

EPROM Cell

Courtesy Intel

This is a non-volatile memory (retains state when supply turned off)

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 22 InteractingInteracting withwith FlashFlash andand (E)EPROM(E)EPROM

„ Reading from flash or (E)EPROM is the same as reading from SRAM

„ Vpp: input for programming voltage (12V) † EPROM: Vpp is supplied by programming machine † Modern flash/EEPROM devices generate 12V using an on-chip charge pump

„ EPROM lacks a write enable † Not in-system programmable (must use a special programming machine)

„ For flash and EEPROM, write sequence is controlled by an internal FSM † Writes to device are used to send signals to the FSM † Although the same signals are used, one can’t write to flash/EEPROM in the same manner as SRAM

Flash/EEPROM block diagram Vcc (5V)

Address Data

Charge Chip Enable pump EPROM omits Output Enable Programming FSM, charge voltage (12V) pump, and write Write Enable FSM enable

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 23 DynamicDynamic RAMRAM (DRAM)(DRAM) CellCell

BL WL DRAM uses Write "1" Read "1" WL Special Capacitor M1 CS Structures X GND

V BL DD

CBL VDD/2 VDD/2 Cell Plate Si sensing [Rabaey03] Capacitor Insulator Refilling Poly

To Write: set Bit Line (BL) to 0 or VDD Storage Node Poly Si Substrate & enable Word Line (WL) (i.e., set to VDD ) 2nd Field Oxide To Read: set Bit Line (BL) to VDD /2 & enable Word Line (i.e., set it to VDD ) ƒ DRAM relies on charge stored in a capacitor to hold state ƒ Found in all high density memories (one bit/transistor) ƒ Must be “refreshed” or state will be lost – high overhead

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 24 AsynchronousAsynchronous DRAMDRAM OperationOperation

Address Row Col

RAS

CAS

(Tristate) Data Q (data from RAM)

WE set high/low before asserting CAS

RAS-before-CAS CAS-before-RAS for a read or write for a refresh (Row and column addresses taken on falling edges of RAS and CAS)

„ Clever manipulation of RAS and CAS after reads/writes provide more efficient modes: early-write, read-write, hidden-refresh, etc. (See datasheets for details)

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 25 AddressingAddressing withwith MemoryMemory MapsMaps

„ ‘138 is a 3-to-8 decoder † Maps 16-bit address space to 8, SRAM 1 SRAM 2 EPROM 13-bit segments † Upper 3-bits of address determine which chip is enabled „ SRAM-like interface is often Address[12:0] Data[7:0] ~G Address[12:0] Data[7:0] Data[7:0] Address[12:0] ~G ~W ~E1 ~W ~E1 used for peripherals ~G ~E1 Output Enable † Referred to as “memory mapped” peripherals Write Enable [12:0] [12:0] [12:0] Address[15:0] 15 C Y7 14 B Y6 Memory Map 13 A Y5 0xFFFF Y4 [2:0] EPROM ~G2B Y3 0xE000 ~G2A Y2 0xDFFF Bus Enable G1 ‘138 Y1 SRAM 2 Y0 0xC000 +5V 0xBFFF SRAM 1 Data[7:0] 0xA000 0x9FFF ~G ~W ~E1 0x2000 Analog 0x1FFF ADC ADC Data[7:0] Input 0x0000 Address[2:0]

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 26 KeyKey MessagesMessages onon MemoryMemory DevicesDevices

„ SRAM vs. DRAM † SRAM holds state as long as power supply is turned on. DRAM must be “refreshed” – results in more complicated control † DRAM has much higher density, but requires special capacitor technology. † FPGA usually implemented in a standard digital process technology and uses SRAM technology „ Non-Volatile Memory † Fast Read, but very slow write (EPROM must be removed from the system for programming!) † Holds state even if the power supply is turned off „ Memory Internals † Has quite a bit of analog circuits internally -- pay particular attention to noise and PCB board integration „ Device details † Don’t worry about them, wait until 6.012 or 6.374

L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 27