The Next IC Design Methodology Transition Is Long Overdue Michael Meredith and Steve Svoboda, Open SystemC Initiative

From the mid-1970s to the late 1990s, these two factors Anyone with a tapeout deadline looming combined to raise designer productivity from 4-5 gates/ knows how finishing a new chip design keeps getting day up to 500-1000 gates/day. Figure 1 shows a slow harder and harder. Fortunately, newly standardized high- increase in productivity that can be attributed to reuse and level languages like SystemC™, along with modern high- incremental tool improvements. This is followed by a jump level synthesis (HLS) tools are offering designers a way to in productivity at the point where the level of abstraction escape the RTL “productivity jailhouse.” moved up to RTL. Since about 2005, however, IC designer productivity has leveled off. Current RTL-based design and Since the turn of the century, the semiconductor industry verification methodologies have reached their limits. has been suffering slowing engineering productivity growth. While during that period the semiconductor Fortunately, new methodologies have started to emerge industry has seen major sales growth, as semiconductors and be adopted by the industry. As of now, at least 24 (over continue working their way into almost every facet of 50%) of the world’s leading semiconductor companies have modern life, with very few exceptions profitability has begun adoption and deployment of high-level synthesis. remained stagnant or even declined. HLS is the fastest-growing segment of EDA. Leading companies such as ST Micro, Sony, and NEC are already Moore’s Law is often cited as the key driver and enabler of taping-out designs using HLS. The chairman of NEC said the semiconductor industry, and indeed the ability of the as early as 2002 that their internal HLS tool was used in semiconductor manufacturing technologies to produce all digital designs as their mainstream design flow. More smaller transistors has very closely followed the smooth recently, it was mentioned at a DAC panel last year that curve that it predicts. What is missing from this analysis is Sony had successfully completed more than 30 designs that in order for electronics companies to use these transistors to develop products, the ability of design engineers to create designs needs to increase at the Evolution of IC Design same rate as the ability to manufacture Semiconductor Industry transistors grows. 10000 “Golden Age” Transaction / Behavior ~15+ years (High-level Synthesis) Two factors have contributed to this growth of design productivity. The first is 1000 ULSI reuse. Very early on, engineers learned ~ 5 years Register-transfer level (Logic Synthesis) to reuse standardized transistor-layouts 100 (“gates”), which were then combined VLSI 0.65µ mainstream ~500k-1m gates/IP into “cells” and “macrocells” enabling Gate level standard-cell ASIC design. These cells/ 10 (Schematic Capture) macrocells were later combined into 0.5µ mainstream SSI, MSI, LSI “cores” and “subsystems” to create ~500k-1m gates/IC 1 Transistor modern SoCs. Designs Original (gates/day) Productivity, level (SPICE)

The second contributor to design 1970’s 1980 1990 2000 2010 productivity is the development of tools that allow the designer to work at a higher level of abstraction. At some point Figure 1. This chart shows the evolution of IC design from in the early 1990s the industry made a transition from the mid-1970s to the present. The mid-1980s to 2000 was the mainly designing semiconductors using schematics at the semiconductor industry’s period of fastest innovation, growth, and gate level to mainly using logic synthesis at the register- value-creation. This was driven in very large part by an over-100x transfer level (RTL). increase in designer productivity. involving over 200 engineers using HLS. ST Micro has The fundamental differences between C++ and SystemC- been quoted by public sources as saying that 90% of all based high-level synthesis flows arise out of the nature of their new digital IP development is done by starting at a the two languages themselves: behavior level of abstraction and using high-level synthesis to create RTL. • C++ is a sequential programming language with a single flow of control. Modeling at higher levels of abstraction (such as TLM) SystemC is a hardware design language with explicit has been used for years by companies to accelerate support for modeling multiple independent entities simulation and verification of complex systems. Just as that coordinate their activities by communicating the development of RTL logic synthesis in the early 1990s through channels. led to a transition from using HDLs for verification only to broad adoption of HDLs in the RTL design flow, the • With C++ you execute a program. development of high-level synthesis is moving companies toward TLM-driven design at a high level of abstraction. With SystemC you simulate hardware behavior. • C++ supports the specification and validation of a single Moving to a higher abstraction level offers opportunities finite state machine. for new kinds of reuse not possible at the register-transfer level. Microarchitecture decisions that bind an IP block SystemC supports the specification and validation of to a particular application are handled automatically by multiple interacting FSMs. high-level synthesis. Instead of having to specify what each part of the hardware is doing in every clock-cycle, In simple dataflow cases, such as where each part of the designer instead focuses on defining the functionality an algorithm consumes a fixed number of values and that meets the requirements and the range of latency and produces a fixed number of values, it is feasible to write throughput constraints on that functionality. Instead of the overall system as a set of C++ subroutines and write a having to specify communication between blocks in terms main program that calls the subroutines in a fixed order. of cycle-by-cycle signal behavior, designers can apply reuse The outputs of one subroutine are used as inputs to to these interfaces, encapsulating the detailed protocol in later-executing subroutines. This is often used as a kind terms of pre-defined “transactions.” With a modern high- of “simulation” of the interoperation of the subroutines. level synthesis tool, the designer can then automatically Other cases—such as those where the number of values explore the area, speed, and power of a broad range of produced and consumed by each entity is dependent on microarchitectures that meet those constraints, selecting the data being processed, or where there are feedback the one that fits the intended application based on loops in the dataflow—are more difficult to model and performance, power, and chip area considerations. The verify using only a sequential language like C++. automatically-created RTL is used for logic synthesis and for the rest of the standard implementation flow. In this way, There are number of flaws in this approach. The greatest design teams can adopt and deploy high-level synthesis of these is that it is entirely non-standard and means that without disturbing their proven RTL-based procedures and the IP product of the engineer’s effort can only be used tool flows. with a single vendor’s toolset. Another great flaw is that the “simulation” that is performed by executing the C++ program does not in fact verify the correct concurrent Which Input Language Is Most execution of the implied modules. It also fails to verify the Suitable for HLS? signal-level behavior that will be required in hardware to implement the data communication and synchronization Quite a few different languages have been proposed for protocols. use by design teams using HLS. The first HLS tools used RTL languages such as and VHDL. These languages SystemC is the accepted industry standard for modeling were unsatisfactory for a number of reasons including their concurrent hardware modules in C++. It provides a set of inadequacy as true high-level languages and the need for concurrent simulation semantics in a way that is supported language translation from the C algorithm specification and by multiple vendors. Because the simulation semantics the implementation language. Most recent approaches are standard and conform to the commonly accepted have tried to stay closer to the C algorithm by using a hardware design paradigm, it is possible to co-simulate variation of C or a C++ library to add hardware capabilities these SystemC modules along with modules written in to the C language. Synthesis variations on the C language Verilog, VHDL, or SystemVerilog. Indeed, all of the major include HardwareC, Handel-C, Cyber-C, Bach C, and HDL simulator vendors provide a co-simulation capability Mentor’s Algorithmic C. Each of these uses C extensions or for SystemC modules. C++ libraries to address hardware requirements. systems companies, this working group has released a draft C++ Constructs document for public review that describes this subset. C++ data types User-defined data types - Integer C++ data types - structures - Operators on C++ integer - classes The subset includes a broad range of C++ and SystemC data types - inheritance constructs consistent with the HLS requirement that - operator overloading it must be possible to determine the structure of the Control structures Templates hardware statically at the time the HLS tool processes the - if/else constructs - template classes design source code. Consequently, a C++ construct (such - for() and while() loops - template functions - switch() constructs as a template) is included in the subset, while dynamic - references resolution of virtual functions is not. Figures 2 and 3 - statically-determined pointers summarize the included constructs.

Figure 2. This table lists C++ constructs included in the draft synthesizable subset. Expanding from HLS Toward

SystemC Constructs an Integrated Design and

Modules & Threads Ports Data Types Verification Flow

SC_MODULE sc_in<> bool Working at a higher level vs. lower level of abstraction can be compared to cutting wood with a chain-saw vs. with sc_int<> SC_CTHREAD sc_out<> an axe. It can be a lot more productive, but can be also a sc_uint<> lot more dangerous if you don’t verify what you’re doing sc_bigint<> SC_METHOD sc_export<> sc_biguint<> at every step. New, advanced verification methodologies will also need to be developed to enable broad adoption Figure 3. This table lists SystemC constructs included in the draft of HLS. Leading EDA companies today are investing synthesizable subset. significantly to develop advanced tools and methodologies enabling comprehensive verification at abstraction levels above RTL. One key is to develop approaches for verifying Since 2005, the IEEE 1666™ standard for SystemC has high-level/TLM IP that optimally map different verification provided standard syntax and semantics for representing tasks to each level of abstraction in order to minimize the hardware using a good high-level language that is overall time and effort spent. The basic elements of this appropriate for synthesis. Beyond this, industry agreement new approach are illustrated in Figure 4. on a standard synthesizable subset is needed to facilitate portability of synthesizable hardware designs between SystemC synthesis tools. This work is currently underway in TLM Design and Algorithm Verification the Open SystemC Initiative’s TLM Verification Flow (OSCI) synthesis working group. Methodology 1 Verification Functional Verification

The OSCI SystemC C/C++, SC, Simulink HLS 2 Simulation Verification Synthesis Draft Implementation Verification High-Level Model Algorithm DUT SystemC TLM 10000 Simulation 3 Standard Verification The OSCI synthesis working Environment group (SWG) is focused on RTL HW 1000 Simulation Accel defining a meaningful minimum synthesizable subset of SystemC Environment to establish a baseline for Reuse Algorithm 100 transportability of SystemC to Architecture design code between HLS tools Environment Reuse Architecture to while allowing for continued Micro-architecture 10 innovation by SystemC-based HLS tool developers. With the participation of more than one Figure 4. TLM design and verification flow. 1 dozen EDA, semiconductor, and Designs Original (gates/day) Productivity,

1970’s 1980 1990 2000 2010

Use Cases

Software Software Architectural Hardware development performance analysis verification

Coding Styles, Abstractions Loosely-timed

Approximately-timed

Mechanisms

Blocking Generic Non-blocking DMI Quantum Sockets Extensions Phases interface payload interface Design teams that have adopted these new methodologies see improvements ~3x more efficient/compact designs 5-10x faster simulation/debug in the quality of the circuits they can produce, the speed of their simulation and RTL Verilog 100 (human) debug cycles, and in overall productivity, 1000 75 as shown in Figure 5. 800

50 600

400 Simulation time (%) Simulation Conclusion Lines of Code 25

200 SystemC (for synthesis) Just as design teams in the early 1990s 0 C/C++ (algorithm) SystemC RTL Verilog 0 adopted logic synthesis and RTL design (synthesizable) (human) to productively take advantage of the larger circuits made possible by new Equal/better QoR than manual 10x+ productivity increases semiconductor manufacturing techniques, today’s design teams are adopting high- 1000000 level synthesis using the SystemC standard SystemC to RTL FPGA to ASIC 100000 in 10 days retargeting in to take advantage of the number of vs. Manual RTL 1-2 days vs. transistors available at 90nm and below. 10000 in 3 months 2-3 weeks (manual) Given that the RTL design abstraction has 1000 HLS generated HLS generated RTL size (gates) RTL size been in use for more than 15 years, it is no 100

10 longer possible to consider it the leading- 10 100 1000 10000 100000 1000000 edge design approach that is required Best manual RTL size (gates) I/F controller IP Motion-detection IP to bring us new, exciting consumer and industrial electronic products. Fortunately the move to the next level of abstraction Figure 5. Benefits of new TLM design and verification methodology using high-level synthesis in SystemC is well underway, vs. traditional RTL (summary of actual data obtained in 2007-2008 and is demonstrating that it can deliver the required by early adopters). productivity.

Michael Meredith

Steve Svoboda

Michael Meredith is Vice President of Technical Marketing for Forte Design Systems and is President of OSCI. Steve Svoboda is Technical Marketing Director of System Design & Open SystemC Initiative Verification for and serves as the Defining and Advancing SystemC Standards Cadence representative to the OSCI Promotions Group. www.SystemC.org February 2010