CSCI 4717/5717 Computer Architecture Buses – Common
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PCI20EX PCI Express (Pcie)
PCI20EX PCI Express (PCIe) Bus ARCNET® Network Interface Modules INSTALLATION GUIDE INTRODUCTION The PCI20EX series of ARCNET network interface modules (NIMs) links PCI Express (PCIe) bus compatible computers with the ARCNET local area network (LAN). Since most PC motherboards have migrated from the legacy PCI and PCI-X Bus, a PCI Express style NIM is required. The PCI20EX series is compliant to the PCI Express Card Electromechanical Specification Revision 2.0 and both standard height and low-profile brackets are provided. The PCI Express interface allows for jumperless configuration and Plug and Play operation. The module operates with either an NDIS driver or a null stack driver in a Windows® environment. The PCI20EX incorporates the COM20022 ARCNET controller chip with enhanced features over the earlier generation ARCNET chips. New features include command chaining, sequential access to internal RAM, duplicate node ID detection and variable data rates up to 10 Mbps. Bus contention problems are minimized since the module’s interrupt and I/O base address are assigned through Plug and Play. The PCI20EX exploits the new features of the COM20022 which includes 10 Mbps communications utilizing the various EIA-485 transceiver options. Each PCI20EX module has two LEDs on the board for monitoring network operation and bus access to the module. It is equipped with an 8 position, general purpose DIP switch typically used to assign the ARCNET node address. Ultimately, the node address is configured via software so the DIP switch can also indicate user-defined functions such as data rate, cable interface, or master/slave status of the system. -
Datasheet for Onenand Power Ramp and Stabilization Times and for Onenand Boot Copy Times
TMS320DM365 www.ti.com SPRS457E–MARCH 2009–REVISED JUNE 2011 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – Support for 32-Bit and 16-Bit – High-Performance Digital Media (Thumb® Mode) Instruction Sets System-on-Chip (DMSoC) – DSP Instruction Extensions and Single Cycle – Up to 300-MHz ARM926EJ-S Clock Rate MAC – Two Video Image Co-processors – ARM® Jazelle® Technology (HDVICP, MJCP) Engines – Embedded ICE-RT Logic for Real-Time – Supports a Range of Encode, Decode, and Debug Video Quality Operations • ARM9 Memory Architecture – Video Processing Subsystem – 16K-Byte Instruction Cache • HW Face Detect Engine – 8K-Byte Data Cache • Resize Engine from 1/16x to 8x – 32K-Byte RAM • 16-Bit Parallel AFE (Analog Front-End) – 16K-Byte ROM Interface Up to 120 MHz – Little Endian • 4:2:2 (8-/16-bit) Interface • Two Video Image Co-processors • 8-/16-bit YCC and Up to 24-Bit RGB888 (HDVICP, MJCP) Engines Digital Output – Support a Range of Encode and Decode • 3 DACs for HD Analog Video Output Operations, up to D1 on 216-MHz device and • Hardware On-Screen Display (OSD) up to 720p on the 270- and 300-MHz parts – Capable of 720p 30fps H.264 video – H.264, MPEG4, MPEG2, MJPEG, JPEG, processing WMV9/VC1 Note: 216-MHz is only capable of D1 • Video Processing Subsystem processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO, -
VME for Experiments Chairman: Junsei Chiba (KEK)
KEK Report 89-26 March 1990 D PROCEEDINGS of SYMPOSIUM on Data Acquisition and Processing for Next Generation Experiments 9 -10 March 1989 KEK, Tsukuba Edited by H. FUJII, J. CHIBA and Y. WATASE NATIONAL LABORATORY FOR HIGH ENERGY PHYSICS PROCEEDINGS of SYMPOSIUM on Data Acquisition and Processing for Next Generation Experiments 9 - 10 March 1989 KEK, Tsukuba Edited H. Fiflii, J. Chiba andY. Watase i National Laboratory for High Energy Physics, 1990 KEK Reports are available from: Technical Infonnation&Libraiy National Laboratory for High Energy Physics 1-1 Oho, Tsukuba-shi Ibaraki-ken, 305 JAPAN Phone: 0298-64-1171 Telex: 3652-534 (Domestic) (0)3652-534 (International) Fax: 0298-64-4604 Cable: KEKOHO Foreword This symposium has been organized to foresee the next generation of data acquisition and processing system in high energy physics and nuclear physics experiments. The recent revolutionary progress in the semiconductor and computer technologies is giving us an oppotunity to extend our idea on the experiments. The high density electronics of LSI technology provides an ideal front-end electronics such as readout circuits for silicon strip detector and multi-anode phototubes as well as wire chambers. The VLSI technology has advantages over the obsolite discrete one in the various aspects ; reduction of noise, small propagation delay, lower power dissipation, small space for the installation, improvement of the system reliability and maintenability. The small sized front-end electronics will be mounted just on the detector and the digital data might be transfered off the detector to the computer room with optical fiber data transmission lines. Then, a monster of bandies of signal cables might disappear from the experimental area. -
Wishbone Bus Architecture – a Survey and Comparison
International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON Mohandeep Sharma 1 and Dilip Kumar 2 1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India [email protected] 2ACS - Division, Center for Development of Advanced Computing, Mohali, India [email protected] ABSTRACT The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. KEYWORDS SoC buses, WISHBONE Bus, WISHBONE Interface 1. INTRODUCTION The introduction and advancement of multimillion-gate chips technology with new levels of integration in the form of the system-on-chip (SoC) design has brought a revolution in the modern electronics industry. With the evolution of shrinking process technologies and increasing design sizes [1], manufacturers are integrating increasing numbers of components on a chip. -
VICTORIA UNIVERSITY of WELLINGTON Te Whare W
VICTORIAUNIVERSITYOFWELLINGTON Te Whare Wananga¯ o te UpokooteIkaaM¯ aui¯ School of Engineering and Computer Science Te Kura Matai¯ Pukaha,¯ Purorohiko¯ PO Box 600 Tel: +64 4 463 5341 Wellington Fax: +64 4 463 5045 New Zealand Internet: offi[email protected] Development of an IoT System for Environmental Monitoring Jolon Behrent Supervisor: James Quilty Submitted in partial fulfilment of the requirements for Bachelor of Engineering with Honours. Abstract The Greater Wellington Regional Council currently uses data loggers to mon- itor the environment. These loggers and accompanying software are provided by a single supplier which effectively locks the Council into using them for all monitoring. The Council wants to develop a low-cost, open-source Internet of Things solution with a connection to a cloud platform. This report looks at the development of a successful proof-of-concept device capable of reading from sensors and transmitting the data to Azure. Contents 1 Introduction and Background 1 1.1 Introduction . .1 1.1.1 Objective . .1 1.1.2 Overview . .2 1.2 Background . .2 1.2.1 HyQuest Solutions Data Loggers . .2 1.2.2 SDI-12 . .3 2 Design 5 2.1 Design Constraints . .5 2.1.1 Power Consumption . .5 2.1.2 Size . .6 2.1.3 Cost . .6 2.2 Microcontroller Selection . .6 2.3 Modem Selection . .7 2.4 Capacitor Selection . .8 2.5 Regulator Selection . .9 2.6 PCB Design . .9 2.7 Enabling Local Wireless Connection . 10 2.7.1 Reed Switches . 11 2.7.2 Hall Effect Sensors . 11 2.8 SDI-12 Design . -
GS3 Greenhouse Sensor 2365 NE Hopkins Ct / Pullman, WA 99163 USA Volumetric Water Content, Electrical Conductivity, and Temperature
GS3 Greenhouse Sensor 2365 NE Hopkins Ct / Pullman, WA 99163 USA Volumetric Water Content, Electrical Conductivity, and Temperature APPLICATIONS DESCRIPTION . Greenhouse substrate monitoring. The Decagon GS3 sensor is an accurate tool for . Volumetric water content measurement. monitoring electrical conductivity, volumetric water . Soil/Substrate water balance. content, and temperature in soil and soilless . Irrigation management. substrates. The GS3 determines volumetric water . Electrical Conductivity measurement. content (VWC) by measuring the dielectric constant . Salt management. (εa) of the medium using capacitance / frequency- . Fertilizer movement. domain technology. The sensor uses a 70 MHz . Soil/Substrate temperature measurement. frequency, which minimizes textural and salinity . Modeling processes that are affected by effects, making the GS3 accurate in most soilless temperature. substrates. The GS3 measures temperature using an onboard thermistor, and electrical conductivity using a stainless steel electrode array. ADVANTAGES For a more detailed description of how this sensor . Digital sensor communicates three makes measurements, refer to the User Manual. measurements over a serial interface. 2-probe EC measurement. Robust thermistor for accurate temperature AUDIENCE measurements. Decagon provides the information in this integrators . Low input voltage requirements. guide to help GS3 customers establish . Low power design supports battery-operated communication between these sensors and their data loggers. data acquisition equipment or field data loggers. Robust epoxy encapsulation and stainless Customers using data loggers that support SDI-12 steel needles to resist corrosive environments. sensor communications should consult the user's . Supports SDI-12 or DDI-Serial 1-wire serial manual for their data logger. These sensors are fully communications protocols. integrated into Decagon's system of plug-and-play . -
Parallel I/O Interface
從微算機原理到系統 宋開泰教授 國立交通大學電機與控制系 工程五館 EE709 Phone:5731865(校內分機:31865) E-mail:[email protected] URL:http://isci.cn.nctu.edu.tw Microcomputer Systems & Lab Microcomputer bus 1 Digital Signal Waveform 1 0 Single-signal waveform 1 0 Multiple-signal waveform Microcomputer Systems & Lab Microcomputer bus 2 Read Timing for External Code Memory Microcomputer Systems & Lab Microcomputer bus 3 Microcomputer BUS • A bus is a set of conducting wires interconnecting the CPU, memory, and I/O devices. • There are three types of bus: Address bus, Data bus and Control bus. There are also utilities in a bus system, such as Vcc and ground lines. • To drive a bus, a bus driver is needed. To receive data from the bus, a bus receiver is needed. The bus driver and bus receiver can be combined to form a bus transceiver. Microcomputer Systems & Lab Microcomputer bus 4 Connecting to a bus • A bus should be driven by no more than one device at any time. Otherwise, bus contention will occur. When bus contention occurs, the devices that are involved in bus contention could be damaged. • A device is disconnected from the bus when the driver-enable and receiver-enable signals are deasserted. When the enable signal is deasserted, the output of the driver or the receiver is in a high-impedance state in which no current flow into or out the device involved. Microcomputer Systems & Lab Microcomputer bus 5 Interconnecting the CPU, Memory, and I/O Devices Memory unit 8 bits 1,048,575 Clock generator 64 672,356 Address Instruction pointer (IP) System address bus Selector/ z System 6 memory 672 356 decoder 5 4 Instruction register 3 2 64 1 Location 0 INC AX Instruction decoder Internal databus System control bus Arithmetic logic unit Memory read Memory write Accumulator I/O write I/O read I/O write I/O read I/O write 26+1=27 System data bus Video monitor I/O devices: Printer keyboard Floppy disk drive z General-purpose registers I/O port Selector/decoder Central processing unit (CPU) Microcomputer Systems & Lab Microcomputer bus 6 System Bus • Internal data bus is used to classify a microprocessor. -
STD 7000 7802 6800 Processor Card USER's MANUAL
STD 7000 7802 6800 Processor Card USER'S MANUAL .: . o o NOTICE The information in this document is provided for reference only. Pro-Log does not assume any liability arising 0 out of the application or use of the information or products described herein. This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Pro-Log, nor the rights of others. Printed in U.S.A. Copyright© 1981 by Pro-Log Corporation, Monterey, CA 93940. All rights reserved. However, any part of this document may be reproduced with Pro-Log Corporation cited as the source. STD 7000 7802 6800 Processor Card USER'S MANUAL o 2/82 aa uailUIlAIMIMIlIdIHI6IJYIWiiIIi&&iIlWiHiiiii1WGL&lil1l4JI£jj1, __ oGllI{fldf4IL1lfI[.JIilJI!1U1l4J!;;QI!IMf&bnUMliMJi1illldOif kLCH1LJ _"- _,L JLJ L _11 ____ ,BAGLin _ ta, _ h 'h41J1P i4I A;.u 4 FOREWORD This manual explains how to use Pro-Log's 7802 6800 Processor Card. It is structured to reflect the answers to o basic questions that you, the user, might ask yourself about the 7802. We welcome your suggestions on how we can improve our instructions. The 7802 is part of Pro-Log's Series 7000 STD BUS hardware. Our products are modular, and they are designed and built with second-sourced parts that are industry standards. They provide the industrial manager with the means of utilizing his own people to control the design, production, and maintenance of the company's products that use STD BUS hardware. -
Teros 21 Gen 1 Integrator Guide
18204-06 6.30.2020 TEROS 21 GEN 1 INTEGRATOR GUIDE SENSOR DESCRIPTION The TEROS 21 Soil Water Potential Sensor measures a wide range of soil water potentials without user maintenance. This dielectric water potential sensor can be packed into a hole, plugged into a data logger, and left to log water potential data. While the TEROS 21 sensor does not have the accuracy of tensiometers, its extended range makes this sensor ideal for measuring the water potential in natural systems or other drier systems where cavitation of tensiometers is a concern. The added temperature measurements can be used to determine approximate soil water potential in frozen soils. NOTE: The TEROS 21 measures the matric component of water potential. For more information on matric potential and the other components of water potential visit Defining water potential. APPLICATIONS • Deficit irrigation monitoring and control • Water potential monitoring in the vadose zone • Crop stress • Waste water drainage studies • Plant water availability • SDI-12 implementation ADVANTAGES • Three-wire sensor interface: power, ground, and data • Digital sensor communicates multiple measurements over a serial interface • Robust thermistor for accurate temperature measurements • Low-input voltage requirements • Low-power design supports battery-operated data loggers • Robust epoxy encapsulation resists corrosive environments • Supports SDI-12 or DDI serial communications protocols • Modern design optimized for low-cost sensing • Does not require a skilled operator • Can measure drier systems where tensiometer cavitation is a concern • Needs no user maintenance Figure 1 TEROS 21 sensor PURPOSE OF THIS GUIDE METER provides the information in this integrator guide to help TEROS 21 Soil Water Potential Sensor customers establish communication between these sensors and their data acquisition equipment or field data loggers. -
Stand-Alone VME Bus PC104 Bus ISA Bus STD Bus, & STD32
SYNCHRO / RESOLVER / LVDT CONVERTERS / BUS CARDS / AMPLIFIERS ABSOLUTE ENCODERS / READOUTS www.computerconversions.com 6 Dunton Court, East Northport, NY 11731 (631) 261-3300 Fax: (631) 261-3308 BUS CARD LEVEL PRODUCTS: SYNCHRO / RESOLVER / LVDT I/O VME Bus PC104 Bus Synchro / Resolver / LVDT I/O Synchro / Resolver / LVDT I/O Inputs: 1 - 12 Channels Synchro / Inputs: 1 - 4 Channels Synchro / Resolver, & 2-3 Wire LVDT Formats, Resolver and LVDT inputs with B-I-T & Forced Angle Self-Test Mods., B-I-T and Forced angle Self-Test, VBT True Wrap-Around Self-Test. Transformer Isolation opt.even on To 16 Bits, acc. 2', Tracking Rates to 60Hz. 200RPS. On-Board AC Reference Models., 16 Bits, 2.'acc.Tracking Rates options, Low cost Solid State and to 200RPS. Ultra Reliable and quick 100% Transformer Isolated models. delivery. AC Reference Supply Outputs: LVDT/ RVDT 1-12 Chan.s options. Synchro/Resolver: 1-4 Channels, high Outputs: 1-2 Channels Synchro / Res. power, output, drive 1.2 to 5VA, Low Low cost & Isol. mod's. 16 Bits, 1 - 4' Cost +/-12V. DC Bus powered & Reference acc. Loss detect, support for external Powered Converters. Transformer Isol ated Boosters upto 300VA. including I/O. Resolution: 14/16 Bits, accuracy 2'/ 4'. Disable control & BIT / Fault Report. All: A24/D16 6UH. Multispeed I/O, & All: No Violations, 0 - 70 and -40 - Mix & Match all I/O. 0 - 70 & -40 to +85C. +85C models. Software Demo w/ Conduction Cooled avail. PCI &COMPACT PCI ISA Bus All Plug and Play, with Software DLL's, PCI Same Selections 1-8 Inputs, Upto 4 High Power Output Channels, Transformer as on ISA Bus, CPCI Same Selections as on VME Bus. -
PC Hardware Contents
PC Hardware Contents 1 Computer hardware 1 1.1 Von Neumann architecture ...................................... 1 1.2 Sales .................................................. 1 1.3 Different systems ........................................... 2 1.3.1 Personal computer ...................................... 2 1.3.2 Mainframe computer ..................................... 3 1.3.3 Departmental computing ................................... 4 1.3.4 Supercomputer ........................................ 4 1.4 See also ................................................ 4 1.5 References ............................................... 4 1.6 External links ............................................. 4 2 Central processing unit 5 2.1 History ................................................. 5 2.1.1 Transistor and integrated circuit CPUs ............................ 6 2.1.2 Microprocessors ....................................... 7 2.2 Operation ............................................... 8 2.2.1 Fetch ............................................. 8 2.2.2 Decode ............................................ 8 2.2.3 Execute ............................................ 9 2.3 Design and implementation ...................................... 9 2.3.1 Control unit .......................................... 9 2.3.2 Arithmetic logic unit ..................................... 9 2.3.3 Integer range ......................................... 10 2.3.4 Clock rate ........................................... 10 2.3.5 Parallelism ......................................... -
Topic 10 Bus Architecture & Interconnects Introductions & Sources
Introductions & Sources X We will consider a number of issues related to bus architectures in digital systems. Topic 10 X Useful references: • “Bus Architecture of a System on a Chip with User-Configurable System Bus Architecture & Logic”, Steven Winegarden, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Interconnects VOL. 35, NO. 3, MARCH 2000, p425-433. • “AMBA: ENABLING REUSABLE ON-CHIP DESIGNS”, David Flynn, IEEE Micro, July/August 1997. Peter Cheung • AMBA™ Specification (Rev 2.0), ARM Ltd., 1999 Department of Electrical & Electronic Engineering • The CoreConnect Bus Architecture, IBM, Imperial College London http://www.chips.ibm.com/products/coreconnect • VSI Alliance Architecture Document, version 1.0, 1997. • Draft Chapter, “System-on-Chip”, Flynn & Luk URL: www.ee.imperial.ac.uk/pcheung/ E-mail: [email protected] PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 1 PYKC 6-Mar-08 E3.05 Digital System Design Topic 10 Slide 2 Basic concepts: Basic concepts: Bus basics: order and broadcast properties Cycles, messages and transactions X Communications on buses must be in strict order: serial nature of bus X Buses operate in units of cycles, Messages and transactions. • Cycles: A message requires a number of clock cycles to be sent from sender to receiver over the bus. • Message: These are logical unit of information. For example, a write message contains an address, control signals and the write data. • Transaction: A transaction consists of a sequence of messages which together form a transaction. For example, a memory read X It can broadcast a transaction – sending to multiple components simultaneously requires a memory read message and a reply with the requested data.