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CSCI 4717/5717 Buses – Common Characteristics Computer Architecture • Multiple devices communicating over a single set of wires • Only one device can talk at a time or the message is garbled Topic: Buses • Each line or wire of a bus can at any one time contain a single binary digit. Over time, however, a Reading: Stallings, Sections 3.4, 3.5, and 7.7 sequence of binary digits may be transferred • These lines may and often do send information in parallel • A computer system may contain a number of different buses CSCI 4717 – Computer Architecture Buses – Page 1 CSCI 4717 – Computer Architecture Buses – Page 2 Buses – Structure Buses – Structure (continued) • Serial versus parallel • Bus lines (parallel) • Around 50-100 lines although it's possible –Data to have as few as 3 or 4 –Address • Lines can be classified into one of four –Control groups – Power – Data lines • Bus lines (serial) – Address Lines – Data, address, and control are sequentially sent down single wire – Control Lines – There may be additional control lines –Power – Power CSCI 4717 – Computer Architecture Buses – Page 3 CSCI 4717 – Computer Architecture Buses – Page 4 Buses – Structure (continued) Bus Structure – Control lines • Because multiple devices communicate on a line, control is needed • Data Lines • Timing – Passes data back and forth • Typical lines include: – Number of lines represents width – Memory Read or Write – I/O Read or Write • Address lines – Transfer ACK – Designates location of source or destination – Bus request – Width of address bus specifies maximum – Bus grant memory capacity – Interrupt request – Interrupt acknowledgement – High order selects module and low order –Clock selects a location within the module – Reset CSCI 4717 – Computer Architecture Buses – Page 5 CSCI 4717 – Computer Architecture Buses – Page 6 1 Operation – Sending Data Operation – Requesting Data • Obtain the use of the bus • Obtain the use of the bus • Transfer the data via the bus • Transfer the data request via the bus • Possible acknowledgement • Wait for other module to send data • Possible acknowledgement CSCI 4717 – Computer Architecture Buses – Page 7 CSCI 4717 – Computer Architecture Buses – Page 8 Physical Implementations Classic Bus Arrangement • All components attached to bus (STD bus) • Parallel lines on circuit • Due to Moore's law, more and more functionality boards (ISA or PCI) exists on a single board, so major components • Ribbon cables (IDE) are now on same board or even the same chip CSCI 4717 – Computer Architecture Buses – Page 9 CSCI 4717 – Computer Architecture Buses – Page 10 Physical Implementations (continued) Single Bus Problems • Strip connectors on Lots of devices on one bus leads to: mother boards (PC104) • Physically long buses • External cabling (USB or – Propagation delays – Long data paths mean that co- ordination of bus use can adversely affect Firewire) performance – Reflections/termination problems • Aggregate data transfer approaches bus capacity • Slower devices dictate the maximum bus speed CSCI 4717 – Computer Architecture Buses – Page 11 CSCI 4717 – Computer Architecture Buses – Page 12 2 Multiple Buses Multiple Buses – Benefits • Most systems use multiple buses to overcome • Isolate processor-to-memory traffic from these problems I/O traffic • Requires bridge to buffer (FIFO) data due to • Support wider variety of interfaces differences in bus speeds • Processor has bus that connects as direct • Sometimes I/O devices also contain buffering interface to chip, then an expansion bus (FIFO) interface interfaces it to external devices (ISA) • Cache (if it exists) may act as the interface to system bus CSCI 4717 – Computer Architecture Buses – Page 13 CSCI 4717 – Computer Architecture Buses – Page 14 Expansion Bus Example Mezzanine Approach • Differences in I/O speeds demands separating devices. • Separate items that are high-speed and those that are not • An additional high-speed bus is added to communicate with the faster devices and also the slower expansion bus • Advantage is that high-speed devices are brought closer to processor CSCI 4717 – Computer Architecture Buses – Page 15 CSCI 4717 – Computer Architecture Buses – Page 16 Mezzanine Approach (continued) Pentium Example (Source: http://www.amd.com/us- en/assets/content_type/white_papers_and_tech_docs/21644.pdf) CSCI 4717 – Computer Architecture Buses – Page 17 CSCI 4717 – Computer Architecture Buses – Page 18 3 Bus Types Bus Types Dedicated vs. Time Multiplexed Physical Dedication • Dedicated – Physically separating buses and controlling – Separate data & address lines them with a "channel changer“ • Time multiplexed – Advantages – faster – Shared lines – Disadvantages – physically larger – Address valid or data valid control line – Advantage - fewer lines – Disadvantages • More complex control • Degradation of performance CSCI 4717 – Computer Architecture Buses – Page 19 CSCI 4717 – Computer Architecture Buses – Page 20 Bus Arbitration Centralised vs. Distributed Arbitration • Listening to the bus is not usually a • Centralised Arbitration problem – Single hardware device controlling bus • Talking on the bus is a problem – need access – Bus Controller/Arbiter arbitration to allow more than one module – May be part of CPU or separate to control the bus at one time • Distributed Arbitration • Arbitration may be centralised or – Each module may claim the bus distributed – Access control logic is on all modules – Modules work together to control bus CSCI 4717 – Computer Architecture Buses – Page 21 CSCI 4717 – Computer Architecture Buses – Page 22 Synchronous Bus Timing Bus Timing • Events determined by clock signals • Co-ordination of events on bus • Control Bus includes clock line • Synchronous – controlled by a clock • A single 1-0 cycle is a bus cycle • Asynchronous – timing is handled by well- • All devices can read clock line defined specifications, i.e., a response is delivered within a specified time after a • Usually sync on leading/rising edge request • Usually a single cycle for an event • Analogy – Orchestra conductor with baton • Usually stricter in terms of its timing requirements CSCI 4717 – Computer Architecture Buses – Page 23 CSCI 4717 – Computer Architecture Buses – Page 24 4 Synchronous Bus Timing Asynchronous Timing • Devices must have certain tolerances to provide responses to signal stimuli • More flexible allowing slower devices to communicate on same bus with faster devices. • Performance of faster devices, however, is limited to speed of bus CSCI 4717 – Computer Architecture Buses – Page 25 CSCI 4717 – Computer Architecture Buses – Page 26 Asynchronous Timing – Read Asynchronous Timing – Write CSCI 4717 – Computer Architecture Buses – Page 27 CSCI 4717 – Computer Architecture Buses – Page 28 Peripheral Component Bus Width Interconnection (PCI) Bus • Wider the bus the better the data transfer Brief history rate or the wider the addressable memory • Original PC came out with 8-bit ISA bus which space was slow, but had enormous amount of existing equipment. • Serial “width” is determined by • For AT, IBM expanded ISA bus to 16-bit by length/duration of frame adding connector • Many PC board manufacturers started making higher speed, proprietary buses • Intel released the patents to its PCI and this soon took over as the standard CSCI 4717 – Computer Architecture Buses – Page 29 CSCI 4717 – Computer Architecture Buses – Page 30 5 PCI Bus (continued) Required PCI Bus Lines (Table 3.3) Brief list of PCI 2.2 characteristics • Systems lines – clock and reset • General purpose • Address & Data • Mezzanine or peripheral bus – 32 time multiplexed lines for address/data • Supports single- and multi-processor – Parity lines architectures • Interface Control • 32 or 64 bit – multiplexed address and data – Hand shaking lines between bus controller and • Synchronous timing devices – Selects devices • Centralized arbitration (requires bus controller) – Allows devices to indicates when they are • 49 mandatory lines (see Table 3.3) ready CSCI 4717 – Computer Architecture Buses – Page 31 CSCI 4717 – Computer Architecture Buses – Page 32 Required PCI Bus Lines Optional PCI Bus Lines (continued) There are 51 optional PCI 2.2 bus lines • Arbitration • Interrupt lines – Not shared – Not shared – Direct connection to PCI bus arbiter – Multiple lines for multiple interrupts on a single device • Cache support • Error lines – parity and critical/system • 64-bit Bus Extension – Additional 32 lines – Time multiplexed – 2 lines to enable devices to agree to use 64-bit transfer • JTAG/Boundary Scan – For testing procedures CSCI 4717 – Computer Architecture Buses – Page 33 CSCI 4717 – Computer Architecture Buses – Page 34 PCI Commands PCI Transaction Types • Transaction between initiator (master) and • Interrupt acknowledge – prompts identification target from interrupting device • Master claims bus • Special cycle – message broadcast • I/O read – read to I/O address space • During address phase of write, 4 C/BE • I/O write – write to I/O address space lines signal the transaction type • Memory read – 1 or 2 data transfer cycles • One or more data phases • Memory read line – 3 to 12 data transfer cycles • Memory read multiple – more than 12 data transfers CSCI 4717 – Computer Architecture Buses – Page 35 CSCI 4717 – Computer Architecture Buses – Page 36 6 PCI Read Timing Diagram PCI Transaction Types (continued) • Memory write – writing 1 or more cycles to memory • Memory write and invalidate – writing 1 or more cycles to memory allowing for cache write-back policy • Configuration
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