MFMIS Negative Capacitance Finfet Design for Improving Drive Current

electronics

Article MFMIS Negative Capacitance FinFET Design for Improving Drive Current

Jinhong Min and Changhwan Shin * Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-31-290-7694

Received: 30 July 2020; Accepted: 30 August 2020; Published: 2 September 2020

Abstract: The effect of remnant polarization (Pr), coercive electric-field (Ec), and parasitic capacitance of baseline device on the drive current (ION) of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance FinFET (NC FinFET) was investigated. The internal gate voltage in the MFMIS structure was simulated considering gate leakage current. Using technology computer aided design (TCAD) tool, the device characteristic of 7 nm FinFET was quantitatively estimated, for the purpose of modeling the baseline device of MFMIS NC FinFET. The need for appropriate parasitic capacitance to avoid performance degradation in MFMIS NC FinFET was presented through the internal gate voltage estimation. With an appropriate parasitic capacitance, the effect of Pr and Ec was investigated. In the case of Ec engineering, it is inappropriate to improve the device performance for MFMIS NC FinFET without threshold voltage degradation. Rather than Ec engineering, an adequate Pr value for achieving high ION in MFMIS NC FinFET is suggested.

Keywords: negative capacitance; steep switching; MOSFET

1. Introduction The negative capacitance field effect transistor (NCFET) was introduced as one of the steep switching devices [1]. The NCFET enables effectively lowering of the power supply voltage of conventional metal oxide semiconductor field effect transistor (MOSFET) because of its super steep switching feature, i.e., sub-60-mV/decade subthreshold swing at room temperature. Unlike the other steep switching devices (e.g., Tunnel FET [2] and nano-electro-mechanical (NEM) relay [3,4]), the NCFET requires an additional ferroelectric layer in its gate stack. Recent studies demonstrated some conspicuous characteristics of NCFET, e.g., improved subthreshold slope, hysteresis-free behavior, and improved DIBL (drain-induced barrier lowering) effect [5–10]. There are several factors which play an important role in determining the performance of NCFET. Those factors include electrical properties, such as coercive electric field (Ec), remnant polarization (Pr), and parasitic capacitance of baseline device without ferroelectric layer. Ec and Pr represent the electrical properties of the ferroelectric layer in NCFET. It is known that a hafnium-based ferroelectric material can have various values of Ec and Pr in a certain range, depending on fabrication conditions or dopants [11,12]. Therefore, the impact of Ec, Pr, and parasitic capacitance on NCFET performance was widely investigated [13,14]. Those studies have shown that the NCFET can improve its subthreshold slope and threshold voltage, by taking appropriate values of Ec, Pr, and parasitic capacitance. Additionally, the gate stack structure in NCFET affects the device performance of NCFET. As a gate stack structure for NCFET, a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure was suggested. It was expected that the intermediate metal layer in the MFMIS structure can act as an equipotential layer that alleviates multi-domain effects, so that it generates a higher voltage gain than in a metal-ferroelectric-insulator-semiconductor (MFIS) structure [15,16]. However, Khan et al. [17]

Electronics 2020, 9, 1423; doi:10.3390/electronics9091423 www.mdpi.com/journal/electronics Electronics 2020, 9, 1423 2 of 7 Electronics 2020, 9, x FOR PEER REVIEW 2 of 7 that,showed if there that, exists if there a leakage exists a leakagecurrent currentin the MFMIS in the MFMIS structure, structure, it is impossible it is impossible for the for polarization the polarization of ferroelectricof ferroelectric material material to stably to stably exist exist in the in the negati negativeve capacitance capacitance (NC) (NC) region region (i.e., (i.e., where where dP/dV dP/dV << 0).0). This is because the polarization of ferroelectric material slips toward either positive or negative Pr, so This is because the polarization of ferroelectric material slips toward either positive or negative Pr, so that thata stabilized a stabilized voltage voltage gain cannotgain cannot be expected. be expected. There isThere little studyis little of study the impact of the of thoseimpact parameters of those parameterson the device on performancethe device performance of MFMIS NCFETof MFMIS (which NCFET is a ff(whichected byis theaffected leakage by ofthe intermediate leakage of intermediate metal). To benefit the performance improvement in MFMIS NCFET, the impact of Ec, Pr, metal). To benefit the performance improvement in MFMIS NCFET, the impact of Ec, Pr, and parasitic and parasitic capacitance should be investigated. In this work, the impact of Ec, Pr, and parasitic capacitance should be investigated. In this work, the impact of Ec, Pr, and parasitic capacitance on capacitanceMFMIS NC on FinFET MFMIS was NC investigated FinFET was through investigat theed framework through the of Khan framework and 7 nmof Khan technology and 7 nodenm technologyfin-shaped node field fin-shaped effect transistor field effect (FinFET). transistor In addition, (FinFET). we In suggest addition, how we to suggest design thehow MFMIS to design NC theFinFET MFMIS to obtainNC FinFET better to device obtain performance. better device performance.

2.2. Simulation Simulation Method Method for for MFMIS MFMIS NC NC FinFET FinFET TheThe MFMIS MFMIS structure structure for for NCFET NCFET was was used used in in this this work work (see (see Figure Figure 11a).a). Due Due to the leakage currentcurrent through through the the internal internal gate, gate, the the ferroelectric ferroelectric layer layer cannot cannot stay stay in in the the negative negative capacitance capacitance region region (i.e.,(i.e., negative negative slope slope region region in in polarization-vs.-electric polarization-vs.-electric field field plot plot of of ferroelectric ferroelectric material), material), and and thereby, thereby, thethe MFMIS MFMIS NCFET NCFET cannot cannot be be expected expected to to benefit benefit the the stable stable voltage voltage amplification amplification of of the the ferroelectric ferroelectric layer.layer. In In order order to to take take advantage advantage of of using using the the voltage voltage amplification amplification of of the the ferroelectric ferroelectric layer layer in in MFMIS MFMIS NCFET,NCFET, the the dynamic responseresponse should should be be considered. considered. From From the the perspective perspective of time-dependency,of time-dependency, we havewe haveused used the frameworkthe framework of [17 of] [17] to estimate to estimate the voltagethe voltage amplification amplification in MFMIS in MFMIS NCFET. NCFET. In reference In reference [17], [17],the metal-ferroelectric-metal-insulator-metalthe metal-ferroelectric-metal-insulator-meta (MFMIM)l (MFMIM) structure structure was modeled was modeled as the series-connected as the series- connectedcircuit network circuit (see network Figure (see1b). TheFigure ferroelectric 1b). The ferro and dielectricelectric and thin dielectric film can thin be modeled film can as be the modeled parallel asconnection the parallel of connection the capacitor of the and capacitor resistor, andand theresistor, intermetal and the layer intermetal was modeled layer was as the modeled internal as node the internalbecause node the intermetal because the layer intermetal acts as thelayer equipotential acts as the equipotential surface between surface the ferroelectricbetween the andferroelectric dielectric andfilm. dielectric The polarization-vs.-electric-field film. The polarization-vs.-electric-field behavior of ferroelectric behavior of material ferroelectric is analytically material is described analytically with describedthe Landau-Khalatnikov with the Landau-Khalatnikov (LK) Equation (LK) (1) as Equation below. (1) as below. 𝑉 𝑇 ∙ 𝛼∙𝑃 𝛽∙𝑃3 , (1) VF = TF α PF + β P , (1) · · · F where TF indicates the thickness of ferroelectric layer, and the coefficients (i.e., α and β) are defined aswhere below.TF indicates the thickness of ferroelectric layer, and the coefficients (i.e., α and β) are defined as below. 3 3 3 3 √ 3 √3 3 √√3 3 𝛼α = ∙ 𝐸(⁄E𝑃c/P r ),, β 𝛽= E∙ c/𝐸P⁄𝑃 (2)(2) 2− 2 · 22 · r

FigureFigure 1. 1. (a()a )Cross-sectional Cross-sectional schematic schematic of of MFMIS MFMIS NC NC FinFET. FinFET. (b (b) )Circuit Circuit configuration conﬁguration of of MFMIM MFMIM

structure.structure. CCDD, C, CF,F C,Cparapara, R,FR, RF,DR indicatesD indicates the the capacitance capacitance of ofdielectr dielectric,ic, ferroelectric ferroelectric layer, layer, and and parasitic parasitic

capacitance;capacitance; and and the the resistance resistance of of the the dielectric dielectric and and ferroelectric layer, respectively.respectively. VG andand V VINTINT representsrepresents the the gate gate voltage voltage and and inte internalrnal metal metal voltage, voltage, respectively. respectively.

Electronics 2020, 9, 1423 3 of 7 Electronics 2020, 9, x FOR PEER REVIEW 3 of 7

ApplyingApplying thethe KirchhoKirchhoff’sff’s current current law law at at the the internal internal metal metal of theof the series series network, network, we we can can derive derive the equationthe equation below. below. dVG VG 1 1 3 C + + αQ + βQ dQF D dt RD RF RD F F − = , (3) dt 2 (3) 1 + CD α + 3βQ , F wherewhere RRFF, RD areare computed computed as as V Vappapp/(J/L( J×L A),A), where where JL isJL theis theleakage leakage current current that that is approximately is approximately 10−2 2 2 × 10A/cm− A2/ cmfor anfor applied an applied bias bias of 1 of V 1 [18]. V [18 The]. The equation equation shows shows the the amount amount of of charge charge in in the the ferroelectric layerlayer overover time. time. Thus,Thus, applying applying a a triangular triangular pulse, pulse, the the amount amount of of charge charge in in the the ferroelectric ferroelectric layer layer can can be estimated,be estimated, and and thereby, thereby, it turned it turned out that out thethat MFMIM the MFMIM structure structure can show can theshow voltage the voltage amplification amplification across theacross ferroelectric the ferroelectric layer. Note layer. that Note the equationthat the equation is derived is from derived the MFMIMfrom the structure, MFMIM butstructure, it is applicable but it is toapplicable MFMIS NCFETto MFMIS [19 ].NCFET [19]. AlthoughAlthough the MFMIS MFMIS NCFET NCFET can can use use the the negative negative slope slope region region of ferr ofoelectric ferroelectric layer, layer, the theperformance performance degradation degradation of ofthe the MFMIS MFMIS NCFET NCFET was was expected. expected. The The work work function function engineering waswas suggestedsuggested to prevent the performance performance degradation degradation as as well well as as to to enhance enhance the the on-state on-state drive drive current current of ofNCFET NCFET [19]. [19 Using]. Using metal metal materials materials with with two two different different work work function function values values to wrap to wrap around around the theferroelectric ferroelectric layer, layer, the the S-curves S-curves in inpolarization polarization ve versusrsus voltage voltage plot plot can can be be shifted shifted along the voltagevoltage axis.axis. TheThe voltagevoltage shift shift can can put put the the ferroelectric ferroelectric into theinto negative the negative capacitance capacitance state (i.e., state a smaller (i.e., a amountsmaller ofamountVG can of put VG thecan ferroelectricput the ferroelectric into the negativeinto the negative capacitance capacitance state). In state). this simulation In this simulation work, 0.2 work, V of V0.2off setV ofis V appliedoffset is applied through through the work the functionwork function engineering engineering between between two metaltwo metal layers layers (see (see Figure Figure2a). It2a). is noteworthyIt is noteworthy that the thatID-vs.- the VIDG-vs.-Vand CGG and-vs.- VCGG-vs.-Vof baselineG of baseline FinFET withoutFinFET MFMwithout layer MFM are estimatedlayer are usingestimated Sentaurus using TCADSentaurus tool TCAD (see Figure tool 3(see). The Figure FinFET 3). The is modeled FinFET inis accordancemodeled in withaccordance 7 nm technology with 7 nm oftechnology IRDS 2017 of roadmapIRDS 2017 [20 roadmap]. The physical [20]. The device physical dimensions device dimensions of the FinFET of the are FinFET shown are in shown Table 1in. WithTable the 1. With estimated the estimatedID-vs.-VG IandD-vs.-VCG-vs.-G andV GCGof-vs.-V baselineG of FinFET,baseline andFinFET, the Equation and the Equation (3), the ID (3),-vs.- theVG IofD- MFMISvs.-VG of NC MFMIS FinFET NC was FinFET estimated. was estimated. In this work, In this the wo capacitancerk, the capacitance condition condition was well satisfiedwas well insatisfied all VG sweepin all V regionsG sweep [ 1regions], so that [1], there so that is no there hysteresis is no hysteresis in the ID-vs.- in theVG IofD-vs.-V MFMISG of NCMFMIS FinFET. NC FinFET.

FigureFigure 2. (a(a) )Two Two S-curves S-curves are are drawn drawn in inpolarization polarization vers versusus voltage voltage plot. plot. The red-colored The red-colored one is one the isS-curve the S-curve with work with workfunction function engineering. engineering. The black-colored The black-colored one is one the is reference the reference S-curve, S-curve, for 2 forcomparison. comparison. Note Note that that Pr Pandr and Ec Eofc ofthe the reference reference S-curve S-curve are are 10 10 μµC/cmC/cm2 andand 0.7 0.7 MV/cm, MV/cm, respectively. respectively.

VVINTINT-vs.-time-vs.-time for for ( b) various parasitic capacitances,capacitances, (c) EEcc, andand ((dd)) PPrr.. Note that thethe referencereference lineline (black-colored(black-colored dotteddotted line)line) indicatesindicates thethe 100100 MHzMHz 11 VV triangulartriangular pulse.pulse.

Electronics 2020, 9, 1423 4 of 7 Electronics 2020, 9, x FOR PEER REVIEW 4 of 7

FigureFigure 3. 3. ((aa)) EstimatedEstimated current-vs.-voltagecurrent-vs.-voltage ((IID-vs.-V-vs.-VG)) of of baseline baseline FinFET FinFET in in log log (left) (left) and and linear linear (right) (right)

scale.scale. ((bb)) EstimatedEstimated capacitance-vs.-voltagecapacitance-vs.-voltage (C (CG-vs.-V-vs.-VGG) )of of baseline baseline FinFET. FinFET. Table 1. The important device parameters for MFMIS NC FinFET. Table 1. The important device parameters for MFMIS NC FinFET. Device Parameter Quantity Device Parameter Quantity Device Parameter Quantity Device Parameter Quantity 1 GateGate Length, Length, LG LG 18 18 nm nm OxideOxide Thickness Thickness 1,T, TOXOX 3 nm3 nm Spacer Thickness, L 7 nm Channel Doping, N 1015 cm 3 SP SP SPSP 15 −3 − Spacer Thickness, L 7 nm Channel Doping, N 10 20cm 3 Fin Height, HFin 50 nm Source/Drain Doping, NSD 10 cm− Fin Height, HFin 50 nm Source/Drain Doping, NSD 1020 cm−3 Fin Width, WFin 7 nm Ferroelectric Thickness, TF 3 nm Fin Width, WFin 7 nm Ferroelectric Thickness, TF 3 nm 1 Hafnium oxide was used as the gate oxide. 1 Hafnium oxide was used as the gate oxide.

3. Effect of Ec, Pr, and Parasitic Capacitance on MFMIS NC FinFET 3. Effect of Ec, Pr, and Parasitic Capacitance on MFMIS NC FinFET Using (1) 100 MHz 1 V triangular pulses, (2) the parameter of hafnium oxide ferroelectric Using (1) 100 MHz 1 V triangular pulses, (2) the parameter of hafnium oxide ferroelectric material, material, and (3) CG-vs.-VG of baseline device, we can find out the voltage-vs.-time characteristic of and (3) CG-vs.-VG of baseline device, we can find out the voltage-vs.-time characteristic of MFMIS MFMIS NC FinFET. Note that Ec and Pr used for the S-curve in Figure 2a was 0.7 MV/cm and 102 NC FinFET. Note that Ec and Pr used for the S-curve in Figure2a was 0.7 MV /cm and 10 µC/cm , μC/cm2, respectively [12–14]. The S-curve of ferroelectric material (in which the work function is respectively [12–14]. The S-curve of ferroelectric material (in which the work function is engineered) is engineered) is shown in Figure 2a. We used the 100 MHz frequency because if the frequency of shown in Figure2a. We used the 100 MHz frequency because if the frequency of sweeping VG is faster sweeping VG is faster than the “effective time constant” [17], the impact of the leakage current should than the “effective time constant” [17], the impact of the leakage current should be neglected. be neglected. The impact of varied Ec and Pr of ferroelectric material is shown in Figure2c,d. As shown in The impact of varied Ec and Pr of ferroelectric material is shown in Figure 2c,d. As shown in the the figures, the internal voltage decreased and was lower than the reference voltage over the whole figures, the internal voltage decreased and was lower than the reference voltage over the whole time. time. The internal voltage decreases more with increasing Ec. In the case of decreasing Pr, the internal The internal voltage decreases more with increasing Ec. In the case of decreasing Pr, the internal voltage increases but is still lower than the reference voltage over the whole time. The reason for voltage increases but is still lower than the reference voltage over the whole time. The reason for the the internal voltage lowering comes from the fact that CG in the baseline FinFET increases at about 0.3 V internal voltage lowering comes from the fact that CG in the baseline FinFET increases at about 0.3 V (see(see Figure Figure3 b)3b) due due to to the the inversion inversionlayer, layer,and and thereby,thereby, thethe internalinternal amplificationamplification deteriorates. In In this this case,case, an an appropriateappropriate parasiticparasitic capacitancecapacitance can allevi alleviateate the the internal internal voltage voltage lowering, lowering, and and therefore, therefore, itit induces induces a a properproper voltagevoltage amplificationamplification in MFMIS structure (see (see Figure Figure 22b).b). Total Total device device capacitance capacitance (C ) can be calculated as (C + Cpara). In the case of 100 aF of parasitic capacitance, V of 1.2 V (CTOTTOT) can be calculated as (CGG + Cpara). In the case of 100 aF of parasitic capacitance, VINT ofINT ≈1.2 V≈ can V canbe implemented be implemented by applying by applying a V aG ofG 1of V. 1 By V. Byapplying applying 100 100 aF aFof ofparasitic parasitic capacitance capacitance to obtain to obtain a aproper proper voltage voltage amplification, amplification, the the impact impact of of EEc candand PPrr waswas investigated investigated again. again. First, First, increasing increasing EEc c makesmakes the the amount amount of of voltage voltage amplification amplification (at (at 1 V1 V of of reference reference voltage) voltage) become become higher higher (see (see Figure Figure4a). However,4a). However, at a low at a reference low reference voltage, voltage, the lowering the lowering of internal of internal voltage voltage becomes becomes severe. severe. This is becauseThis is abecause higher Ea chigherneeds E additionalc needs additional voltage tovoltage put ferroelectricto put ferroelectric material material into the into negative the negative slope region.slope Inregion. the case In the of highercase ofE higherc, the loweringEc, the lowering of internal of internal voltage voltage can be can compensated be compensated using using different different metal (whichmetal (which makes makes Voffset moreVoffset thanmore0.2 than V) 0.2 [8]. V) [8]. When Pr is increased, the reference voltage (at which the internal voltage is amplified) is pushed to a higher voltage (see Figure 4b). Low Pr (i.e., 5 μC/cm2) can derive the voltage amplification at a much lower reference voltage. However, the internal voltage at a high reference voltage will be degraded. Additionally, even if Pr becomes lower, it is hard to expect performance enhancement at

Electronics 2020, 9, x FOR PEER REVIEW 5 of 7

the deep subthreshold region. In the case of high Pr (i.e., 15 μC/cm2), the internal voltage loses the voltage amplification in all regions of the reference voltages. Using the internal voltages of various conditions, ID-vs.-VG of NC FinFETs were estimated (see Figure 4c,d). In the ID-vs.-VG of NC FinFETs, the on-state drive current (ION) and threshold voltage (VT) were extracted (see Figure 5). Note that VT was extracted at the constant current of 100 nA/um. Higher Ec enables the MFMIS NC FinFET to achieve the highest ION, but, at the same time, it increases VT significantly. If Pr is in-between 5 μC/cm2 and 10 μC/cm2, ION and VT have a trade-off relationship to each other. However, the trade-off is not Electronicsfound2020 in, 9 the, 1423 case of 15 μC/cm2. Even using a low Pr in MFMIS NC FinFET, a significant improvement 5 of 7 in VT is hard to expect.

Electronics 2020, 9, x FOR PEER REVIEW 5 of 7

the deep subthreshold region. In the case of high Pr (i.e., 15 μC/cm2), the internal voltage loses the voltage amplification in all regions of the reference voltages. Using the internal voltages of various conditions, ID-vs.-VG of NC FinFETs were estimated (see Figure 4c,d). In the ID-vs.-VG of NC FinFETs, the on-state drive current (ION) and threshold voltage (VT) were extracted (see Figure 5). Note that VT was extracted at the constant current of 100 nA/um. Higher Ec enables the MFMIS NC FinFET to achieve the highest ION, but, at the same time, it increases VT significantly. If Pr is in-between 5 μC/cm2 and 10 μC/cm2, ION and VT have a trade-off relationship to each other. However, the trade-off is not found in the case of 15 μC/cm2. Even using a low Pr in MFMIS NC FinFET, a significant improvement in VT is hard to expect.

FigureFigure 4. VINT 4. V-vs.-timeINT-vs.-time for for a a few few EEcc ((aa)) and and PrP (rb).(b The). The black-colored black-colored dotted dotted reference reference line indicates line indicatesthe the 100100 MHz MHz 1 1 V V triangular triangular pulse.pulse. The esti estimatedmated drain drain current-vs.-gate current-vs.-gate voltage voltage (ID-vs.-V (ID-vs.-G) ofV baselineG) of baseline FinFETFinFET (see the(see black-colored the black-colored solid solid line) line) and and MFMIS MFMIS NC NC FinFET FinFET (see (see the the blue blue/red/purple-colored/red/purple-colored solid solid lines) for a few Ec (c) and Pr (d). lines) for a few Ec (c) and Pr (d).

When Pr is increased, the reference voltage (at which the internal voltage is amplified) is pushed 2 to a higher voltage (see Figure4b). Low Pr (i.e., 5 µC/cm ) can derive the voltage amplification at a much lower reference voltage. However, the internal voltage at a high reference voltage will be degraded. Additionally, even if Pr becomes lower, it is hard to expect performance enhancement 2 at the deep subthreshold region. In the case of high Pr (i.e., 15 µC/cm ), the internal voltage loses the voltage amplification in all regions of the reference voltages. Using the internal voltages of various conditions, ID-vs.-VG of NC FinFETs were estimated (see Figure4c,d). In the ID-vs.-VG of NC FinFETs, the on-state drive current (ION) and threshold voltage (VT) were extracted (see Figure5). Note that VT was extracted at the constant current of 100 nA/um. Higher Ec enables the MFMIS NC FinFET to 2 achieve the highest ION, but, at the same time, it increases VT significantly. If Pr is in-between 5 µC/cm Figure2 4. VINT-vs.-time for a few Ec (a) and Pr (b). The black-colored dotted reference line indicates the and 10 µC/cm ,ION and VT have a trade-off relationship to each other. However, the trade-off is not 100 MHz 1 V triangular pulse. The estimated drain current-vs.-gate voltage (ID-vs.-VG) of baseline 2 found in theFinFET case of(see 15 theµ Cblack-colored/cm . Even solid using line) a and low MFPMISr in NC MFMIS FinFET NC (see FinFET, the blue/red/purple-colored a significant improvement in VT is hardsolid to expect.lines) for a few Ec (c) and Pr (d).

Figure 5. Scatter plot of extracted ION and VT of various MFMIS NC FinFETs.

FigureFigure 5. Scatter 5. Scatter plot plot of extractedof extracted I ONION and VVT Tofof various various MFMIS MFMIS NC FinFETs. NC FinFETs.

Electronics 2020, 9, 1423 6 of 7

4. Conclusions

The impact of Ec, Pr, and parasitic capacitance on the performance of MFMIS NC FinFET was investigated. To ﬁnd out the voltage of intermediate metal in the MFMIS structure, Landau-Khalatnikov model with the gate leakage current was used. Investigating the eﬀect of parasitic capacitance on the MFMIS structure, the parasitic capacitance can be the key knob to control the internal voltage. 2 With 100 aF of parasitic capacitance, Ec and Pr in ferroelectric material were varied between 5–15 µC/cm and 0.7–1.2 MV/cm, respectively. In order to design MFMIS NC FinFET to achieve high drive current, Ec of 1.2 MV/cm can induce the highest drive current (i.e., 1.5 times higher drive current than in baseline device). However, the threshold voltage of the NC FinFET was increased (by 0.12 V) than that of ≈ 2 baseline device. On the other hand, the NC FinFET with an appropriate value of Pr (i.e., 10 µC/cm ) can achieve 1.4 times higher drive current than baseline device with little VT degradation.

Author Contributions: Conceptualization, J.M. and C.S.; methodology, J.M.; software, J.M.; validation, J.M. and C.S.; formal analysis, J.M.; investigation, J.M.; resources, J.M.; data curation, J.M. and C.S.; writing—original draft preparation, J.M.; writing—review and editing, C.S.; visualization, J.M.; supervision, C.S.; project administration, C.S.; funding acquisition, C.S. All authors have read and agreed to the published version of the manuscript. Funding: This study was supported by the National Research Foundation of Korea (NRF) through a grant funded by the Korean government (MSIP; No. 2020R1A2C1009063, 2020M3F3A2A01081672, and 2020M3F3A2A02082473). Additionally, this work was supported by the Future Semiconductor Device Technology Development Program (10067746) funded by the Ministry of Trade, Industry & Energy (MOTIE), and the Korea Semiconductor Research Consortium (KSRC). The EDA Tool was supported by the IC Design Education Center. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References

1. Salahuddin, S.; Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 2008, 8, 405. [CrossRef][PubMed] 2. Choi, W.Y.; Park, B.; Lee, J.D.; Liu, T.K. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE Electron Device Lett. 2007, 28, 743. [CrossRef] 3. Choe, K.; Shin, C. Adjusting the Operating Voltage of an Nanoelectromechanical Relay Using Negative Capacitance. IEEE Trans. Electron Devices 2017, 64, 5270. [CrossRef] 4. Nathanael, R.; Pott, V.; Kam, H.; Jeon, J.; Liu, T.K. 4-terminal relay technology for complementary logic. In Proceedings of the 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, USA, 7–9 December 2009. 5. Jo, J.; Choi, W.Y.; Park, J.-D.; Shim, J.W.; Yu, H.-Y.; Shin, C. Negative capacitance in organic/ferroelectric capacitor to implement steep switching MOS devices. Nano Lett. 2015, 15, 4553. [CrossRef][PubMed] 6. Jo, J.; Shin, C. Negative capacitance field effect transistor with hysteresis-free sub-60-mV/decade switching. IEEE Electron Device Lett. 2016, 37, 245. [CrossRef] 7. Li, K.-S.; Chen, P.-G.; Lai, T.-Y.; Lin, C.-H.; Cheng, C.-C.; Chen, C.-C.; Wei, Y.-J.; Hou, Y.-F.; Liao, M.-H.; Lee, M.-H.; et al. Sub-60mV-swing negative-capacitance FinFET without hysteresis. In Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 7–9 December 2015. 8. Zhou, H.; Kwon, D.; Sachid, A.B.; Liao, Y.; Chatterjee, K.; Tan, A.J.; Yadav, A.K.; Hu, C.; Salahuddin, S. Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect. In Proceedings of the 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 18–22 June 2018; p. 53. 9. Kwon, D.; Chatterjee, K.; Tan, A.J.; Yadav, A.K.; Zhou, H.; Sachid, A.B.; Dos Reis, R.; Hu, C.; Salahuddin, S. Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors. IEEE Electron Device Lett. 2018, 39, 300. [CrossRef] 10. Shin, J.; Shin, C. Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET. Solid State. Electron. 2018, 153, 12. [CrossRef] 11. Kim, T.; Jeon, S. Pulse switching study on the HfZrO ferroelectric films with high pressure annealing. IEEE Trans. Electron Devices 2018, 65, 1771. [CrossRef] Electronics 2020, 9, 1423 7 of 7

12. Kobayashi, M.; Hiramoto, T. Device design guideline for steep slope ferroelectric FET using negative capacitance in sub-0.2V operation: Operation speed, material requirement and energy efficiency. In Proceedings of the 2015 Symposium on VLSI Technology (VLSI Technology), Kyoto, Japan, 16–18 June 2015; p. T212. 13. Khandelwal, S.; Duarte, J.; Khan, A.; Salahuddin, S.; Hu, C. Impact of parasitic capacitance and ferroelectric parameters on negative capacitance FinFET characteristics. IEEE Electron Device Lett. 2017, 38, 142. [CrossRef] 14. Lin, C.; Khan, A.; Salahuddin, S.; Hu, C. Eﬀects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics. IEEE Trans. Electron Devices 2016, 63, 2197. [CrossRef] 15. Saha, A.K.; Sharma, P.; Dabo, I.; Datta, S.; Gupta, S.K. Ferroelectric transistor model based on self-consistent solution of 2D Poisson’s, non-equilibrium Green’s function and multi-domain Landau Khalatnikov equations. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017. 16. Pahwa, G.; Agarwal, A.; Chauhan, Y.S. Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Above-Threshold Behavior. IEEE Trans. Electron Devices 2019, 66, 1591. [CrossRef] 17. Khan, A.I.; Radhakrishna, U.; Chatterjee, K.; Salahuddin, S.; Antoniadis, D.A. Negative Capacitance Behavior in a Leaky Ferroelectric. IEEE Trans. Electron Devices 2016, 63, 4416. [CrossRef] 18. Ando, T.; Sathaye, N.D.; Murali, K.V.R.M.; Cartier, E.A. On the Electron and Hole Tunneling in a HfO2 Gate Stack with Extreme Interfacial-Layer Scaling. IEEE Electron Device Lett. 2011, 32, 865. [CrossRef] 19. Khan, A.I.; Radhakrishna, U.; Salahuddin, S.; Antoniadis, D. Work Function Engineering for Performance Improvement in Leaky Negative Capacitance FETs. IEEE Electron Device Lett. 2017, 38, 1335. [CrossRef] 20. The International Roadmap for Devices and Systems (IRDS 2017). Available online: https://irds.ieee.org/ roadmap-2017 (accessed on 1 August 2019).

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).