Design of Low Power 4 Bit ALU Using 32 Nm Finfet Technology

Home , FinFET

International Journal of Pure and Applied Mathematics Volume 120 No. 6 2018, 8089-8100 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ Special Issue http://www.acadpubl.eu/hub/

Design of Low power 4 bit ALU using 32 nm FinFET technology

Jency Rubia J1, Babitha Lincy R2, 1,2Department of ECE, 3Sri Venkateswara College of Engineering, Chennai,India. [email protected] [email protected]

July 19, 2018

Abstract This paper proposes a 4-Bit Arithmetic logic unit (ALU) using FinFET at 32nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel eﬀects such as DIBL, GIDL, Sub threshold swing, channel length modulation, mobility degra- dation etc. To change nanoscale CMOS, a multi gate device called FinFET is suggested. FinFET has its own advantages over the CMOS such as reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this paper is to reduce and calculate leakage power of 4-Bit ALU using FinFET. Key Words:FinFET technology; Cmos technology; Arith- metic logic unit (ALU); Leakage power; Low power analysis; Delay analysis.

1 INTRODUCTION

Today mobile and computing markets continue to innovate at a dra- matic rate delivering more performance in smaller form factors with

8089 International Journal of Pure and Applied Mathematics Special Issue

higher power efficiencies. According to Moores law, the number of transistors in an area should double every months. To achieve this into realism, transistors should get shrink in size to accommodate double the number per unit area. While scaling down the device channel length, the short channel effects are raised [1]. These draw- backs are tackled by FinFET. FinFETs have been considered as a promising technology to reduce the short channel effects of the scale down devices, due to their better electrostatic control over the channel[15]. ADDITION is the most commonly used arithmetic operation in Central Processing Unit(CPU) and Arithmetic Logic Unit(ALU). Therefore, careful designing of ADDER is of the utmost relevance. Back Gate is used to control the threshold voltage (VT) of the front gate, which is very important parameter of the device [3]. This helps in optimizing the circuits in terms of delay, area and power. In the paper [4], the logic gates and flip flops are designed and anal- ysed in Short Gate (SG), Independent Gate (IG), Low Power (LP) and Mixed Mode (MM) in 90 nm technology. Minimum delay has been achieved in SG mode, low power in LP configuration at the expense of increased delay was also discussed. In IG mode, inputs can be applied to two different gates; thus reduces the number of devices in a circuit. An MM results in low leakage, reduced area and higher delay. 4-T SRAM cell was designed to achieve effective static noise margin (SNM) without area penalty [5]. This paper is organized as follows. Section II simplifies the FinFET technology, its features and issues in the design. Section III describes the 4-bit ALU using FinFET 32nm technology. Section IV shows the simulation waveform and the results. Finally the conclusion and the future enhancement has been explained in section V.

2 FINFET TECHNOLOGY

FinFETs are quasi-planar field-effect transistors. The working prin- ciple is same as that of planar MOSFET [6-13]. Figure 1 shows the structure of a FinFET. With SOI wafer as a basic platform, a thin film of silicon having thickness TSI is patterned on it. The gate shawls around the fin. The channel is formed perpendicular to the

8090 International Journal of Pure and Applied Mathematics Special Issue

plane of the wafer. Its length is shown as LG. This is the reason that the device is termed quasi-planar. The effective width of a FinFET is 2nHfin , where n is the number of fins and Hfin is the fin height. Multiple fins led to make a high on-current transistor [14]. FinFET width is quantized, in terms of number of fins. Some key design factors like performance, power and functionality, profound on ra- tio are also dealt. Beyond the technology-driven benefits offered by FinFETs, circuits can also benefit from the double gate structure of FinFETs to further optimize power and performance. FinFET leads to some interesting designs by means of etching out the top part of the device that achieves independent gate structure[17].

Figure 1 Structure of the FinFET

A. FinFET Model Parameter

In FinFET, as in Figure 2, the gate straddles a thin, fin shaped body, forming three-aligned channels along the top and vertical sidewall surfaces of the fin. The use of double or multiple gates surrounding the fin ensures an excellent electrostatic control. When the channel length is scaled down, the predominant short channel effects and off-state leakage current arises which are suppressed by reducing the width of the fin. The fin width is an additional scaling parameter to the gate oxide. The fin width should be unevenly half the channel length.

8091 International Journal of Pure and Applied Mathematics Special Issue

Figure 2 Electrical Dimension of the 3D FinFET Structure A FinFET can have multiple ﬁns in parallel, all straddled by a single gate line, thus its eﬀective width [2] is given by,

where n is the number of fins, Hfin and Wfin is the fin height and width respectively.

B. Leakage Power Analysis

Leakage current (ILEAK) is directly proportional to the thickness of the silicon and moderately independent of oxide thickness. However, for FinFETs under the short-channel regime with low silicon thickness and gate length, this is inaccurate as it fails to account for the short-channel effect and quantum confinement effect. Based on the short-channel effect and quantum confinement, the FinFETs are inaccurate which occurs in the short-channel regime. Leakage current should then be obtained from the general expression for sub-threshold leakage.

where nc(x,y) is the eﬀective channel concentration, using Taylor se- ries expansion of log (nc(x,y)), an analytical model is developed for leakage in individual transistors and transistor stacks. The model correctly predicts an exponential loss in gate control over increasing

8092 International Journal of Pure and Applied Mathematics Special Issue

silicon thickness or decreasing gate length, and hence an exponential increase in ILEAK. From the above remarks, we formulate a macro model for leakage in SG-mode FinFET as

where a1,a2,b1 are the coeﬃcients.

C. Challenges in FinFET

In a conventional planar transistor, shown in Figure 3 the current ﬂowing through channel depends upon the width of the device (W). As we know, width of the device is half the channel length (L). If the device scale is down, it is necessary to decrease its channel length, which improves the drive strength of the transistor. How- ever smaller gate length, transistors have less control over the channel and exponentially higher subthreshold leakage. To control leakage, the channel should be heavily doped, which will leads to design ﬂuctuations are important challenges in manufacturing FinFET.

Fig 3. Planar FinFET vs. Tri Gate FinFET

In tri-gate transistor, the gate surrounds the channel on all three sides. It gives much control over the channel. So all the charges be- low the channel is removed (fully depleted). If the gate is controlled strongly then sub threshold leakage can be reduced with the best control of dopant variation on the channel. FinFETs cause con- siderable changes in physical IP design but their eﬀect can mostly be hidden from higher levels. Designers can take advantages of improved performance by working at lower voltages.

8093 International Journal of Pure and Applied Mathematics Special Issue

3 4 BIT ALU USING FINFET

A. Overview of ALU

In digital electronics, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and bitwise logical operations on integer binary numbers. It is a fundamental building block of the central processing unit found in many computer. The designed ALU circuit performs addition/subtraction and comparator operations and some logic functions. The block diagram of the proposed ALU is in Figure 4. In the above diagram, full adder/subtractor has 3 inputs so we take three inputs namely A.B and Cin. Other than adder/subtractor all the operations only needs 2 inputs. The functions are selected by multiplexer with select line. And then we obtained the output.

Fig 4 Block diagram of the Proposed ALU Circuit

B. Arithmetic Operation

Arithmetic or arithmetics is the oldest and most elementary branch of mathematics. It consists of the study of numbers, espe- cially the properties of the traditional operations between them -

8094 International Journal of Pure and Applied Mathematics Special Issue

addition, subtraction, multiplication and division. Arithmetic is an elementary part of number theory, and number theory is considered to be one of the top-level divisions of modern mathematics, along with algebra, geometry and analysis. The designed arithmetic logic unit does the arithmetic operations of addition, subtraction and comparison operations. The comparator consists of lesser, greater and equal operations.

C. Logic Operations

A digital Logic Gate is an electronic device that makes logical decisions based on the diﬀerent combinations of digital signals present on its inputs. Digital logic gates may have more than one input but generally only have one digital output. Individual logic gates can be connected together to form combinational or sequen- tial circuits, larger logic gate functions. The proposed ALU circuit does various logic operations such as AND, OR, NOT and XOR. Each and every gate structure replaced with FinFET.

4 SIMULATION RESULTS & WAVE- FORMS

Input and the output waveforms are shown in Figure 5, 6 and Figure 7 respectively for ALU circuit. The proposed ALU circuit has 2 inputs, one carry input and 3 select lines. The resulted output is the functional output and Carry out. The Figure 5 explains about 2 inputs and carry input which are A, B, Cin waveforms.

8095 International Journal of Pure and Applied Mathematics Special Issue

Fig 5 Input waveform to the ALU circuit

Fig 6 output waveform of the ALU circuit Fig 7 output comparator waveform of the ALU circuit

The above Figure 6 shows the output waveforms for Adder/Subtractor, AND, OR, NOT A, XOR. The output waveform of Comparator is shown in Figure 7. The ﬁrst waveform is the output for less than value (A¡B). The second waveform shows that the output for greater than values (A¿B). The third waveform is the output for equal values (A=B) and the carry output cout.

Fig 8 Leakage power of the ALU circuit

8096 International Journal of Pure and Applied Mathematics Special Issue

The power dissipation in each sub-circuit of ALU is exhibited in Figure 8. Initially, the power dissipation of ﬁrst sub-circuit is 176 n watts. Similarly the power dissipation has been calculated from all the sub-circuits. The total voltage source power dissipation calculated is 219.733n watts.

5 CONCLUSION & FUTURE ENHANCEMENT

The proposed work presents designing of ALU using FinFET 32nm technology. To minimize the leakage power, leakage current and operating power of a ALU FinFET technique has been employed. It is realized from the power analysis of arithmetic logic unit circuit as shown in Figure 8, the leakage power is found to be 219.733 nW. The HPICE EDA tool is used to get the simulation results.

A reliable future work can be carried out in designing higher bit of ALU and other complex processing circuits using this ALU.

References

[1] Jency Rubia, Gopal B.G and Prabhu V. Analysis, Design and implementation of 4 bit full adder using FinFET. Journal of convergence information technology (JCIT) volume 10. number 2.pp 71-77.March 2015.

[2] Bibin Lawrence R and Jency Rubia J.Review of FinFET technology and circuit design challenges.international journal of engineering research and applications.Volume 5. issue 12.De- cember 2015.

[3] Y.Taur and T.H.Ning.Fundamentals of modern VLSI Devices New York: Cambridge Univ. Press .1998.

[4] Mayank Shrivastava, M.S.Baghni, D.K.Sharma, V.R.Rao .A novel bottom spacer FinFET structure for improved short- channel, power delay, and thermal performance .IEEE Trans. On Electron Devices.vol. 57.no.6. pp 1287-1294 June 2010

8097 International Journal of Pure and Applied Mathematics Special Issue

[5] M.Rostami and K.Mohanram. Dual-Vth independent-gate FinFETs for low power logic circuits. IEEE Trans. Computer Aided Design. volume 30. no 3, pp 337-349, March 2011. [6] Zheng Guo, Sriram Balasubramanian, Radu Zla- tanovici.FinFET Based SRAM Design. in proceeding 2005 International Symposium on Low Power Electronics and Design. IEEE Transaction. pp 2-7. August 2005 [7] A.Datta, A.Goel , R.T.Cakichi , H.Mahmoodi, D.Lakshmanan, and K.Roy. Modeling and circuit syn- thesis for independently controlled double gate FinFET devices. IEEE Transaction Computer Aided Design. volume 26. no 11. pp 1957-1966. Nov 2007. [8] A.Muttreja, N.Agarwal, and N.K.Jha. CMOS logic design with independent-gate FinFETs.in Proc. International Conference in Computer Design. pp 560-567. October 2007. [9] S.A.Tawfik and V.Kursun. Low-power and compact sequen- tial circuits with independentgate FinFETs. IEEE Transaction Computer Aided Design. Volume 26. no 55. pp 60-70. January 2008. [10] S.A.Tawfik and V.Kursun. Characterization of new static independent-gate biased FinFET latches and flip-flops under process variations. in Proc. International Symposium Qual. Electron Design. March 2008. pp 311-316. [11] Prateek Misra, Anish Muttreja and Niraj K.Jha, FinFET Cir- cuit Design .Springer. 2011. [12] M.Alioto. Comparative evaluation of layout density in 3T , 4T , and MT FinFET standard cells IEEE Trans. Very Large Scale Integration (VLSI) System Volume 19 no 5 pp 751-762. May 2011. [13] Anish Muttreja , Niket Agarwal and Niraj K.Jha. CMOS Logic Design with independent-gate FinFETs 25th Interna- tional Conference on Computer Design. pp 560-567. Oct 2007. [14] Prateek Mishra. Low power FinFET circuit design and syn- thesis under Spatial and Temporal variation . November 2012.

8098 International Journal of Pure and Applied Mathematics Special Issue

[15] Indraneel Suryavanshi, Ajit Gangad and Prathamesh Chodankar. Design of 1-bit Full Adder using FinFET. Inter- national Journal of Applied Engineering Research. vol.8. no. 19. 2013.

[16] International Technology Roadmap for Semiconductors. Semiconductor Industry Association.[Online] Available : http://public.itrs.net

[17] Design of High-performance digital logic circuits based on Fin- FET technology. International Journal of Computer Applica- tions. pp 40-44 March 2012.

8099 8100