Finfet: a New Era for Integrated Circuits

International Journal of Advance Science and Technology Vol. 29, No. 10S, (2020), pp. 1928-1932

FinFET: A New Era For Integrated Circuits Saumya Srivastava1, Deepak B Kuttan2 1,2Electronics and communication Department, Chandigarh University, Mohali Punjab Abstract In this new world due to the increase in the demand of high speed technologies, FinFET plays a major role. FinFET has surpassed MOSFET technology because it has lesser small channel effect. This review paper consist of an explanation of FinFET, its basic diagram, its construction details, working, some analysis, advantages, disadvantages and future scope.

Keyword: FinFET, SOI, oxide, SEU, Ion INTRODUCTION Due to the increase in the difficulty of the scaling of MOSFET below 32nm FinFET helps to work below this technology level. Now the question arises what is FinFET? A FinFET is a non-planar double gate transistor build on the substrate. It is made in that form such that it looks like a double gate structure. It is also known as quasi-planar device due to its vertical geometry. This kind of structure helps to increase the energy efficiency [1]-[4]. It was first introduced by Chenming Hu with his collegues at university of calorfonia.Main aim of the introduction of FinFET was to reduce the leakage current which was more in CMOS design [5] The geometry of FinFET depends on the height, length, width of Fin. The minimum width of single is Fin should be approximately equal to W= 2X height[1] Basic diagram:

Fig1: A basic outlook of FinFET

Construction detail: There are basically 7 steps to make the FinFET they are as follows:

1. The base is a lightly doped p doped substrate which have a hard mask on top on top(can be a silicon nitride) with a patterned resistive layer.

International Journal of Advance Science and Technology Vol. 29, No. 10S, (2020), pp. 1928-1932

2. In the second process the fins are made with a high anisotropic etch process. As the bulk doesn’t contain any stop layer because present in SOI it becomes a time based process [6].

3. The third process is an oxide deposite process in which we isolate the fins from each other by deposition. Oxide deposition is needed with a high (W/L) ratio behaviour.

4. In this process excess amount of oxide is removed by planarizing it by chemical mechanical polishing known as planarization [7].

5. An extra etch process is used to recess the oxide film and form a lateral isolation of the films which is known as recess etch.

International Journal of Advance Science and Technology Vol. 29, No. 10S, (2020), pp. 1928-1932

6. Sixth process is a gate oxide process in which oxide is deposited on the gate chip via thermal oxidation process is used to isolate the channel from gate electrode [8]-[10].

7. Finally in deposition process of the gate, a highly doped n+ poly silicon layer is lightly deposited over fins.

Working: The working of FinFET is same as the conventional MOSFET but its having the advantage of having gate on both side of conduction inversion channel. So that entire fin is conducting above threshold.When the gate electrode is energised at its best level for different region of fin located beneath the electrode is inverted and forms a conductive pathway between source and drain [1]- [3].FinFET features that silicon germanium or silicon carbon over drain source to enhance performance just like classical transistor. Performance parameters: These performance parameters are basically used over 6T-SRAM[5] 1. Soft error vulnerability analysis: The major cause of generation of soft error are alpha particle, high energy neutron and the interaction of cosmic rays thermal neutron, it is also known as SEU ( single event upset). The concept of critical charge is used to estimate SEU. Soft error vulnerability is used to analyse it which is performed on FinFET and on CMOS logic.[2] 2. Leakage current: It was one of the main issue in MOSFET which was overcome by FinFET as it less down the leakage current by 90% and also increases its speed by 37%.[3] 3. Temperature: Ion which is also known as the driving current is responsible for delay, when Ion increases the switching of logic gates gets faster. When MOSFET operates at subthreshold (Vdd) , which results in rise in temperature and lowering down Ion. But in FinFET, when it work at subthreshold it shows opposite behaviour then that of MOSFET which means when temperature rises Ion decreases [4]-[6]

Advantages: 1. Better control over channel 2. It lowers the short channel effect. 3. It reduces the static leakage current. 4. It has high drain current. Disadvantages: 1. It has high parasitic capacitance due to its 3d structure.

International Journal of Advance Science and Technology Vol. 29, No. 10S, (2020), pp. 1928-1932

2. Have high parasitic resistance due to local interconnect. 3. It has corner effect.

Future scope: Future scope of FinFET technology is to scale down the gate to 10nm and similarly improve the utility of the device. It is great thing to mention that 10nm is the size of virus, so the future research is going on to make it even smaller.

References: [1] Alireza Shafaei, Yanzhi Wang, Xue Lin, and MassoudPedram , “FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-scaled FinFET Devices”, Los Angeles, CA 90089.

[2] Feng Wang*, Yuan Xie*, Kerry Bernstein† ,Yan Luo‡, “Dependability Analysis of Nano- scale FinFET circuits”, The Pennsylvania State University,University Park, PA, 16802 † IBM T.J. Watson Research Center, Yorktown Heights, NY, 10598, USA ‡ Silicon Engineering Group, Synopsys .Inc, Shanghai, China.

[3] Girish H, J C BOSE, Shashikumar D. R., “Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells”, Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 5 – No.6, July 2016.

[4] Woojoo Lee, Yanzhi Wang, Tiansong Cui, Shahin Nazarian and MassoudPedram, “Dynamic Thermal Management for FinFET-Based Circuits Exploiting the Temperature Effect Inversion Phenomenon”, University of Southern California, CA, USA, Proceeding of the 2014 international symposium on low power electronics and design-ISLPED 14.

[5] Vita Pi-Ho Hu, , Ming-Long Fan, Chien-Yu Hsieh, Pin Su, and Ching-Te Chuang, “FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 3, MARCH 2011.

[6] Ravindra Singh Kushwah* and ShyamAkashe, “FinFET-based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect”, Department of Electronics & Communication, Institute of Technology and Management University, Gwalior 474001, MP, India, Int. J. Signal and Imaging Systems Engineering, Vol. 8, No. 6, 2015.

[7] Giovanni Crupi a,⇑ , Dominique M.M.-P. Schreurs b , Jean-Pierre Raskin c , Alina Caddemi, “A comprehensive review on microwave FinFETmodeling for progressing beyond the state of art”, Received 13 July 2012 Received in revised form 28 September 2012 Accepted 28 October 2012 Available online 21 December 2012 The review of this paper was arranged by Prof. A. Zaslavsky.

[8] Olivier Bonnaud, Laurent Fesquet, “Trends in Nanoelectronic Education From FDSOI and FinFET Technologies to Circuit Design Specifications”, IETR UMR 6164, University of Rennes I 3 parvis Louis Neel 38016 Grenoble Cedex, France, CIME Nanotech, University of Grenoble Alpes 3 parvis Louis Neel 38016 Grenoble Cedex, France.

[9] Xinfei Guo∗, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, and Mircea R. Stan, “Back to the Future: Digital Circuit Design in the FinFET Era”, Department of

International Journal of Advance Science and Technology Vol. 29, No. 10S, (2020), pp. 1928-1932

Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, 22904, USA, Journal of Low Power Electronics Vol. 13, 1–18, 2017.

[10] Shweta Kataria , Poonam Beniwal, “FinFET Technology: A Review Paper”, 1MTech Scholar, 2Assistant Professor, Department of Electronics and Communication, Om Institute of Technology & Management, Hisar Haryana”, International Journal of Technical Research (IJTR) Vol. 5, Issue 2, July-Aug 2016.