International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com
Commencing from MOSFET to FinFET Technology: A Short Review
Prof. Rajashri K. Patil Dr. D. Y. Patil College of Engineering, Ambi, Pune [email protected]
Abstract: Now days we can observe that the size of various high density of logic functions on a chip. This made the integrated electronic devices are reducing. More or less all CMOS an adorable technique for the use in IC electronic devices use MOSFET as a main component. The Technique. The past 3 decades CMOS IC technologies reduction in size is because we scale down various parameters have been scaled down continuously and entered into the of MOSFET. As we scaled down the MOSFET to nanometer nanometer region for various applications. [2] scale , it causes various effects called as short channel effects like DIBL, surface scattering, velocity saturation, impact Long channel MOSFET devices are an excellent means ionization etc. arises which degrades the performance and of describing how MOSFET works. They are rarely used reliability of MOSFET and thus device. nowadays. In order to increase the number of active In view of difficulties of the planar MOSFET, in order to get devices on a chip and thus to improve the functionality, the acceptable gate control over the channel, to reduce short MOSFET devices have undergone continuous channel effects, FinFET technology can be a better option. miniaturization. There are many complication arises It’s a technology which uses more than one gate, called as when MOSFET devices are miniaturized. These multiple gate devices, is an enhanced technology option for complications can be summarized from material to further shrinking the size of the planar MOSFET. For double processing problems. gate SOI- MOSFET the gates control the channel which is formed between source and drain terminal effectively. So the several short channel effects get reduced without increasing the carrier concentration into the channel. Short Channel Effects (SCEs) which are difficult to suppress. Multi-gate MOSFET technology mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. This paper gives detail description about the short channel effects which are caused by scaling of MOSFET. Also describe the alternative MOSFET called FinFET which Fig. 1. Long and Short Channel of MOSFET reduces the short channel effects, its structure and its particular type named as FinFET technology. MOSFET device is considered as short channel when the channel length is the same order of as channel length L, is Keywords: Scaling, Short Channel Effect, DG MOSFET, reduced to increase both the operation speed and the FinFET. number of components per chip, so short channel effects I. INTRODUCTION arises due to short channel length means depletion width st between source and drain. Short channel MOSFET has During the first decade of 21 century there were many good processing speed, requires low operating potential noteworthy advances in nanoelectronics materials. We and increases transistor density on the chip. know that in 1965 Gordon Moore predicted that the number of transistor on a device would quadruple every As we are scaling down the size of MOSFET, channel three years. The channel length which is a significant length of the device shrinks and this closeness between dimension has been shrinking continuously and will source and drain reduces effect of gate voltage on continue to decreasing. The speed of the FET went up potential distribution and current flow in the channel, while the area occupied by the device and power used by which degrade the performance of the device. This causes the device went down, so that the power density remained instability in the structure when we scaled down constant. [6] MOSFET to nanometers. This happens mainly due to short channel effects (SCEs) which play a key role in CMOS is a technology use extensively for building ICs determining the performance of scaled devices. because it provides high noise immunity and low static power dissipation. In CMOS devices, power is basically Although the performance degrades with decrease in used in switching process. Also CMOS devices do not channel length as the device dimension shrink, it is ever produce thermal noise as other forms of logic, for more difficult to perform the basic device fabrication example Transistor-Transistor Logic (TTL). It allows a steps like in lithography, interconnects and processing. 40
International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com
As device dimension becomes smaller, circuit becomes denser and more complex. II. SUBSTANTIAL ERRORS IN DOWNSCALING OF MOSFET DEVICES The class of effects that alter device behavior that arise from device miniaturization are generally referred to as short channel effects. These results in increasing the leaking current between the drain - source and reduces Fig. 3 (a). Surface Scattering in Channel Region ON state to OFF state ratio of current. In particular following short channel effects can be distinguished a. Drain Induced Barrier Lowering (DIBL): In small geometry MOSFET, potential barrier is controlled by both Vgs and Vgs. If Vds increases, this reduces the barrier by electron or holes in the source allowing them to go from source and drain where the gate voltage remains unchanged. Potential barrier in channel decreases, leading DIBL. The reduction of potential barrier eventually allows electron flow between source Fig. 3 (b). Surface Scattering in Channel Region and drain, even if Vgs
International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com
Secondary holes are collected at substrate causing to We know that relation between natural length of device 2 si increase latch up and number of gates n, is given as: = tox , where n ox n is number of gates, si - permittivity of Si, ox - permittivity of oxide, tox -thickness of Si body and oxide respectively [11]. When supply voltage Vdd is reduced, hot carrier effect and power get reduced but the performance enhancement is not good but it can be improved by reducing threshold voltage V . T Researcher are on search to find high-k gate dielectric so Fig. 5. Impact Ionization that a thicker physical oxide can be used help to reduce gate leakage and yet have adequate channel control, but e. Velocity Saturation: this is not successful at the point of being usable. Upto certain point velocity is directly proportional to the The thermal instability problem has led researchers to electric field. But after the point velocity saturates and search for metal gate electrodes instead of polysilicon. has no effects of increase in electric field. This reduces But metal gates with suitable work functions have not transconductance in the saturation mode been found to the point of being usable. In the absence of f. Parasitic Resistances and Capacitances: this, polysilicon continues to be used, whose work function require that VT be set by high channel doping
As transistor dimensions are shrinked parasitic concentration which in turn leads to random dopant resistances and capacitances both scale unfavorably with fluctuations (at small gate lengths) as well as increased reduced field. Therefore, influence of parasitic elements impurity scattering and therefore reduced mobility [12]. on on-current increases considerably. These parasitic elements will diminish the performance gain by transistor Due to short channel length, off state leakage current and scaling. power are increasing so its difficult to keep electrostatic integrity of the devices. Fully-depleted devices, double- g. Heat Dissipation: gate devices in particular, offer significantly better electrostatic integrity and hence, better short-channel MOSFETs release energy in the form of heat in the immunity [13]. resistive parts. If this heat is not dissipated properly, then hot spots are created on the circuit, which finally Adding up to excellent channel control, the FinFET resulting in malfunction of device. transistors also offer approximately twice the on-current compare to the planar MOSFETs because of the dual Thus as devices get shrink more, the problem with gates, even without increasing channel doping. This is conventional MOSFETs are increasing [1]. Solving one beneficial for the carrier mobility and results in a low gate problem leads to another. Short channel effects problems leakage at the same time [14]. such as VT roll off, drain induced barrier lowering (DIBL), increasing leakage current and so on. To solve a) DG – MOSFET Structure: these short channel effects problem quite a lot of MOSFET has been introduced such as double gate, Currently standard CMOS technology can be replaced by FinFET, Tri-gate, Fore-gate, all-around gate and so on DG MOSFETs technology to raise the integration [1]. capacity of silicon technology in the near future. A DGSOI Structure consists, basically, of a silicon slab III. FinFET sandwiched between two oxide layers as illustrated in Fig.6 Double gate MOSFET is an alternate rising device to overcome all problems occurred MOSFET with single The salient features of the DG MOSFETs are control of gate. This new architecture will aid us to maintain the short-channel effects by device geometry, as compared to Moore's law research going towards inventions of novel bulk FETs, where the short-channel effects are controlled devices [7]-[10] The predictions of International by doping concentration; and a thin silicon channel Technology Roadmap for Semiconductors (ITRS) are leading to tight coupling of the gate potential with the followed by the device designers to propose various channel potential. novel device structures and process parameter variations [5]. 42
International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com
Fig. 8. FinFET Fabrication [12] V. CHARACTERISTICS OF FinFET Fig. 6. FinFET Structure [15] Now we discuss electrostatic characteristic of FinFET IV. TYPES OF FinFET (Current–voltage).The unique characteristic of the FinFET is that the gate is formed by conducting channel Basically there are 2 types of DG-FETs: which is enclosed by a thin silicon "fin”. The thickness of a. Symmetric: the fin is measured in the direction from source to drain which determines the effective channel length of the In Symmetric DG-FETs have identical gate electrode device. materials for the front and back gates means gate electrode material is same for both gate. When The gate electrode is wrapped around the channel, so that symmetrically driven, the channel is formed at both the there can be formed several gate electrodes on each side surfaces. which leads to the reduction in the leakage currents and an enhances drive current b. Asymmetric: Theory: MOSFET characteristics are expressed as In an asymmetric DG-FET, the top and bottom gate functions of the values of the surface potential at the electrode materials can different. Channel is formed only source and drain ends. in one surface [4]. In the threshold voltage approach separate solutions are In the Fig.7 9(a) and (b) it is shown that there are three available for different regions of MOSFET operation (Fig ways to fabricate the DG-FET. 9). For FinFET Figure 9 consists of a vertical Si fin controlled by self aligned double gate. Linear Region: It is the region in which Ids, increases linearly with Vds, for a given 푉𝑔 > 푉푡ℎ To a first approximation, Ids, in the linear region is given 2휇퐶표푥푊 푉푑푠 퐼푑푐 = 푉𝑔 − 푉푡ℎ − 푉푑푠 퐿 2 where μ is mobility of the carriers in the inversion region i.e. channel, Cox is the gate oxide capacitance per unit area, W/L is device width to length ratio and Vth is threshold voltage. Fig. 7 (a) Type -1 Planar DG-FET (b) Type-2 Vertical Saturation Region: In this region Ids becomes constant DG-FET [16] even though Vds increases. Once more to a first rough calculation, Ids in the saturation region is Types 1 and 2 suffer most from fabrication problems, like it is tough to fabricate gates of same size and that gates should be exactly aligned with each other and it is hard to align the source/drain regions accurately to the edges of gate electrode. Further, in Type 1 DG-FETs, as this type uses buried contact, it is hard to provide a low-resistance, area-efficient contact the bottom gate. The FinFET which is shown in Fig 8 is the easiest to fabricate. Fig. 9. FinFET details [4] 43
International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com
given by by using FinFET. This could increase the speed of W vg −vt 푡표푥 operation and provides better control over the channel 퐼푑푠 = μCox ( )^2 푚 = 1 + 3 L 2m 푥푑 and reduces power consumption. 푥푑 is the depletion layer thickness and is the oxide This paper gives details about the short channel effects thickness showing that Ids, does not depend on Vds which are generated after scaling and an insight knowledge of FinFET To summarize, in FinFET due to dual gate structure it has better controlling over several short channel effect such as V roll off, DIBL, sub threshold swing, gate direct T tunneling leakage and hot carrier effects compare to the planner MOSFET FinFET has higher integration density compare to the planner MOSFET. FinFET technology is a good alternative to planar MOS for scaling
VIII. EFERENCES Fig. 10. Structure of FinFET R Cut-Off Region: In this region Vg< Vth so that no [1] Shivani Chopra1 and Subha Subramaniam,A channel exist between source and drain, resulting in Review on Challenges for MOSFET Scaling, Ids=0. In fact for Vg< Vth, sub threshold current flows, IJISET - International Journal of Innovative which is exponential decay current. Science, Engineering & Technology, Vol. 2 Issue 4, April 2015.ISSN 2348 – 79681055. The low electron concentration results in low electric field along the channel and as a result the sub-threshold [2] Raju Hajare,Sunil C,Anish Kumar A R, Sumanth current is primarily owing to diffusion of carriers. The Jain P R, Sriram AS, Performance Analysis of current in this region is approximated as FinFET Based Inverter circuit, NAND and NOR Gate at 22nm and 14nm Node technologies, W Vg −∆∅ Vds International Journal on Recent and Innovation Ids = µ kT ήi tsi eq (1 − eq L kT kT Trends in Computing and Communication ISSN: Δφ is the work function difference between the gate 2321-8169 Volume: 3 Issue: 5 2527 – 2532, electrode and the almost intrinsic silicon body. [4] IJRITCC | May 2015. [3] Harsh Vardhan, “Effects of Gate Length and Oxide VI. FEATURES OF FinFET Thickness on DG-MOSFET” International Research Most important Features of FinFET are: Journal of Engineering and Technology (IRJET) e- ISSN: 2395-0056 Volume: 02 Issue: 08 | Nov-2015. Ultra thin Si fin for suppression of short channel effects. [4] Tushar Surwadkar, swapnali Makdey, Deepak, Upgrading the Performance of VLSI Circuits using Raised source/drain to reduce parasitic resistance and FinFETs, International Journal of Engineering improve current drive. Trends and Technology (IJETT) – Volume 14 Symmetric gates yield great performance, but can Number 4 – Aug 2014 ISSN: 2231-5381.
built asymmetric gates that target VT. [5] Sarman K Hadia, Rohit R. Patel, Dr. Yogesh P. FinFETs are designed to use multiple fins to achieve Kosta, FinFET Architecture Analysis and larger channel widths. Source/Drain pads connect the Fabrication Mechanism, IJCSI International Journal fins in parallel. As the number of fins is increased, the of Computer Science Issues, Vol. 8, Issue 5, No 1, current through the device increases. September 2011 ISSN. The main advantage of the FinFET is the ability to [6] Yong-Bin Kim, Review Paper: Challenges for drastically reduce the short channel effect.[4] Nanoscale MOSFETs and Emerging Nanoelectronics , Trans. Electr. Electron. Mater. VII. SUMMARY 10(1) 21 (2009): G.-D. Hong et al. 23. Due to scaling of MOSFET various short channel effects are generated. The device performance may be improved 44
International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com
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