International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com Commencing from MOSFET to FinFET Technology: A Short Review Prof. Rajashri K. Patil Dr. D. Y. Patil College of Engineering, Ambi, Pune [email protected] Abstract: Now days we can observe that the size of various high density of logic functions on a chip. This made the integrated electronic devices are reducing. More or less all CMOS an adorable technique for the use in IC electronic devices use MOSFET as a main component. The Technique. The past 3 decades CMOS IC technologies reduction in size is because we scale down various parameters have been scaled down continuously and entered into the of MOSFET. As we scaled down the MOSFET to nanometer nanometer region for various applications. [2] scale , it causes various effects called as short channel effects like DIBL, surface scattering, velocity saturation, impact Long channel MOSFET devices are an excellent means ionization etc. arises which degrades the performance and of describing how MOSFET works. They are rarely used reliability of MOSFET and thus device. nowadays. In order to increase the number of active In view of difficulties of the planar MOSFET, in order to get devices on a chip and thus to improve the functionality, the acceptable gate control over the channel, to reduce short MOSFET devices have undergone continuous channel effects, FinFET technology can be a better option. miniaturization. There are many complication arises It’s a technology which uses more than one gate, called as when MOSFET devices are miniaturized. These multiple gate devices, is an enhanced technology option for complications can be summarized from material to further shrinking the size of the planar MOSFET. For double processing problems. gate SOI- MOSFET the gates control the channel which is formed between source and drain terminal effectively. So the several short channel effects get reduced without increasing the carrier concentration into the channel. Short Channel Effects (SCEs) which are difficult to suppress. Multi-gate MOSFET technology mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. This paper gives detail description about the short channel effects which are caused by scaling of MOSFET. Also describe the alternative MOSFET called FinFET which Fig. 1. Long and Short Channel of MOSFET reduces the short channel effects, its structure and its particular type named as FinFET technology. MOSFET device is considered as short channel when the channel length is the same order of as channel length L, is Keywords: Scaling, Short Channel Effect, DG MOSFET, reduced to increase both the operation speed and the FinFET. number of components per chip, so short channel effects I. INTRODUCTION arises due to short channel length means depletion width st between source and drain. Short channel MOSFET has During the first decade of 21 century there were many good processing speed, requires low operating potential noteworthy advances in nanoelectronics materials. We and increases transistor density on the chip. know that in 1965 Gordon Moore predicted that the number of transistor on a device would quadruple every As we are scaling down the size of MOSFET, channel three years. The channel length which is a significant length of the device shrinks and this closeness between dimension has been shrinking continuously and will source and drain reduces effect of gate voltage on continue to decreasing. The speed of the FET went up potential distribution and current flow in the channel, while the area occupied by the device and power used by which degrade the performance of the device. This causes the device went down, so that the power density remained instability in the structure when we scaled down constant. [6] MOSFET to nanometers. This happens mainly due to short channel effects (SCEs) which play a key role in CMOS is a technology use extensively for building ICs determining the performance of scaled devices. because it provides high noise immunity and low static power dissipation. In CMOS devices, power is basically Although the performance degrades with decrease in used in switching process. Also CMOS devices do not channel length as the device dimension shrink, it is ever produce thermal noise as other forms of logic, for more difficult to perform the basic device fabrication example Transistor-Transistor Logic (TTL). It allows a steps like in lithography, interconnects and processing. 40 International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com As device dimension becomes smaller, circuit becomes denser and more complex. II. SUBSTANTIAL ERRORS IN DOWNSCALING OF MOSFET DEVICES The class of effects that alter device behavior that arise from device miniaturization are generally referred to as short channel effects. These results in increasing the leaking current between the drain - source and reduces Fig. 3 (a). Surface Scattering in Channel Region ON state to OFF state ratio of current. In particular following short channel effects can be distinguished a. Drain Induced Barrier Lowering (DIBL): In small geometry MOSFET, potential barrier is controlled by both Vgs and Vgs. If Vds increases, this reduces the barrier by electron or holes in the source allowing them to go from source and drain where the gate voltage remains unchanged. Potential barrier in channel decreases, leading DIBL. The reduction of potential barrier eventually allows electron flow between source Fig. 3 (b). Surface Scattering in Channel Region and drain, even if Vgs<Vth. c. Hot Electron Effect: When the depletion region surrounding the drain extends When carriers acquire high energies having effective to source, so that the two depletion layer merge, punch temperature greater than the lattice temperature, they are through occurs. Gate losses the control of flow of current said to be hot. These hot electrons are generated in through MOSFET and become as good as redundant. inverted channel region when MOSFET is operating in Punch through can be minimized with thinner oxide, linear or saturation mode. larger substrate doping, shallower junctions and obliviously longer channel. These hot electrons cannot transfer their energies to the lattice atoms fast enough. The main problems which arise due to hot carriers are parasitic gate currents, drain current degradation, decrease in transconductance and shift of threshold voltage with time. Using graded drain profile reduces generation of hot carriers [4]. The technique is used in floating gate devices to increase the threshold by trapping the electrons in floating gate. To reduce this effect drain is lightly doped, resulting in less electric field created for carriers. Fig. 2. Drain Induced Barrier Lowering b. Surface Scattering: In long channel, Ex>> Ey, but in short channel Ex is not negligible. Ex and Ey field makes electron to travel in zigzag path, reducing their mobility. As channel length becomes shorter, Ey (longitudinal electric field component) increases causing surface mobility to become field dependent. As the channel length becomes smaller due to lateral Fig. 4. Hot Carrier Effect extension of depletion layer into channel region, the d. Impact Ionization: longitudinal electric field component increases and surface mobility becomes field dependant Electron travelling to the drain creates electron-hole pair by impact ionization. Secondary electrons which are collected at drain causes current to increase in saturation. 41 International Journal of Electrical Electronics & Computer Science Engineering Volume 5, Issue 3 (June, 2018) | E-ISSN : 2348-2273 | P-ISSN : 2454-1222 Available Online at www.ijeecse.com Secondary holes are collected at substrate causing to We know that relation between natural length of device 2 si increase latch up and number of gates n, is given as: = tox , where n ox n is number of gates, si - permittivity of Si, ox - permittivity of oxide, tox -thickness of Si body and oxide respectively [11]. When supply voltage Vdd is reduced, hot carrier effect and power get reduced but the performance enhancement is not good but it can be improved by reducing threshold voltage V . T Researcher are on search to find high-k gate dielectric so Fig. 5. Impact Ionization that a thicker physical oxide can be used help to reduce gate leakage and yet have adequate channel control, but e. Velocity Saturation: this is not successful at the point of being usable. Upto certain point velocity is directly proportional to the The thermal instability problem has led researchers to electric field. But after the point velocity saturates and search for metal gate electrodes instead of polysilicon. has no effects of increase in electric field. This reduces But metal gates with suitable work functions have not transconductance in the saturation mode been found to the point of being usable. In the absence of f. Parasitic Resistances and Capacitances: this, polysilicon continues to be used, whose work function require that VT be set by high channel doping As transistor dimensions are shrinked parasitic concentration which in turn leads to random dopant resistances and capacitances both scale unfavorably with fluctuations (at small gate lengths) as well as increased reduced field. Therefore,