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Design and Computer Aided Optimization of a Fully Integrated CMOS RF Distributed Amplifier

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Design and Computer Aided Optimization of a Fully Integrated CMOS RF Distributed Amplifier AN ABSTRACT OF THE THESIS OF Brian M. Ballweber for the degree of Master of Science in Electrical and Computer Engineering presented on November 13, 1998. Title: Design and Computer Aided Optimization of a Fully Integrated CMOS RF Distributed Amplifier. Redacted for Privacy Abstract approved: David J. Alistot Advancements in the sophistication and complexity of modern electronic sys­ tems are creating a need for highly integrated systems with ever higher operational fre­ quencies. The economical demands of these systems dictate that they be implemented using low cost fabrication technologies, such as digital CMOS. One of the major chal­ lenges facing circuit designers is the difficulty in implementing high frequency RF ana­ log circuits on these types of technologies. Analog circuits which make use of parasitic-laden components such as inductors are especially difficult to realize. The purpose of this thesis is to investigate the design and application of an opti­ mization tool based on simulated annealing to this type of problem. The goal is to have the optimizer incorporate these unavoidable component parasitics into a design, and thus eliminate any undesirable performance degradation. The optimization technique will be applied to the design of a CMOS RF distrib­ uted amplifier. This type of amplifier has a flat gain characteristic over an exceptionally wide bandwidth, and it is heavily reliant on inductive structures. Historically, an ampli­ fier of this type has never been implemented on a standard CMOS process, without the use of bondwire inductances or special processing techniques. However, it will be shown in this thesis that, with the aid of the optimization technique, a distributed ampli­ fier design can be successfully realized on a standard CMOS process. Design and Computer Aided Optimization of a Fully Integrated CMOS RF Distributed Amplifier by Brian M. Baliweber A THESIS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science Completed November 13, 1998 Commencement June 1999 Master of Science thesis of Brian M. Ballweber presented on November 13, 1998 APPROVED: Redacted for Privacy Major Professor, representing Electrical & Computer Engineering Redacted for Privacy Head of Department of Electrical & Computer Engineering Redacted for Privacy Dean of Graduat chool I understand that my thesis will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my thesis to any reader upon request. Redacted for Privacy Brian M. Ballweber, Author ACKNOWLEDGMENTS I would like to acknowledge a number of people who had a significant influence on this thesis, as well as me personally during my studies at Oregon State University. I would first like to thank my advisor, David J. Allstot, for his support and encourage­ ment throughout the progression of this work. His instruction and guidance were what first set me down the path of analog circuit design, and for that I am very grateful. I would like also to thank Professor Andreas Weisshaar, Professor Ben Lee, and Professor David McIntyre for reviewing my thesis, and taking the time to serve on my graduate committee. I extend many thanks to my friends and colleagues in the analog and mixed-sig­ nal group at Oregon State University. I thank Ramsin Ziazadeh for his friendship and unswerving optimism when I questioned the outcome of this project. Ravi Gupta and Jianjun Zhou also provided me with a number of insights and extensive technical help throughout the course of the project, and for that I thank them. I thank also Rick Lutz for his extensive help in acquiring detailed measurement results. I would also like to thank fellow group members Hiok-Tiaq Ng, and Hiok-Hion Ng for their friendship and helpful discussions. Finally, I owe perhaps the largest amount of gratitude to my parents, Donald and Kathleen Ballweber, for their endless love, support, and guidance, without which this work never would have been possible. TABLE OF CONTENTS Page Chapter 1. Introduction to Distributed Amplification 1 1.1 Principle of Distributed Amplification 3 1.2 Distributed Amplifier Design Optimizations 9 1.2.1 Staggering 10 1.2.2 M-Derived Transmission Line Sections 12 1.2.3 Bridged T-Network 15 1.2.4 M-Derived Half Section Terminations 16 1.2.5 Gate Series Capacitor 19 1.2.6 Increased Sections 20 1.2.7 Additional Techniques 21 1.3 Introduction to Distributed Amplification Summary 22 Chapter 2. Distributed Amplifier Design 24 2.1 CMOS Design Procedure 25 2.2 Distributed Amplifier Design Summary 35 Chapter 3. Computer Aided Optimization 37 3.1 Inductor Modeling 38 3.1.1 Determining Optimum Metal Geometry for an Inductor 40 3.1.2 Inductor Simulation using a Planar Electromagnetic Simulator 46 3.1.3 Integration of Inductor Models with Optimizer 59 3.2 Simulated Annealing 62 3.3 Application of Simulated Annealing to Distributed Amplifier Design 65 3.3.1 Cooling Schedule 68 3.3.2 Cost Function 69 3.3.3 File Manipulation and HSpice Interaction 73 3.4 Distributed Amplifier Simulated Annealing Program 75 3.5 Computer Aided Optimization Summary 79 TABLE OF CONTENTS (Continued) Page Chapter 4. Simulation and Measurement 80 4.1 Design Changes due to Simulated Annealing Results and Physical Constraints 80 4.2 Final Amplifier Design 89 4.2.1 Final Design #1 91 4.2.2 Final Design #2 96 4.3 Design Layout and Packaging 100 4.4 Measurement Results 107 4.4.1 Measurements for Amplifier Design #1 108 4.4.2 Measurements for Amplifier Design #2 112 4.5 Simulation and Measurement Summary 119 Chapter 5. Conclusion 124 Bibliography 129 Appendices 132 LIST OF FIGURES Figure Page 1.1 Basic Distributed Amplifier 4 1.2 Constant-K Sections; T-Section (a), Pi-Section (b) 5 1.3 Two-Port Network Terminated in its Image Impedances 5 1.4 Normalized Forward and Reverse Gain Versus Frequency for 7-Section Amplifier 7 1.5 Unilateral Model of Basic Distributed Amplifier 8 1.6 Phase Characteristics Illustrating Improvement from Staggering (Arbitrary Scales) 12 1.7 M-Derived Sections; Amplifier Implementation (a), Equivalent Circuits (b) 13 1.8 Relative Gain Characteristic of Distributed Amplifier with m-Derived Sections 15 1.9 Bridged T-Network with Equivalent Circuit 16 1.10 Image Impedances for Constant-K Section with Resistive Termination 17 1.11 M-Derived Half Circuit Termination with m = 0.6 18 1.12 Distributed Amplifier Section with Gate Series Capacitor 19 2.1 Distributed Amplifier with m-Derived Half Section Terminations 26 2.2 Gate Line (a) and Drain Line (b) Sections Including Losses 27 2.3 Optimum Number of Sections Versus Frequency 29 2.4 Initial Analytically Derived Circuit Schematic 31 2.5 Gain and Phase Response for Initial Circuit 31 2.6 Revised Analytically Derived Circuit Schematic 32 2.7 Gain and Phase Response for Revised Circuit 33 2.8 Amplifier Response with Ideal Components (-) and Losses (--) 34 3.1 Inductance Value Versus Geometry 42 3.2 Target Inductance Value (4.25 nH) Versus Geometry 43 LIST OF FIGURES (Continued) Figure Page 3.3 Parasitic Resistance (a) and Capacitance (b) Estimates Versus Target Inductance Geometry; Dashed Line Indicates Overall Trend (- -) 43 3.4 Example 3.25 nH Inductor Layout (a), and Real (b), and Imaginary (c) One Port Impedance 46 3.5 Initial Momentum Substrate Definition 47 3.6 Revised Momentum Substrate Definition 48 3.7 Real (a) and Imaginary (b) One-Port Impedance for 5.25 Turn, 6.1 nH Inductor; Measured Data (-), Initial Momentum Substrate (- -), and Revised Momentum Substrate (- .) 49 3.8 Real (a) and Imaginary (b) One-Port Impedance for 7.25 Turn, 12.6nH Inductor; Measured Data (-), Initial Momentum Substrate (--), and Revised Momentum Substrate (- .) 50 3.9 Black Box T-Section Model with Frequency Dependent Components 52 3.10 T-Section Model with Real and Reactive Frequency Dependent Components 53 3.11 Momentum S-Parameters (A) and HSpice Simulation Results (-) Using Fitted T-Section Model 55 3.12 Momentum Z-Parameters (A) and HSpice Simulation Results (-) Using Fitted T-Section Model 56 3.13 Generated Frequency Dependent T-Section Model; Schematic and HSpice Net list 57 3.14 Real and Imaginary Impedance of T-Section Shunt Branch; Momentum Data (A) and Fitted Parameter Data (-) 58 3.15 Real and Imaginary S12 Parameter; Momentum Data (A) and HSpice Simulation Data (-) 58 3.16 Inductor Model as a Function of Inductance and Frequency 60 3.17 Coefficients for Component C3 as a Function of Inductance; Momentum Data (A) and Mat lab Polyfit (-) 61 3.18 General Simulated Annealing Algorithm 65 3.19 Simulated Annealing Optimizer Block Diagram 67 LIST OF FIGURES (Continued) Figure Page 3.20 Example Lines from Optimization Files; HSpice Input File "input.sp" (a), Include File "param.inc" (b), and Annealer Configuration File "annealer.cf' (c) 73 3.21 Amplifier Schematic with Simulated Annealing Variables 76 3.22 Distributed Amplifier Simulated Annealing Program 78 4.1 Initial Simulated Annealing Design with Independent Variables 82 4.2 Initial Simulated Annealing Run for Analytically Derived Design 83 4.3 Gain Response Before (- -) and After (-) Initial Simulated Annealing Run 83 4.4 Inductance Changes in LG2L (a) and LD2R (b) During Simulated Annealing Run 84 4.5 Capacitance Changes in CD During Simulated Annealing Run 85 4.6 Estimated Lead Frame and Bond Wire Package Parasitics for Center Pins (a), and Corner Pins (b) 86 4.7 Integrated Drain Line Bias Network 88 4.8 Final Distributed Amplifier Design with Simulated Annealing Variables 89 4.9 Final Design #1 92
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