A CMOS Distributed Amplifier with Distributed Active Input Balun Using

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012 1331 A CMOS Distributed Amplifier With Distributed Active Input Balun Using GBW and Linearity Enhancing Techniques Amin Jahanian, Member, IEEE, and Payam Heydari, Senior Member, IEEE Abstract—ACMOSdistributedamplifier (DA) with distributed transmission lines (t-lines) to improve efficiency for power am- active input balun is presented that achieves a gain-bandwidth plifiers. In [6], t-line tapering and -derived terminations are product of 818 GHz, while improving linearity. Each cell used in a multistage DA to improve BW. A distributed low- within the DA employs dual-output two-stage topology that im- proves gain and linearity without adversely affecting bandwidth noise amplifier (DLNA) is designed for minimum noise figure (BW) and power. Comprehensive analysis and simulations are (NF) for ultra-wideband (UWB) applications in [7]. Reference carried out to investigate gain, BW, linearity, noise, and stability [13] uses differential stages, incorporating cross-connected of the proposed cell, and compare them with conventional capacitive neutralization, distributed along nonuniform down- cells. Fabricated in a 65-nm low-power CMOS process, the sized artificial lines to improve BW. A DA with gain stages 0.9-mm DA achieves 22 dB of gain and a of 10 dBm, while consuming dc power of 97 mW from a 1.3-V supply. A distributed comprising input emitter followers and output cascode stages is balun, designed and fabricated in the same process, using the implementedinanSiGebipolartechnology in [14]. same topology achieves a BW larger than 70 GHz and a gain Besides distributed amplification, many broadband amplifiers of 4 dB with 19.5-mW power consumption from 1.3-V supply. using other methods have been proposed, as well [16]–[20]. In Index Terms—Active balun, bandwidth (BW) compensation, [16], a low-frequency amplifier and a high-frequency tuned am- BW enhancement, CMOS, coplanar waveguide (CPW) transmis- plifier are cascaded to design a broadband amplifier. Impedance- sion line (t-line), distributed amplifier (DA), gain BW, linearity. tuned cascaded emitter–follower drivers have been utilized in an SiGe bipolar technology in [17] and [18] to increase BW I. INTRODUCTION of cascode-based lumped amplifiers, while increasing dc power consumption. A synthesis-based BW enhancement technique is presented in [19] that brings bandwidth enhancement ratio ISTRIBUTED amplifiers (DAs) have been used exten- (BWER) of CMOS amplifiers close to its theoretical limit. In sively for broadband wired/wireless applications. Various D [20], asymmetric transformer peaking was applied to cascaded techniques, examined in different technologies, have been pro- common-source (CS) CMOS stages to enhance BW. posed by prior work to improve DA performance parameters Distributed circuits are also implemented in the context of such as gain, bandwidth (BW), and power [1]–[15]. In [1], mul- active single-to-differential conversion (i.e., active baluns). Im- tistage cells are used to improve gain, while interstage induc- plemented using either active or passive components, baluns are tive peaking is employed to compensate for the BW degradation useful for various applications, such as broadband wired con- due to interstage poles of the cell. Reference [2] uses cas- nectivity and high-frequency general-purpose test and measure- caded DAs to improve gain, while sacrificing high-frequency ment equipment. Active baluns offer the advantage of achieving matching by removing the backward-propagation resistive ter- voltage and power gain of higher than (or around) unity, as mination of the drain line. Reference [3] uses feedback to double well as a higher reverse isolation over their passive counter- gain, while increasing the lower corner frequency to 12 GHz. In parts. Several active baluns have been proposed in the liter- [4], a series capacitor at the input of the cell is introduced, ature. One solution is to use a differential pair stage with a which trades gain for BW. Reference [5] employs nonuniform single-ended signal applied to one input transistor’s gate (or base) terminal, while ac grounding the other one [21]–[24]. An- Manuscript received September 28, 2011; revised November 22, 2011; ac- other candidate utilizes the 180 phase shift between the outputs cepted November 29, 2011. Date of publication February 06, 2012; date of cur- rent version April 27, 2012. This work was supported in part by the National of a common-gate–common-source (CG–CS) pair [25]–[28] to Science Foundation (NSF) CAREER Grant under Contract ECS-0449433 and realize differential output. An issue with the CG–CS topology by Mindspeed Technologies. This paper is an expanded paper from the IEEE is incompatible input impedances of the two stages (i.e., capaci- RFIC Symposium, June 5–10, 2011, Baltimore, MD. A. Jahanian was with the Nanoscale Communication Integrated Circuit tive input for CS and resistive input for CG). This issue is (NCIC) Laboratory, Electrical Engineering and Computer Science Department, addressed in [29] by adding a CS-connected transistor with its University of California at Irvine, Irvine, CA 92697-2625 USA. He is now with gate terminal connected to the input and its drain terminal con- Qualcomm Atheros Inc., Irvine, CA 92618 USA (e-mail: [email protected]). P. Heydari is with the Electrical Engineering and Computer Science Depart- nected to the input node of the CS-CG pair. The original CG–CS ment, University of California at Irvine, Irvine, CA 92697-2625 USA (e-mail: topology has been incorporated into the distributed architecture [email protected]). [30]. In [31], CS gain stages are used and differential outputs Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. are taken from far-end gate and drain t-line terminations. Two Digital Object Identifier 10.1109/TMTT.2012.2184134 DAs (each with inverting CS gain stages) are cascaded and their 0018-9480/$31.00 © 2012 IEEE 1332 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012 Fig. 2. of the proposed stage and its relative improvement versus of a single stage. , as in Fig. 1(b), to introduce an additional signal path. Tran- sistor acts as a cascode device for the new signal path, while behaving similar to a resistive load (with for the first stage of the two-stage path. Assuming that the output signals and are summed constructively (as will be shown below), the overall transcon- Fig. 1. (a) Two-stage cell. (b) Two-stage dual output cell. (c) Two-stage ductance of the proposed two-stage dual-output cell, , dual output cell with compensation. (d) Two-stage fully differential cell with compensation. thus becomes (1) far-end terminations are used as balun outputs [32]. Finally, [33] stacks two DAs (with inverting CS gain stages) on top of each where the first and second terms on the right side represent the other in a 2-D matrix-like topology and uses their drain termi- equivalent transconductance of and nations as balun’s outputs. paths, respectively. The addition of the second term indicates This study presents a CMOS DA with distributed active input gain improvement over conventional two-stage cell of balun that achieves high gain and linearity without sacrificing Fig. 1(a). The percentage of relative gain improvement com- BW and dc power dissipation. In addition to the discussions pared to the conventional two-stage cell is depicted in covered in [34], this paper presents thorough analysis and Fig. 2 (on the left -axis) along with the gain expression in (1) simulation, investigating performance metrics of the proposed (on the right -axis) in terms of the gain of a single stage. For cell used in the DA including gain, BW, and linearity. It these plots, it is assumed that and ,for also contains additional measurement results for the fabricated simplicity. Fig. 2 shows gain improvement of 20%–100% com- DA and balun, as well as more comprehensive performance pared to conventional two-stage cell for gain values achievable comparison tables. Specifically, in Section II, the evolution of byasinglestageinananoscaleCMOSprocess.Thisgain the cell leading to the proposed architecture is presented. improvement comes at no extra power consumption and BW Section II also includes analysis and simulation results veri- degradation, as will be shown below. fying the functionality of the proposed topology. Section III B. BW discusses the design of the DA, as well as the distributed active balun. Section IV presents measurement results and comparison In Fig. 1(b), the path is similar to a cascode stage tables, and Section V provides concluding remarks. with an BW-enhancement circuit added to remove the cascode pole. The path, however, is different from II. CELL TOPOLOGY the two-stage cell of Fig. 1(a) in that resistor is replaced by transistor . To see the effect of on BW, we use the sim- A. Proposed Architecture plified equivalent small-signal model of Fig. 3, where transistor Fig. 1 demonstrates step-by-step evolution of the proposed ’s input impedance seen through its source terminal is mod- multistage cell used in the DA. The conventional two-stage eled with a parallel circuit . cell in Fig. 1(a), similar to the one proposed in [1], increases Here, is modeled by its transconductance , drain ca- the overall transconductance from (for a single stage pacitance , and drain–source resistance . is modeled cell) to ;where guarantees gain improve- by its transconductance and gate capacitance ,and ment compared to a single-stage cell. The BW-limiting in- with its circuit (where resistance ). The terstage pole of the cell is compensated using an inductive- gate capacitance and drain capacitance are absorbed peaking-based BW-enhancement network, comprising into the t-lines and can be removed from the model. SPICE sim- in Fig.

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