A CMOS Distributed Amplifier with Distributed Active Input Balun Using

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012 1331 A CMOS Distributed Ampliﬁer With Distributed Active Input Balun Using GBW and Linearity Enhancing Techniques Amin Jahanian, Member, IEEE, and Payam Heydari, Senior Member, IEEE

Abstract—ACMOSdistributedamplifier (DA) with distributed transmission lines (t-lines) to improve efficiency for power am- active input balun is presented that achieves a gain-bandwidth plifiers. In [6], t-line tapering and -derived terminations are product of 818 GHz, while improving linearity. Each cell used in a multistage DA to improve BW. A distributed low- within the DA employs dual-output two-stage topology that improves gain and linearity without adversely affecting bandwidth noise amplifier (DLNA) is designed for minimum noise figure (BW) and power. Comprehensive analysis and simulations are (NF) for ultra-wideband (UWB) applications in [7]. Reference carried out to investigate gain, BW, linearity, noise, and stability [13] uses differential stages, incorporating cross-connected of the proposed cell, and compare them with conventional capacitive neutralization, distributed along nonuniform down- cells. Fabricated in a 65-nm low-power CMOS process, the sized artificial lines to improve BW. A DA with gain stages 0.9-mm DA achieves 22 dB of gain and a of 10 dBm, while consuming dc power of 97 mW from a 1.3-V supply. A distributed comprising input emitter followers and output cascode stages is balun, designed and fabricated in the same process, using the implementedinanSiGebipolartechnology in [14]. same topology achieves a BW larger than 70 GHz and a gain Besides distributed amplification, many broadband amplifiers of 4 dB with 19.5-mW power consumption from 1.3-V supply. using other methods have been proposed, as well [16]–[20]. In Index Terms—Active balun, bandwidth (BW) compensation, [16], a low-frequency amplifier and a high-frequency tuned am- BW enhancement, CMOS, coplanar waveguide (CPW) transmis- plifier are cascaded to design a broadband amplifier. Impedance- sion line (t-line), distributed amplifier (DA), gain BW, linearity. tuned cascaded emitter–follower drivers have been utilized in an SiGe bipolar technology in [17] and [18] to increase BW I. INTRODUCTION of cascode-based lumped amplifiers, while increasing dc power consumption. A synthesis-based BW enhancement technique is presented in [19] that brings bandwidth enhancement ratio ISTRIBUTED amplifiers (DAs) have been used exten- (BWER) of CMOS amplifiers close to its theoretical limit. In sively for broadband wired/wireless applications. Various D [20], asymmetric transformer peaking was applied to cascaded techniques, examined in different technologies, have been pro- common-source (CS) CMOS stages to enhance BW. posed by prior work to improve DA performance parameters Distributed circuits are also implemented in the context of such as gain, bandwidth (BW), and power [1]–[15]. In [1], mul- active single-to-differential conversion (i.e., active baluns). Im- tistage cells are used to improve gain, while interstage induc- plemented using either active or passive components, baluns are tive peaking is employed to compensate for the BW degradation useful for various applications, such as broadband wired con- due to interstage poles of the cell. Reference [2] uses cas- nectivity and high-frequency general-purpose test and measure- caded DAs to improve gain, while sacrificing high-frequency ment equipment. Active baluns offer the advantage of achieving matching by removing the backward-propagation resistive ter- voltage and power gain of higher than (or around) unity, as mination of the drain line. Reference [3] uses feedback to double well as a higher reverse isolation over their passive counter- gain, while increasing the lower corner frequency to 12 GHz. In parts. Several active baluns have been proposed in the liter- [4], a series capacitor at the input of the cell is introduced, ature. One solution is to use a differential pair stage with a which trades gain for BW. Reference [5] employs nonuniform single-ended signal applied to one input transistor’s gate (or base) terminal, while ac grounding the other one [21]–[24]. An- Manuscript received September 28, 2011; revised November 22, 2011; ac- other candidate utilizes the 180 phase shift between the outputs cepted November 29, 2011. Date of publication February 06, 2012; date of current version April 27, 2012. This work was supported in part by the National of a common-gate–common-source (CG–CS) pair [25]–[28] to Science Foundation (NSF) CAREER Grant under Contract ECS-0449433 and realize differential output. An issue with the CG–CS topology by Mindspeed Technologies. This paper is an expanded paper from the IEEE is incompatible input impedances of the two stages (i.e., capaci- RFIC Symposium, June 5–10, 2011, Baltimore, MD. A. Jahanian was with the Nanoscale Communication Integrated Circuit tive input for CS and resistive input for CG). This issue is (NCIC) Laboratory, Electrical Engineering and Computer Science Department, addressed in [29] by adding a CS-connected transistor with its University of California at Irvine, Irvine, CA 92697-2625 USA. He is now with gate terminal connected to the input and its drain terminal con- Qualcomm Atheros Inc., Irvine, CA 92618 USA (e-mail: [email protected]). P. Heydari is with the Electrical Engineering and Computer Science Depart- nected to the input node of the CS-CG pair. The original CG–CS ment, University of California at Irvine, Irvine, CA 92697-2625 USA (e-mail: topology has been incorporated into the distributed architecture [email protected]). [30]. In [31], CS gain stages are used and differential outputs Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. are taken from far-end gate and drain t-line terminations. Two Digital Object Identifier 10.1109/TMTT.2012.2184134 DAs (each with inverting CS gain stages) are cascaded and their

Fig. 2. of the proposed stage and its relative improvement versus of a single stage.

, as in Fig. 1(b), to introduce an additional signal path. Tran- sistor acts as a cascode device for the new signal path, while behaving similar to a resistive load (with for the first stage of the two-stage path. Assuming that the output signals and are summed constructively (as will be shown below), the overall transcon- Fig. 1. (a) Two-stage cell. (b) Two-stage dual output cell. (c) Two-stage ductance of the proposed two-stage dual-output cell, , dual output cell with compensation. (d) Two-stage fully differential cell with compensation. thus becomes (1) far-end terminations are used as balun outputs [32]. Finally, [33] stacks two DAs (with inverting CS gain stages) on top of each where the first and second terms on the right side represent the other in a 2-D matrix-like topology and uses their drain termi- equivalent transconductance of and nations as balun’s outputs. paths, respectively. The addition of the second term indicates This study presents a CMOS DA with distributed active input gain improvement over conventional two-stage cell of balun that achieves high gain and linearity without sacrificing Fig. 1(a). The percentage of relative gain improvement com- BW and dc power dissipation. In addition to the discussions pared to the conventional two-stage cell is depicted in covered in [34], this paper presents thorough analysis and Fig. 2 (on the left -axis) along with the gain expression in (1) simulation, investigating performance metrics of the proposed (on the right -axis) in terms of the gain of a single stage. For cell used in the DA including gain, BW, and linearity. It these plots, it is assumed that and ,for also contains additional measurement results for the fabricated simplicity. Fig. 2 shows gain improvement of 20%–100% com- DA and balun, as well as more comprehensive performance pared to conventional two-stage cell for gain values achievable comparison tables. Specifically, in Section II, the evolution of byasinglestageinananoscaleCMOSprocess.Thisgain the cell leading to the proposed architecture is presented. improvement comes at no extra power consumption and BW Section II also includes analysis and simulation results veri- degradation, as will be shown below. fying the functionality of the proposed topology. Section III B. BW discusses the design of the DA, as well as the distributed active balun. Section IV presents measurement results and comparison In Fig. 1(b), the path is similar to a cascode stage tables, and Section V provides concluding remarks. with an BW-enhancement circuit added to remove the cascode pole. The path, however, is different from II. CELL TOPOLOGY the two-stage cell of Fig. 1(a) in that resistor is replaced by transistor . To see the effect of on BW, we use the sim- A. Proposed Architecture plified equivalent small-signal model of Fig. 3, where transistor Fig. 1 demonstrates step-by-step evolution of the proposed ’s input impedance seen through its source terminal is mod- multistage cell used in the DA. The conventional two-stage eled with a parallel circuit . cell in Fig. 1(a), similar to the one proposed in [1], increases Here, is modeled by its transconductance , drain ca- the overall transconductance from (for a single stage pacitance , and drain–source resistance . is modeled cell) to ;where guarantees gain improve- by its transconductance and gate capacitance ,and ment compared to a single-stage cell. The BW-limiting in- with its circuit (where resistance ). The terstage pole of the cell is compensated using an inductive- gate capacitance and drain capacitance are absorbed peaking-based BW-enhancement network, comprising into the t-lines and can be removed from the model. SPICE sim- in Fig. 1(a). However, the amplified signal power on the resis- ulations are run to investigate the effect of variationonfre- tive drain load, ,ofthefirst stage is totally wasted and is not quency response, as depicted in Fig. 4. For these simulations, utilized to improve performance. This issue is mitigated in the mA/V, fF, k , proposed dual-output cell by replacing with a transistor , and the output current is terminated through a 50- JAHANIAN AND HEYDARI: CMOS DA WITH DISTRIBUTED ACTIVE INPUT BALUN USING GBW AND LINEARITY ENHANCING TECHNIQUES 1333

Fig. 3. Equivalent model of the dual-output cell of Fig. 1(b).

Fig. 4. Effect of source capacitance on frequency response.

Fig. 6. Effect of: (a) compensation and (b) variation on frequency response.

The effect of adding the parallel compensation circuit to the circuit of Fig. 3 is simulated (Fig. 6). It is evident from Fig. 6(a) that the circuit compensates for the degrading Fig. 5. DA cell compensation. effect of parasitic capacitance, and restores the frequency response of the two-stage cell when there is no parasitic effect of . resistive load. The BW-enhancement network ( pH An important consideration is the sensitivity of the transfer and pH) is designed for the case where no exists. function with respect to and values of this BW compen- Fig. 4 shows that as takes on larger values, the voltage-gain’s sation network. The sensitivity of in Fig. 5(b) with respect frequency response experiences increasingly more ripple and to variation in values in (4) is obtained by accounting BW degradation. To mitigate the effects, a BW compen- for relative resistive and inductive offset errors and , respec- sation network with impedance is added in series with the tively. Assuming and in circuit of , as seen in Fig. 5(a). The input impedance, (3), the relative impedance error, ,deﬁned as , then becomes (2) (5)

is found, after removing second-order errors (i.e., ) If is synthesized such that the effective input impedance seen into the source of is purely resistive, i.e., ,the effect will have been fully compensated. Using this notion in rearranging (2), we will have (6) At very low frequencies where , (6) is simpli- (3) ﬁed to

can be realized using a parallel network, as indicated (7) in Fig. 5(b), with and at higher frequencies where , (6) becomes

(4) (8) 1334 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012

Equations (7) and (8) show that variation in the absolute value of is roughly proportional, to the first degree, to resistive and inductive offset errors. The effect of varying the inductor on the overall transfer function is depicted in Fig. 6(b), where the inductance is varied by 10% of its nominal value. The frequency response, shown via the solid line for the nominal value, and dashed and dotted lines for minimum and maximum values, respectively, shows negligible sensitivity of the frequency response to variation. Similarly, low sensitivity is observed Fig. 7. Low-frequency models for linearity analysis of: (a) CS stage and with respect to the resistance variation in the parallel cir- (b) proposed stage. cuit. The resulting dual-output cell with compensation, shown in Fig. 1(c), has the same BW as the two-stage by expressing in terms of and for ; cell of Fig. 1(a). Additionally, the gain improvement [see (1)] and considering that ,wehave provided by this cell results in an increase in gain-bandwidth (GBW) compared to conventional two-stage cells. (9) C. Fully Differential Topology The right-hand side of (9) is a function of and nMOS In the dual-output cell with parallel compensation transistor’s parameters, and is a constant with respect to device depicted in Fig. 1(c), the drain of sees two paths provided operating points. On the other hand, using (1) and considering by CS and CG stages and (similar to [29]), resulting in once again that , the overall transconductance of an ideally 180 phase shift between and nodes. the proposed dual-output cell is rewritten as If two identical cells are connected to differential input lines and their output nodes are cross-coupled as in Fig. 1(d), each (10) output of the resulting fully differential cell exhibits the same [specified by (1)]. The resulting fully differential cell Comparing (9) and (10) reveals that the left-hand side of (9) of Fig. 1(d) enjoys symmetric design and implementation, and and the right-hand side of (10) will be identical if . minimal phase and amplitude distortion at its two output termi- Hence, the overall will stay constant even in the presence nals. of variations in and . More precisely, as the drain currents fluctuate away from their bias values due to large-signal D. Power and Area input voltage, the ’s will change in such a way that stays intact. This large signal constant- characteristic results in im- In the dual-output cell of Fig. 1(c), can easily be sized provement in linearity. such that is equal (or close to) the drain resistance This phenomenon can be analyzed using the square-law I–V in Fig. 1(a). Moreover, the parallel circuit does not af- relation of MOS transistors (a similar approach has been pre- fect the dc bias at all, and the gate of can be biased at a sented in [35]). The following notations are introduced so as to dc voltage high enough to ensure that two stacked gate–source make it easier to follow the forthcoming analysis. voltages and both stay above , given that the DC biasing signals are represented with uppercase letters supply voltage is 1.3 V. Consequently, the proposed cell can and uppercase indices (e.g., ), and small-signal ac sig- be designed, sized, and biased similar to the conventional two- nals are represented with lowercase letters and lowercase stage cell. This means that no additional power is needed to indices (e.g., ). The sum of these two components is achieve the gain improvement described by (1). represented using lowercase letters with uppercase indices As for chip area, replacing drain resistance with transistor (e.g., ). The nMOS I–V characteristic is expressed as has a negligible effect on area. This is because the overall , where constant common param- area is dominated by passive elements (especially the gate/drain eters are grouped together in the form of .To t-lines) rather than transistor sizes. The circuit added to facilitate the linearity analysis, the low-frequency circuit model the proposed cell does not occupy a large area either, as for a conventional CS stage and the proposed dual-output and values are in the order of 50 and 35–72 pH, respec- cell are utilized (Fig. 7). For the CS stage of Fig. 7(a), the tively. The dual-output cell of Fig. 1(c), therefore, occu- small-signal drain current, , is expressed as a function of pies approximately the same size and consumes almost the same gate–source voltage [36] power as the conventional cell of Fig. 1(a). (11) E. Linearity Assuming , (11) is rewritten as Transistor in the cellofFig.1(c)isbiasedfromthedc voltage applied through the gate t-line, and is biased at , where . Using this voltage relationship, and (12) JAHANIAN AND HEYDARI: CMOS DA WITH DISTRIBUTED ACTIVE INPUT BALUN USING GBW AND LINEARITY ENHANCING TECHNIQUES 1335

Consequently, the ratio between second and fundamental harmonic amplitudes in a CS stage, ,is

(13)

For the proposed cell of Fig. 7(b), the drain currents are found using (11)

Fig. 8. Compression curves for the proposed and cascode cells. (14)

Using the relations and , we rearrange (14) in order to ﬁnd the overall output current as a function of input voltage

(15)

yields

(16)

From (16), the ratio of the second to the fundamental har- monics for the proposed cell is

(17)

Referringto(17),maximumlinearityisachievedwhenthe second harmonic (numerator) vanishes. This occurs when , which veriﬁes the conclusion made earlier through intuitive analysis. Fig. 9. Signal loop in the differential cell. (a) Circuit-level representation While equal aspect ratios for and results in maximum and (b) -parameter simulation. linearity, higher gain improvement is achieved for larger [see (1)], i.e., , at the expense of reduced linearity improvement. Therefore, design solutions for maximum gain (18) improvement and maximum linearity improvement differ from each other, indicating that a tradeoff exists between gain and The linearity improvement ratio between the dual-output linearity improvements for this topology. To delve deeper into cell and the CS stage, deﬁned as ,willbe this notion, we compare linearity of the proposed dual-output cell (for ) and conventional CS stage. For sim- (19) plicity, in (17), we assume all devices have the same overdrive voltage, . Moreover, we choose (with to For values of close to 1 (which improves the frequency achieve voltage gain) and . ,and , therefore, behavior of cells in high-frequency DAs), the condition become ensures that is larger than unity. Consequently, the topology does improve linearity even when it is optimized for gain improvement. For instance, for 1336 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012

Fig. 10. Four-stage DDA with three-stage distributed input balun.

Fig. 11. Two-stage distributed balun.

( and ), a linearity improvement of 5 can be achieved. For more gain improvement, (e.g., and ), linearity improvement drops to 3, verifying tradeoff between gain and linearity improvements. To simulate linearity of the proposed topology, a conventional cascode cell and the dual-output cell were designed for the same resistive load, voltage gain, and power consumption. Simulations were conducted to extract output-referred 1-dB compression points for the two structures. Both cells use the same resistive load of 50 with overall dc current Fig. 12. Die microphotograph of the: (a) DA and (b) standalone two-stage of 8.7 mA for cascode and 8.2 mA for the proposed cell balun. from a 1.2-V power supply. The cascode cell achieved adcgainof8.4dBandan of 2.0 dBm, whereas the proposed cell achieved a dc gain of 8.8 dB and an instance, making too large to further increase gain will make of 5.5 dBm. Consequently, for this case study, the proposed inductive peaking less effective due to excessive parasitic ca- cell achieved a 3.5-dB improvement in compared pacitance. In the meantime, making too small will lead to with a conventional cascode cell under similar conditions, excessively large , which makes hard as seen in Fig. 8. to realize at nominal supply voltages around 1–1.3 V. For this During design and optimization, in addition to gain and lin- design, approximate values of arechosentoad- earity requirements, other criteria need to be met, as well. For dress these concerns. JAHANIAN AND HEYDARI: CMOS DA WITH DISTRIBUTED ACTIVE INPUT BALUN USING GBW AND LINEARITY ENHANCING TECHNIQUES 1337

Fig. 13. Measured and simulated: (a) -parameters, (b) , (c) NF, (d) GD, (e) phase response, and (f) phase imbalance of the DA.

F. Noise Noise analysis for each of the two input-output paths of the two-stage cell in Fig. 1(c) results in two different input-re- (21) ferred noise voltages. For the path, the cascode device does not contribute to the overall noise because of From (20) and (21), it is evident that increasing the ratio the large resistive degeneration provided by in the equiv- improves overall noise performance. This is in alent noise circuit model. Neither does the second stage tran- line with the gain performance of the cell. Therefore, in the sistor since it is not directly in the signal path. Consequently, gain-linearity tradeoff investigated in Section II-E, improving the overall input-referred noise voltage reflects only the gain results in noise improvement as well. thermal noise component contributed by the input transistor, G. Stability (20) In the fully differential cell of Fig. 1(d), a signal loop However, for the path, the thermal noise com- is formed due to the cross-coupled connection of two cells in ponents of all three transistors contribute to overall output noise Fig. 1(c). Here, we show this loop entails significant signal at- power. Using superposition, the overall input-referred noise tenuation, and therefore does not create instability issue for the voltage is found to be amplifier. We first expand the cell as seen in Fig. 9(a), where 1338 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012

Fig. 14. Measured and simulated: (a) ,(b) -parameters, (c) phase response, (d) phase imbalance, (e) gain imbalance, and (f) of the distributed balun. is the characteristic impedance of the drain t-line. The low-fre- DA. The plots show an increasingly large reverse attenuation at quency loop gain, , is found from point to point and dc and minimum reverse attenuation larger than 30 dB. It also back to in Fig. 9(a) in the forward direction (the reverse di- shows a dc forward attenuation of 25 dB and minimum forward rection clearly includes considerable attenuation close to ideal attenuation of 18 dB across the BW of around 80 GHz. isolation at low frequencies) III. PROPOSED DA (22) The ideally differential outputs of the proposed dual-output cell in Fig. 1(c) makes it suitable for a: 1) distributed balun It is evident from (22) that for practical CMOS amplifiers, and 2) distributed fully differential distributed amplifier (DDA) significant attenuation exists along the loop. For instance, for incorporating symmetric cross-coupled cells of Fig. 1(d). , is approximately ten times larger than ,and Shown in Fig. 10 is the complete DA (along with device sizes) with , 40-dB attenuation in the loop gain will be that is composed of a three-stage distributed balun followed obtained. This amount of attenuation is far too much to lead by a four-stage DDA. In Fig. 10, Vand to any unstable or close-to-unstable behavior in the amplifier V. The circuit uses differential coplanar waveguides in any condition. Eventually, the proposed cell follows the (CPWs) as t-lines with signal lines on top Al metal, ground walls same stability rules as other CS-based DAs. on all metals, and slotted ground shield on lowest metal. The dis- Fig. 9(b) depicts the simulatedloopgainintheforward tributed input balun of the DA shown in Fig. 10 is also designed and reverse directions for the cell designed for the as a standalone two-stage distributed balun, shown in Fig. 11. To JAHANIAN AND HEYDARI: CMOS DA WITH DISTRIBUTED ACTIVE INPUT BALUN USING GBW AND LINEARITY ENHANCING TECHNIQUES 1339

TABLE I DA MEASUREMENT RESULTS AND COMPARISON WITH PRIOR WORK

BW is calculated as the difference of higher and lower 3-dB frequencies. achieve impedance matching, the DDA and the balun should The NF of the DA, measured using a 40-GHz noise source, have equal characteristic impedance . is depicted in Fig. 13(c), where a measured in-band NF of 7 Since the DDA is the main provider of gain, and thus contains dB is achieved up to 40 GHz. Fig. 13(d) shows measured and larger transistors with larger parasitic input/output capacitances, simulated group delay (GD) versus frequency. The relatively its CPWs are longer to allow for higher inductance. These CPWs ﬂat GD of around 40 ps proves high phase linearity across the are carefully bent using 45 line breaks so that the DDA chip is band. In Fig. 13(d), the GD at low frequencies is adversely af- not overextended in one dimension. DA and balun CPWs have fected by the input/output dc coupling capacitors of the bias of 93 and 118 GHz and unloaded of 87 and 84 ,re- tees. Fig. 13(e) shows measured and simulated phase responses spectively. The balun output and the DDA input are dc coupled of the transfer functions for two main outputs of the DA. Both to avoid the degrading effects of an ac coupling capacitor. The measured and simulated responses show almost linear phase re- spiral inductors and interconnects inside the cells are im- sponse. The phase imbalance of the two phase responses, shown plemented in a top Cu-thick metal layer to minimize loss. The in Fig. 13(f), demonstrates less than 12 of phase imbalance inductors are all octagonal spirals smaller than 70 mindiam- over the entire frequency range. eter, with an inductance of 40 220 pH and a maximum Measurement results of the standalone balun are shown along close to 20. The approximate spiral inductor values are shown with simulation results in Fig. 14, where a measured voltage in the table in Fig. 10. The inductances lower than 35 pH (ap- gain of 4 dB and a measured of less than 10 dB are re- proximate value) are realized using t-lines. All CPWs, induc- ported. The measured BW of the balun exceeds (and is thus lim- tors, t-lines, and interconnects have been electromagnetic (EM) ited by) the BW of test equipment, which is 70 GHz. Fig. 14(a), simulated using a Sonnet planar EM simulator to accurately cap- however, shows a simulated BW of around 80 GHz. ture high-frequency effects. Moreover, all inductors and inter- Phase and gain imbalance between the two outputs is an im- connects within any cell have been EM simulated together as portant performance metric of baluns. This becomes more cru- a complex multiport structure to capture and minimize any par- cial for baluns that are structurally asymmetric such as the one asitic mutual coupling that could degrade performance at high proposed in this paper. The measured phase response of the frequencies. balun is shown in Fig. 14(c) along with the simulation result. The fabricated balun exhibits phase imbalance of less than 10 IV. MEASUREMENT RESULTS across the BW, as seen in Fig. 14(d). In Fig. 14(e), gain im- The DA and standalone balun are fabricated in a 65-nm low- balance of the balun is shown, which demonstrates a measured power (LP) CMOS process with GHz imbalance of less than 1 dB across the BW. The 1-dB compres- and V (Fig. 12). Two 65-GHz bias tees are con- sion point of the balun for 2- and 10-GHz input tones is depicted nected at the output and one at the input to isolate the dc biases in Fig. 14(f), which shows an output-referred of 2 dBm. of these nodes from equipment ports. Both measured and simu- Simulation results for plots of Figs. 13 and 14 are shown to help lated -parameters of the DA are shown in Fig. 13(a). The DA comparison with measurement results. has a measured in-band voltage gain of 22 dB and an less Tables I and II present and compare performance summary than 10 dB. The voltage gain stays within 3 dB of its low-fre- of the DA and the distributed balun with prior work, respec- quency value for frequencies up to 65 GHz. It is found from tively. Table I shows 818-GHz GBW along with high linearity -parameter curves in Fig. 13(a) that the DA is stable across the for the proposed DA compared to prior art. Table II shows su- BW. Fig. 13(b) shows measured and simulated transfer curves perior gain and BW performance with lowest power consump- of the DA for 2-, 10-, and 20-GHz input tones, where an av- tion for the presented distributed balun. It also shows that de- erage measured differential output of 10 dBm is reported. spite its asymmetric structure, the balun achieves low phase and 1340 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012

TABLE II DISTRIBUTED BALUN MEASUREMENT RESULTS AND COMPARISON WITH PRIOR WORK

gain imbalance compared to prior art. The input balun and the [10] J.-O. Plouchart et al., “A 4–91-GHz traveling-wave amplifier in stan- DDA consume 18- and 57-mA current from a 1.3-V supply, re- dard 0.12- m SOI CMOS microprocessor technology,” IEEE J. Solid- State Circuits, vol. 39, no. 9, pp. 1455–1461, Sep. 2004. spectively. The overall circuit consumes 97 mW, and occupies [11] C. Pavageau et al., “A 7-dB 43-GHz CMOS distributed amplifier on 0.94 mm without and 1.58 mm with pad rings. The standalone high-resistivity SOI substrates,” IEEE Trans. Microw. Theory Tech., balun consumes a 15 mA current from 1.3-V supply, and occu- vol. 56, no. 3, pp. 587–598, Mar. 2008. [12] F. Ellinger, “60-GHz SOI CMOS travelling-wave amplifier with NF pies a chip area of 0.16 mm withoutand0.64mm with pads. below 3.8 dB from 0.1 to 40 GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 553–558, Feb. 2005. [13] A. Yazdi, D. Lin, and P. Heydari, “A 1.8 V three-stage 25 GHz 3 V. C ONCLUSION dB-BW differential non-uniform downsized distributed amplifier,” in A DA and a distributed balun are designed in a 65-nm CMOS Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2005, pp. 156–590. [14] O. Wohlgemuth, P. Paschke, and Y. Baeyens, “SiGe broadband am- process that achieve gain and linearity improvement without de- plifiers with up to 80 GHz bandwidth for optical applications at 43 grading BW, power consumption, and area. This is due to the Gbit/s and beyond,” in 33rd Eur. Microw. Conf., Oct. 2003, vol. 3, pp. use of a two-stage dual-output cell with parallel R–L cir- 1087–1090. [15] L.-H. Lu, T.-Y. Chen, and Y.-J. Lin, “A 32-GHz non-uniform cuit for BW compensation. Gain and linearity improvement is distributed amplifier in 0.18-mm CMOS,” IEEE Microw. Wireless verified through comprehensive analysis, modeling, and simu- Compon. Lett., vol. 15, no. 11, pp. 754–747, Nov. 2005. lations. Extensive EM simulation, as well as corner and post- [16] J. Kim and J. F. Buckwalter, “Staggered gain for 100 GHz broadband amplifiers,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1123–1136, layout simulation, have resulted in a good match between sim- May 2011. ulation and measurement results. [17] S. Trotta et al., “An 84 GHz bandwidth and 20 dB gain broadband amplifier in SiGe Bipolar technology,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2099–2106, Oct. 2007. ACKNOWLEDGMENT [18] W. Perndl et al., “A 60 GHz broadband amplifier in SiGe bipolar technology,” in Proc. Bipolar/BiCMOS Circuits Technol. Meeting,Sep. The authors would like to thank MOSIS, Marina Del Rey, 2004, pp. 293–296. CA, Mindspeed Technologies Inc., Newport Beach, CA, and [19] D. Pi, B.-K. Chun, and P. Heydari, “A synthesis-based bandwidth en- C. Wang, University of California at Irvine, F. Tzeng, Zerowatt hancement technique for cmos amplifiers: Theory and design,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 392–402, Feb. 2011. Tech., Irvine, CA, and V. Jain, SaberTek Inc., Irvine, CA. [20] J.-D. Jin and S. Hsu, “A miniaturized 70-GHz broadband amplifier in 0.13- m CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 12, pp. 3086–3092, Dec. 2008. REFERENCES [21] C. Viallon et al., “Design of an original -band active balun with [1] J. C. Chien and L. H. Lu, “40-Gb/s high-gain distributed amplifiers with improved broadband balanced behavior,” IEEE Microw. Wireless cascaded gain stages in 0.18- mCMOS,”IEEE J. Solid-State Circuits, Compon. Lett., vol. 15, no. 4, pp. 280–282, Apr. 2005. vol. 42, no. 12, pp. 2715–2725, Dec. 2007. [22] B. J. Huang et al.,“A2–40GHzactivebalunusing0.13 mCMOS [2] M.D.Tsaiet al., “A 70 GHz cascaded multi-stage distributed amplifier process,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 3, pp. in 90 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig.,Feb. 164–166, Mar. 2009. 2005, pp. 402–403. [23] S.-H. Weng, H.-Y. Chang, and C.-C. Chiong, “A DC–21 GHz low im- [3] A. Arbabian and A. M. Niknejad, “A broadband distributed amplifier balance active balun using darlington cell technique for high speed data with internal feedback providing 660 GHz GBW in 90 nm CMOS,” in communications,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2008, pp. 196–197. 11, pp. 728–730, Nov. 2009. [4]R.C.Liuet al., “An 80 GHz travelling-wave amplifier in a 90 nm [24] B. Welch, K. T. Kornegay, H.-M. Park, and J. Laskar, “A 20-GHz low- CMOS technology,” in Int. Solid-State Circuits Conf. Tech. Dig.,Feb. noise amplifier with active balun in a 0.25- mSiGeBICMOStech- 2005, pp. 154–155. nology,” IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2092–2097, [5] J. Chen and A. M. Niknejad, “Design and analysis of a stage-scaled Oct. 2005. distributed power amplifier,” IEEE Trans. Microw. Theory Tech., vol. [25] T. Hiraoka et al., “A miniaturized broadband MMIC frequency 59, no. 5, pp. 1274–1283, May 2011. doubler,” IEEE Trans. Microw. Theory Tech., vol. 38, no. 12, pp. [6] A. Arbabian and A. M. Niknejad, “Design of a CMOS tapered cascaded 1932–1937, Dec. 1990. multistage distributed amplifier,” IEEE Trans. Microw. Theory Tech., [26] M. C. Tsai et al., “A compact wideband balanced mixer,” in IEEE vol. 57, no. 4, pp. 938–947, Apr. 2009. MTT-SInt.Microw.Symp.Dig., 1994, pp. 5–8. [7]P.Heydari,“Designandanalysis of a performance-optimized CMOS [27] M. Kawashima et al., “A novel broadband active balun,” in 33rd Eur. UWB distributed LNA,” IEEE J. Solid-State Circuits,vol.42,no.9, Microw. Conf., Oct. 2003, vol. 2, pp. 495–498. pp. 1892–1905, Sep. 2007. [28] P.-Z. Rao, T.-Y. Chang, C.-P. Liang, and S.-J. Chung, “An ultra-wide- [8] J. Kim and J. F. Buckwalter, “A 92 GHz bandwidth distributed am- band high-linearity CMOS mixer with new wideband active baluns,” plifier in a 45 nm SOI CMOS technology,” IEEE Microw. Wireless IEEE Trans. Microw. Theory Tech., vol. 57, no. 9, pp. 2184–2192, Sep. Compon. Lett., vol. 21, no. 6, pp. 329–331, Jun. 2011. 2009. [9] J. Kim et al., “A 12 dBm 320 GHz GBW distributed amplifier in a [29] K. Jung et al., “Broadband active balun using combined cascode—Cas- 0.12 m SOI CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., cade configuration,” IEEE Trans. Microw. Theory Tech.,vol.56,no.8, Feb. 2004, pp. 478–540. pp. 1790–1796, Aug. 2008. JAHANIAN AND HEYDARI: CMOS DA WITH DISTRIBUTED ACTIVE INPUT BALUN USING GBW AND LINEARITY ENHANCING TECHNIQUES 1341

[30] A. M. Pavio, R. H. Halladay, S. D. Bingham, and C. A. A. Sapashe, Payam Heydari (S’98–M’00–SM’07) received the “Double balanced mixers using active and passive techniques,” IEEE B.S. and M.S. degrees (with honors) in electrical en- Trans. Microw. Theory Tech., vol. 36, no. 12, pp. 1948–1957, Dec. gineering from the Sharif University of Technology, 1988. Tehran, Iran, in 1992 and 1995, respectively, and the [31] A. H. Baree and I. D. Robertson, “Analysis and design of multi-octave Ph.D. degree in electrical engineering from the Uni- MMIC active baluns using a distributed amplifier gate line termination versity of Southern California, Los Angeles, in 2001. technique,” in IEEE MTT-S Int. Microw. Symp. Dig., May 16–20, 1995, In August 2001, he joined the University of vol. 2, pp. 865–868. California at Irvine (UCI), where he is currently [32] I. D. Robertson and A. H. Aghvami, “A novel wideband MMIC active a Professor of electrical engineering. He is the balun,” in Proc.20thEur.Microw.Conf., 1990, vol. 1, pp. 419–423. co-founder of ZeroWatt Technologies Inc. He coau- [33] M. Ferndahl and H. O. Vickes, “The matrix balun—A transistor-based thored one book and over 90 journal and conference module for broadband applications,” IEEE Trans. Microw. Theory papers. His research interests include the design of high-speed analog, RF, and Tech., vol. 57, no. 1, pp. 53–60, Jan. 2009. mixed-signal integrated circuits. [34] A. Jahanian and P. Heydari, “A CMOS distributed amplifier with active Dr. Heydari has been a guest editor for the IEEE JOURNAL OF SOLID-STATE input balun using GBW and linearity enhancing techniques,” in IEEE CIRCUITS. He currently serves on the Technical Program Committees of the RFIC Symp., Jun. 2011, pp. 1–4. Compound Semiconductor Integrated Circuit Symposium (CSICS). He was an [35] K. Bult and H. Wallinga, “A class of analog CMOS circuits based on associate editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART the square-law characteristic of an MOS transistor in saturation,” IEEE I: REGULAR PAPERS (2006–2008). He was a Technical Program Committee J. Solid-State Circuits, vol. SSC-22, no. 3, pp. 357–365, Jun. 1987. member of the IEEE Custom Integrated Circuits Conference (CICC), the In- [36] B. Razavi, Design of Analog CMOS Integrated Circuits.NewYork: ternational Symposium on Low-Power Electronics and Design (ISLPED), the McGraw-Hill, 2001, ch. 13. IEEE Design and Test in Europe (DATE), and the International Symposium on Quality Electronic Design (ISQED). The Office of Technology Alliances, UCI, Amin Jahanian (S’05–M’11) received the B.S. has named him one of ten outstanding innovators at the university. He was the and M.S. degrees in electrical engineering from the corecipient of the 2009 Business Plan Competition First Place Prize Award and Sharif University of Technology, Tehran, Iran, in Best Concept Paper Award, both from the Paul Merage School of Business at 2003 and 2005, respectively, and the Ph.D. degree UCI, the 2010 Faculty of the Year Award from the Engineering Student Council in electrical engineering from the University of (ECS), UCI, the 2009 School of Engineering Fariborz Maseeh Best Faculty Re- California at Irvine, in 2011. search Award, the 2007 IEEE Circuits and Systems Society Guillemin–Cauer In Summer 2007, he was with Fujitsu Laborato- Award, the 2005 National Science Foundation (NSF) CAREER Award, the 2005 ries of America, where he was involved with mod- IEEE Circuits and Systems Society Darlington Award, the 2005 UCI School of eling and design of millimeter-wave frequency syn- Engineering Teaching Excellence Award, the Best Paper Award of the 2000 thesizers. In Summer 2008 and 2010, he was with IEEE International Conference on Computer Design (ICCD), the 2000 Honor- Qualcomm Inc., where he designed an ultra-compact able Award of the Department of Electrical Engineering Systems, University of on-chip tone generator for calibration purposes and a real-power detector for Southern California, and the 2001 Technical Excellence Award in the area of Bluetooth and wireless local area network (WLAN) transmitter modules. In electrical engineering from the Association of Professors and Scholars of Ira- 2011, he joined Qualcomm Atheros Inc., Irvine, CA as a Senior Engineer. nian Heritage (APSIH). He was also recognized as the 2004 Outstanding Fac- Mr. Jahanian was the recipient of the Henry Samueli School of Engineering ulty of the Electrical Engineering and Computer Science Department, UCI. His Fellowship Award in 2006, the Center for Pervasive Communications and Com- research on novel LP multipurpose multiantenna RF front-ends received the puting (CPCC) Fellowship Award in 2007, and Mindspeed Fellowship Award Low-Power Design Contest Award presented at the 2008 IEEE International in 2010. He was a corecipient of the Eighth International Low-Power Design Symposium on Low-Power Electronics and Design (ISLPED). Contest Award presented at ISLPED 2008.