CMOS Technology Characterisation for analog/RF application

Ehrenfried Seebacher

austriamicrosystems AG, Schloss Premstaetten, A-8141 Unterpremstaetten, Austria [email protected] ,

Abstract RF modeling features like gate resistor or a substrate network must be added to the existing MOS model for the old model We discuss state of the art and new developments for the generations like BSIM3 or MOS Model 9 but is mostly characterization of CMOS technologies. In the first chapter included in the newer models like BSIM4. Passive devices the most important issues of MOS transistor modeling will be such as resistors, capacitors, varractors and inductors find shown. Topics like AC/DC modeling, noise modeling and wide usage in analog and RF CMOS integrated design. This temperature modeling for the MOS transistor will be devices must be modeled highly accurate for their frequency, explained. State of the art MOS transistor models like the voltage and temperature dependency. In most analog designs BSIM3 and BSIM4 models as well as the newest surface bandgap reference circuit are needed. Accurate modelling of potential and charge based models will be highlighted. the parasitic BJT transistor specially the voltage and the This article touch on a few of the issues that are important temperature dependency of the base emitter junction is for RF design. However the bottom line is the existence of required. And including all this devices the process variations high accurate S-Parameter measurements and frequency for robust design and increasing yield must be addressed in dependent SPICE models not only for the active devices like Worst Case corner modeling, Monte Carlo modeling or other MOS transistor and varactors, also for passive devices like statistic corner sets for parametric or non parametric corner resistors, inductors and capacitors. models. CMOS technologies include also additional parasitic devices like PNP bipolar transistors, which should be modeled II. CMOS TRANSISTOR ANALOG COMPACT very carefully for different analog applications like band-gap MODELLING reference circuits. And last but not least the very important topic statistical modeling including worst case corner For analog SPICE simulation of CMOS circuits it is modeling, Monte Carlo simulation, statistical boundary important to use a physically based model as opposed to modeling and mismatch parameter will be discussed. purely mathematical models as for example BSIM1 or BSIM2 [1.] or numerically abstract look-up tables. The industry standard BSIM3v3 [2.], the Philips LEVEL9 [5.] or the EKV I. INTRODUCTION [4.] compact models allow many parameters - such as oxide Circuit simulation for analog/RF design has become more thickness TOX or long channel threshold voltage VTH - to be and more important for the development of integrated circuits set at their actual process values and other parameters to be during the past years. The growing complexity of the tuned to achieve a good fit between measured and extracted applications and shorter product development cycles demand values. high efforts from the designers to create complex designs This process is iterative and must be checked not only for more quickly. Circuit simulation has become a very important the first order parameters such as the drain current Ids but for tool to check the functionality of a design before prototyping the small signal transconductance gm and the small signal in order to avoid time-intensive and expensive production output transconductance gds (see Figure 1) also. For analog iterations. The increasing use of MOSFETs for analog and RF simulation, with limited simulator convergence, it is important applications combined with the decreasing dimensions has to use these physical and scaleable models which apply to all create the need for advanced compact models for the geometries and all operating conditions [8.]. High precision MOSFET. Most of the existing MOS technologies using the SPICE modelling especially in the transition region of the so called “Threshold based” like BSIM3 BSIM4 or MOS MOS transistor for low VTH and sub-micron processes is MODEL 9. This generation of models rely on approximate needed. For anlog/ms designs with supply voltages of 1.2V solutions that are only valid in particular regions of operation the operating conditions of the MOS transistor is in the connected mathematically to provide continues solutions. transition region between sub-threshold and inversion region, New models, which overcomes to this problems are the dependent of the geometry. State-of-the art piece-wise “charge based models” e.g. EKV, ACM, BSIM5 and the regional-based compact models like in BSIM3v3 [3.] or surface potential models e.g. MOS Model 11 HiSIM and SP. BSIM4 are developed to describe the behaviour of the These models also try to solve all important challenges which transistor in the different operating regions and connect this occur in deep-sub micron CMOS process technologies. 1/f equations using so called effective voltages to avoid and high frequency noise characterization is an essential part discontinuities (see Eq.1). of MOS SPICE models, which can be optionally chosen in the simulator or inherently included in the specific model type. −3 x 10 NMOS + Meas. − BSIM3v3 W/L= 10/0.3; VB[V]= 0 VG[V]=0.9,1.5,2.1,2.7,3.3, results are shown in Fig. 2 where the transfer characteristic of

5 a MOS transistor with the geometry W/L=10/0.24 is shown. The parameter set has been extracted from 10 different 4 geometries with the use of transfer, output characteristic, gm and gds with local optimisation strategy and high emphasis on 3 low power applications. IDS [A]

2

NMODN + Meas. − BSIM3v3 W/L= 10/0.24 VD[V]=0.1 VB[V]=0,−0.65,−1.3,−1.95,−2.6, −3 1 10

−4 10 0 0 0.5 1 1.5 2 2.5 3 −5 VDS [V] 10

−6 10

−7

IDS [A] 10

−8 10

−9 −4 10 10

−10 10

0 0.5 1 1.5 2 2.5 VGS [V] GDS [A/V]

−5 10

−5 x 10 4

0 0.5 1 1.5 2 2.5 3 VDS [V] 3 Figure 1: NMOS output characteristic W/L=10/0.3,VGS=0.9,1.5,2.1,2.7,3.3V; +=measurements, - 2

=BSIM3v3 SPICE model . GM [A/V]

The old generation of transistor models like the most 1 common SPICE LEVEL2 or LEVEL3 did not care about the transition regions and therefore are not usable critical analog 0 0 0.5 1 1.5 2 2.5 design. Discontinuities in the first and second order derivative VGS [V] lead to wrong simulation results and often to convergence Figure 2: NMOS transfer characteristic problems. These problems exist in the equations for the W/L=10/0.24,VBS=0,0.65,1.3,1.95,2.6V; +=measurements, -- currents as well as for the charges and capacitances of the =BSIM3v3 SPICE model, -=BSIM4 SPICE model. MOS transistor. The new model generation like the BSIM3v3 Some weaknesses in modelling the transition region has been the Philips Level9 or the advanced BSIM4 [6.] model recognised for the BSIM3v3 model for processes smaller than transform the physical voltages like the gate voltage vgs into 0.35um. The BSIM4 model which includes some additional effective voltages vgseff (Eq. 1) to smoothen the transition physical effects like the pocket implant and additional fitting between the sub-threshold and the inversion region. parameters shows much better results in the transition region *  m ⋅Vgst  compared to the BSIM3v3 model. Fig. 2 shows the transfer n⋅v characteristic of a W/L=20/0.24um NMOS transistor where n⋅v ⋅ln1+ e t  t   the measurements and the models for the BSIM3v3 and the   V = BSIM4 model are compared. Both model-parameter sets are gsteff * ' (1) ()1−m Vgst −V off valid for all geometries and operating conditions and have * 2Φ been extracted from 10 different geometries and with the use m + n⋅Coxe s e n⋅vt q⋅ε N of the transfer, the output characteristic gm and gds, si dep respectively. These state of the art models will be more and more replaced by a new generation of models, which can be divided into two As an example equation 1 shows the improved effective groups. The “surface potential” models and the “charge gate voltage vgseff of the BSIM4v2 model - where n stands based” models. These modern models are based on a single for the sub-threshold swing, vgst is the effective voltage vgs- current equation for all operation regions and do not need any vth, Voff is the length dependent offset voltage and the smoothing functions. There are several “surface potential” parameter m* improves the accuracy of gm in the transition and “charge based” models under development or even region. The industry standard model BSIM3v3 which includes implemented in common SPICE simulators. The most a similar effective gate-source voltage shows acceptable important “surface potential” models are the SP model from results for the sub-threshold characteristic and the transition G.Gildenblat, the MOS Model 11 from R. van Langevelde regions for sub-micron processes larger than 0.25um. The and the HiSIM model from M. Miura-Mattausch. Notable where the total capacitance Cgg =C gs +C gd +C gb . Since gm is “Charge based” models are the EKV model from C. Enz, the proportional to Weff /Leff and Cgg is proportional to Weff *L eff , ACM model from C Galup-Montoro and the BSIM5 model FT is inversely proportional to Leff ^2. from W. Hu. g m 1 FT = ≈ 2 (2) III. RF MOS TRANSISTOR MODELLING 2π Cgg L eff CMOS technologies have resulted in deep sub-micron transistors with higher transit frequencies (FT) and maximum Note that this is only true at low lateral electrical field oscillation frequencies (Fmax). In view of system on chip where there is no velocity saturation. If ther carriers are realisation where digital, mixed signal base band and HF velocity saturated the F T only scales as 1/Leff . The transit transceiver blocks would be integrated, the RF performance of frequency F T as a function of the drain current Ids is shown in CMOS technologies is very attractive. Design tools with figure 4. Measured are performed on a 0.35um CMOS process accurate compact models for devices and interconnect for two different gate voltages. The model is based on the parasitic are very essential. sub-circuit in figure 3. 30

28

26

24

22

ft [GHz] 20

18

16

14

12 −5 −4 −3 10 10 10 Ids/W [A/um]

Figure 4: Measured and simulated (-) FT versus I DS at VDS =1.5V (+) and 3V (x). Figure 3: RF sub-circuit for a MOS transistor model

The state of the Art MOS transistor models (BSIM3, IV. NOISE MODELLING OF MOS TRANSISTORS EKV) have been developed for digital and low frequency The different noise sources of a MOS transistor are shown 2 2 2 analog circuit design. This models focus on DC drain current, in figure 5. They include: iG , iS and iD the Terminal 2 conductance, intrinsic charge and capacitance behaviour up to resistance noise contribution gate, source and drain, id is the 2 the megahertz range. For an RF model, which is accurate in noise contribution in the channel including Flicker noise, iDB , 2 2 the gigahertz range it is extremely important to include both iSB and iDSB are the noise contribution by the substrate 2 the intrinsic and extrinsic components of a MOS transistors to resistance and id is the induced gate noise achiev accurate and predictive results in the simulation of a designed circuit. A typical MOS transistor sub-circuit, which is used for RF application at austriamicrosystems is shown in figure 3. This equivalent circuit includes the BSIM3v3.2 model as intrinsic transistor, Rg as gate resistor, Rs and Rd as extrinsic source and drain resistors, the extrinsic source/drain to bulk junctions Djsb/jdb and the substrate resistors Rsub. This model fulfils the most important requirements for RF simulations with the extrinsic components, the accurate modelling of the bias dependent overlap capacitances and the accurate prediction of the small signal parameters. Newer models like BSIM4 or MOS Model 11 include already the Figure 5: Noise contributions to a MOS transistor extrinsic part inherently in the model with additional features like intermodulation distortion, high-speed large signal operation, HF noise modelling and NQS effects. The performance of RF devices is often evaluated by looking at their transit frequency ft, which is given by equations (2), directly depend on the effective gate voltage overdrive and the A. Flicker Noise Modelling noise current spectral density is defined It may occur that an analog design fulfils all of its first KF ⋅ I AF order parameters such as the gain or bandwidth, but that other D SID ( f ) = EF 2 (2) parameters such as the signal to noise ratio are out of spec. f Cox Leff Accurate estimation of such effects relies on a process description and SPICE modelling covering not just the KF ⋅ I AF S ( f ) = D standard characteristic curves but also the noise behaviour of ID f EF C W L (3) each active and passive device (Fig. 9). Low frequency noise ox eff eff (1/f noise) of MOS transistors is of special importance for 2 analog designs (LNA’s, A/D converters) since devices are KF ⋅ gm SID ( f ) = AF (4) becoming smaller and more compact. f Cox Weff Leff The flicker noise can be represented as a noiseless MOS 1 I transistor and noise sources in the gate and the drain current. S = ⋅ D ⋅ µ ⋅ [9.] The low frequency noise (LFN) of the gate current is iF 2 EF (= )1 eff COX ⋅ Leff f appreciable only in ultra thin gate oxide devices thus its effect (5) is usually neglected in the present noise models. A typical NOIA ,NOIB ,ΝΟΙC;    presently used MOS LFN equivalent circuit is shown on Fig ⋅ f1   N o (Vgsteff −VTH ), N l (Vgsteff −VTH ) 6. The access resistances RD and RS do not generate LFN   hence these sources can be omitted from the equivalent. The present 1/f noise models in the most widely used simulators PMOSM 10/10 Measurement Data are summarised in equation 2-5. The spectral density SID (f) is −10 10 proportional to the current I D for equation (2) and (3) or gm and inverse proportional to the oxide thickness C OX and the transistor geometry Weff and Leff . equations (2)-(4).

−11 10 Inoise [A/sqrt(Hz)]

−12 10

1 2 3 4 10 10 10 10 freq [Hz] Figure 7: . PMOSM current noise, measurement data [A/ Hz ], W/L=10/10,Bias Current: IDS= 1, 5, 20, 100 uA.

CSX, PMOSM, BSIM3V3, W=1e−05 L=1e−05 Ids[uA]: 100 50 20 10 5 2 1 −9 10

Figure 6: Typical LNA equivalent of a MOS transistor −10 10 Figure 7 shows the measured low frequency current noise

−11 [A/ Hz ] for a PMOS transistor in a 0.35 um process with 10

fixed bias currents IDS= 1, 5, 20, 100 uA. The IDS= 1 uA Inoise [A/sqrt(Hz)] bias (lowest curve) has a gate overdrive VGS-VTH=320 mV −12 working in the weak inversion transition region. For the 10 measurement of noise in such regions a special noise

measurement hardware unit with a low resolution limit −13 10 1 2 3 4 10 10 10 10 (preferably below 1 pA/ Hz ]) is needed. Frequency [Hz] For the modelling of weak inversion noise standard SPICE Figure 8: BSIM3V3 noise parameter extraction for PMOSM models (equation 2-4) are not sufficient for describing noise Hz in the low voltage regions since they do not include an measurement (smoothed) vs. extracted [A/ ], W/L=10/10, Bias Current: IDS= 1, 5, 20, 50, 100 uA, VGS-VTH: 0.32, 0.69, 0.97, explicit voltage dependence on the gate overdrive. Therefore, 1.39, 2.18, 3.19 V. more accurate models like the BSIM3V3 noise model [3.] have to be used in order to describe all geometric and voltage- Therefore, accurate high accuracy can be achieved in the dependent effects. In the BSIM3V3 model the carrier weak inversion region when parameter extraction is applied to densities at the source at the source (N o) and at the drain (Nl) optimise parameters NOIA, NOIB and NOIC. Fig.8 shows the optimisation result of a BSIMV3 noise slightly smaller than the long channel value. The induced gate parameter extraction for a PMOS transistor where accurate noise is not included in standard compact models like results could be achieved for the gate overdrive ranging from BSIM3v3 or EKV. The new generation models like BSIM4, 320 mV to 3.19 V from strong to weak inversion. The noise or MOS Mode 11 have included the induced gate noise effect. parameters evaluated to NOIA=1.09e+18, NOIB=6.01e+03 Generally the HF noise is characterised by a set of four and NOIC=1.19e-12. The integration of those noise parameters, namely: the minimum noise factor Fmin or parameters as part of the MOS transistor model enables the minimum noise figure NF = 10log(F ), the input referred designer the accurate prediction of the 1/f noise corner in the min min noise resistance Rv and the optimum source admittance low current region during circuit simulation. Yopt =G opt +jB opt for which the minimum noise figure is optained. B. Thermal Noise Modelling All noise sources contribute to the total noise in the MOS V. BIPOLAR TRANSISTORS IN CMOS TECHNOLOGY transistor. The dominant part is the channel thermal noise. The characteristic in saturation region has been studied for In CMOS technology bipolar transistors can be realised in over the last decades. In SPICE2 a simple thermal noise vertical and lateral direction. In figure 9 a symmetrical lateral model has been implemented which is shown in equation (6) PNP bipolar transistor is shown. Emitter E and Collector C are built with p+ diffusion and separated with a gate G for where kB is the Boltzmann constant T is the absolute exact definition of the base width. The primary transistor is temperature in Kelvin and G m is the transconductance of the device. Some other models have been also implemented in pictured as Q and the parasitic pnp transistors are shown as Qpc on the emitter and collector side. For accurate circuit different simulators as shown in equation (7-9), where G DS simulation both transistors must be modelled. A typical beta and Gmb are the channel conductance and bulk transconductance. Newer model generations have there own plot is shown in Figure 10, where the lateral beta (Ic/Ie), thermal noise model. For example BSIM3v3 includes which is used for design and the parasitic beta, the ratio of the substrate current and the emitter current (Is/Ie) is shown. equation (9) as thermal noise description, where µeff is the effective carrier mobility, Leff is the channel length of the device and Qinv is the total inversion charge in the channel. 8⋅ k ⋅T ⋅G S = B m ID 3 (6) 8⋅ k ⋅T ⋅(G + G ) S = B m DS ID 3 (7) 8⋅ k ⋅T ⋅(G + G + G ) S = B m DS mb ID 3 (8) Figure 9: X-section of a PNP transistor in CMOS technology 4 ⋅ k ⋅T ⋅ µ S = B eff Q ID 2 INV (9) The standard SPICE Gummel Poon Model is used for the L eff PNP transistor model in Figure 10. The following issues A thermal noise model, which is widely used for noise should be considered in supporting a bipolar transistor model analysis but not implemented in any SPICE simulator is given for analog design in CMOS technology: in equation (10), where γ is a bias dependent factor which for 1. Physical based sub-circuit for accurate parasitic long channel devices is equal to unity in linear region and to substrate current. 2/3 in the saturation region. (10) 2. High accurate temperature modelling for band gap S ID = 4k B ⋅T ⋅γ ⋅Gm applications. The γ-factor has been used as a figure of merit to compare 3. Precise description of the intrinsic capacitances and the thermal noise performance of different device. Different resistors based on s-parameter measurements. models [13.] have been proposed to describe the geometry 4. 1/f noise modelling and voltage dependency of the γ-factor, but they are not implemented in SPICE. 5. Process related corner modelling for robust design. The physical origin of the induced gate noise is the same as the channel thermal noise at the drain. Therefore the two VI. MODELLING OF PASSIVE DEVICES IN CMOS noise sources are correlated [14.]. For long channel transistors TECHNOLOGY in strong inversion and in saturation the correlation coefficient Passive devices such as resistors, capacitors, inductors and is c=j*cg with cg=0.4 [14.]. For short channel devices the varactors find a wide usage in analog and RF CMOS correlation factor c remains mainly imaginary with a value integrated circuit design. Resistors are supported in form of In the case of single ended operation one of the terminals is poly, high resistive poly, diffusion or well resistors. connected to AC ground.

Figure 12: Standard single ended inductor sub-circuit model. Figure 10: Beta plot of a parasitic lateral PNP transistor in 0.35um CMOS technology After transforming the measured two-port S-parameter data For analog design the correct modelling of the voltage and to Y-parameters important electrical parameters for P1 drive temperature dependency as well as the parasitic capacitance is (P2 connected to AC ground) operation can be calculated important. The resistor value is in first order a function of the from the impedance Z=1/y 11 as geometry where length and width have to be taken as Im(Z) effective values into account. Diffusion and well resistors are Effective Series Inductance: L = modelled as JFET for accurate modelling of the voltage ω dependency and the parasitic capacitances and diode leakage Im(Z) currents. Quality Factor: Q = Re()Z 26.18 Since the model is not scalable designers have to be 26.16 < 175 deg C provided with inductor models covering a broad inductance (1 26.14 nH – 20 nH) and frequency (0.9 GHz-6 GHz) range. The < 150 deg C 26.12 extracted inductance and quality factor are presented for a

< 125 deg C thick metal inductor in Fig.15. 26.1 7 10 < 100 deg C 26.08 Cap [pF]

26.06 < 75 deg C 6.5 8

26.04 < 50 deg C 6 6 26.02 < 25 deg C Q L [nH] 26 < 0 deg C 5.5 4

25.98 −8 −6 −4 −2 0 2 4 6 8 V [V] 5 2 Figure 11: MIM capacitance as a function of bias and temperature 4.5 0 0 1 2 3 4 5 6 frequency [Hz] 9 x 10 In Figure 11 the analog model and the measurement of a MIM Figure 13: Measured and simulated (-) effective capacitor is demonstrated as a function of bias and series inductance (+) and Q factor (o) as a function of temperature. In CMOS technology Metal-Metal (MIM), poly- frequency.symbols: measurement, -: simulation. poly (PIP), MOS transistor and sandwicht (poly-metal) are realisable and used for analog design. For RF integrated circuit simulation additionally to the analog VII. STATISTICAL MODELLING characterisation the accurate frequency dependency of the Designers need physical, predictive, and accurate device is essential. statistical models to describe the devices and hence the circuit A key component in VCOs is the inductor. The sub-circuit parameter variation caused by process variation. The device model shown in Fig.12 has been used for inductor modeling. parameter variations are divided into two categories, interdie preferred to perform worst case modeling and the PFA variation and intradie variation/mismatch. The interdie method is mostly used to identify dominant parameters. variation describes the die to-die, wafer to wafer or lot to lot The advantage of non-parametric analysis is mainly given process variability. The intradie device variation/mismatch by the fact that measured electrical data can directly used, it variation describes the die-/wafer level process variability works for any distributions for worst-case analysis, it can across the die/wafer. This effect is also called local process handle large number of samples with many parameters and it variation or device mismatch where devices in the same cuts down the time and number of parameter extractions. circuit may have different variations of some process parameters such as oxide thickness or doping. Mismatch has A special statistical modeling method has been introduced larger influences in some analog designs such as current by C. McAndrew [16.]. The backward propagation of mirrors with a constant current bias where interdie variation is variance method (BPV) is based on physical process not that important. For digital circuits the simulation of parameter propagation of variances and allows modeling of interdie variations is more essential because the influence it is process extremes, distributional modeling for Monte Carlo much larger than the mismatch variability. For robust design type simulation and mismatch modeling. and high yield it is essential for a analog/RF Design Kit to austriamicrosystems [15.] propose a non-parametric support Worst Case, Monte Carlo and Mismatch models. statistical method the Location Depth Corner Method (LDCM) to find sets of simulation parameters that cover the A. Worst Case Modelling and Simulation process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors Most foundries support Worst Case Models where the using a location depth algorithm (s. Figure 14). The e-test SPICE parameters (e.g. VTHO, LINT, TOX in BSIM3) are corner vectors are then transformed to SPICE parameter set to the specification limits (s. Figure 14) of the vectors by a linear mapping. A special corner extension corresponding process parameter (e.g. VTN, LEFF, TOX). algorithm makes the resulting simulation setup robust against This process parameters are specified in the design documents moderate process shifts while preserving the underlying of the corresponding foundries and based on a 6 or 3 sigma correlation structure. To be applicable in a production and parameter distribution. Corners are constructed to circuit design environment, the models are integrated into an maximize/minimize one specific performance of a device automated model generation flow for usage within a design- such as the saturation current IDSAT or the Gate capacitance framework. The statistical methods are validated for CGG for the MOS transistor. The resulting corners are analog/mixed-signal benchmark circuits. constructed from different device groups like MOS and Bipolar transistors, resistors and capacitors. The robustness of the design is assumed if all worst case combinations are within the specification including extreme temperatures. The Worst Case Simulation gives information about the robustness, the sensitivity with respect to parameter combinations or device groups but not about the yield of the designed circuit.

B. Monte Carlo Modelling and Simulation With Monte Carlo (MC) simulation a direct yield estimation of the given integrated circuit can be performed. Device parameters like the threshold voltage VTH and the effective channel length Leff are randomly distributed according to the process specification where as basic parameters allowed to vary independently and device correlation is generally included. MC simulation allows a Figure 14: Parameter distribution of NMOS and PMOS simultaneous examination of process variation and mismatch. threshold voltage. Red dots represents the Worst Case condition. Green dots the results of the LDCM C. Statistical Model Parameters Statistical model parameter sets are performed generally D. Mismatch Modelling with two different multivariate methods namely parametric and non-parametric statistical methods. State of the art tools In addition to large-scale process variations, which may – from Agilent (IC-Cap) and from Silvaco (SPAIN) support the and will – occur between different wafer lots, silicon generation of parametric statistical models for principal performance will also vary on the microscopic scale affecting component analysis (PCA) and principal factor analysis devices placed on the same die. These local or matching (PFA). PCA transfer the correlated parameters into a set of effects are often even more critical for designs and the uncorrected parameters whereas PFA performs a similar availability of statistically accurate matching parameters can rotation based on dominant parameters. The PCA method is be used to significantly reduce the risk of low-yields. As anlog designs operate at voltages close to the threshold provided to enable yield prediction during circuit simulations voltage, voltage and geometry dependent mismatch taking both process variations and mismatch effects into parameters for MOS transistors are essentially. The expected account. MOS transistor current mismatch increases at lower gate- source voltages vgs and the geometry dependency in case of NMOS transistors of a 0.35 µm process is shown in Fig.7. The Author

+ ... Measurement, − ... Mismatchmodel 2 10 Ehrenfried Seebacher received the M.Sc. degree in physics from Graz University of Technology, Graz Austria, in 1993. From 1994 to 1998, he was with the Research and Development Department, austriamicrosystems AG, Schloss

1 10 Premstätten, Austria, working on SPICE modeling of CMOS, BiCMOS, and HV CMOS processes. Since 1999, he has been W/L = 0.6/0.3 the Section Manager of the Process and Device

W/L = 1.5/0.6 Characterization group at austriamicrosystems AG. The group

0 is responsible for device modeling, process characterization,

Sigma(Delta(ID)/ID) [%] 10 W/L = 5/0.3 verification run-sets, and SPICE simulator support. His main W/L = 4/1 research areas are compact modeling of MOS transistors,

W/L = 12/2 bipolar transistors, and passive devices.

−1 10 0 0.5 1 1.5 2 2.5 3 VG − VT [V] VIII. REFERENCES Figure 15: Mismatch characteristics of NMOS transistors in [1.] ELDO User's Manual 5.6, Release 2001.2, August a 0.35 µm CMOS process. +=measurements, =mismatch model. 2001, p. 10/258-10/262 A variance model based on that proposed by Bastos [10.] [2.]Cheng. Y., Jeng M.C., Liu Z., Huang J., Chen M., Ko is used to fit the measured mismatch data σ(∆ID/I D) that is P.K., and Hu C.: and Hu,C.:A physical and scalable I-V gained from MOS transistors of different geometries. In this model in BSIM3v3 for analog/digital circuit simulation IEEE variance model the sensitivity of the fitting parameters (e.g. Electron Devices 1997, 44 (2), pp. 277-287. 2 2 σ (∆VT), σ (∆κ)) ensures that all parameters are equally well [3.] Department of Electrical Engeneering and Computer determined. This means that the current mismatch Sience: BSIM3v3 Manual, University of California, Berkeley. performance σ(∆ID/I D) in the operating region around the [4.] C.Enz, F. Krummenacher, E. Vittoz, “An analytical threshold voltage - the most important region in case of low 2 MOS transistor model valid in all regions of Operation and power design - is dominated by the mismatch of σ (∆VT). At dedicated to low-voltage and low current applications”, Jornal 2 higher gate voltages σ (∆κ) becomes the dominant parameter on Analog Integration Circuits and Signal Processing, Kluwer and in this region additionally the variation of the mobility Academic Pub. 1995, pp83-114. reduction is important. Another advantage of the variance model approach is that only a single fit is needed, which [5.] R.M.D.A. Velghe, D.B.M. Klaassen, F.M. Klaassen, prevents the mismatch parameters from picking up MOS model 9, NL-UR 003/94,1994. Internet: additionally “fitting noise”. Scaling of the mismatch http://www.semiconductors.philips.com/Philips_Models. parameters is done by using the well known Pelgrom’s law [6.] Weidong Liu, Xiaodong Jin, Kanyu M. Cao, [11.] which defines the geometry dependence of the mismatch Chenming Hu, Project Director:Professor Chenming Hu: parameters. BSIM4.0 MOSFET Model, User’s Manual, University of California, Berkeley. [7.] J. Watts, C McAndrew, C. Enz,C. Galup-Montoro, G. Gildenblatt, C Hu, R. van Langevelde, M. Miura-Mattausch, R Rios, C-T Sah, ”Advanced Compact Models for MOSFETs”, NSTI-Nanotech 2005, www.nsti.org. [8.] B. Ankele, W. Hölzl and P. O'Leary, "Enhanced MOS Parameter Extraction and SPICE Modelling for Mixed Analogue and Digital Circuit Simulation", 1989 IEEE International Conference on Microelectronic Test Structures, Edinburgh 1989 Figure 16: σ(∆VT) as a function of the device geometry 1/ √(W ⋅L) – Pelgroms law. [9.] A. Laigle et al. “MOSFETs Flicker Noise Modeling for Circuit Simulation,” Advanced Compact Modeling This is shown in case of the threshold voltage mismatch Workshop, Estoril, 19-Sep-2003 σ(∆VT) of NMOS transistors of a 0.35 µm CMOS process in [10.] J. Bastos, M. Steyaert, A. Pergoot and W. Sansen: Fig.8. Statistical SPICE model sets (Monte Carlo models) are “Mismatch Characterisation of Sub micron MOS Transistors” , Analog Integrated Circuits and Signal Processing, 12, 95-106(1997), Kluwer Academic Publisher, Boston, 1997. [11.] M. Pelgrom, A. Duinmaijer and A.Welbers: “Matching Properties of MOS Transistors”, IEEE Journal of Solid-State Circuits, Vol.24, October 1989. [12.] Kwok K. Hung, Ping K. Ko, Chenming, Hu, Yiu C. Cheng, “A physics based MOSFET Noise Model for Circuit Simulators”, IEEE Transactions on Electron Devices, Vol. 37, No. 5, May 1990. [13.] A.J. Scholten “Compact modeling of drain and gate current noise for RF CMOS” IEDM 2002. [14.] A. van der Ziel, “Noise in Solid-State Devices and Circuits”, John Wiley, 1986 [15.] G. Rappitsch,” SPICE Modeling of Process Variation Using Location Depth Corner Models”, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 2, MAY 2004 [16.]Colin C.McAndrew and Patrick G.Drennan, “Unified Statistical Modeling for Circuit Simulation”, WCM-MSM 2002