32-Nm RF CMOS Technology

RF CMOS Technology Scaling in High-k/Metal Gate Era for RF SoC (System-on-Chip) Applications

C.-H. Jan, M. Agostinelli, H. Deshpande, M. A. El-Tanani, W. Hafez, U. Jalan, L. Janbay, M. Kang, H. Lakdawala*, J. Lin, Y-L Lu, S. Mudanai, J. Park, A. Rahman, J. Rizk, W.-K. Shin, K. Soumyanath*, H. Tashiro, C. Tsai, P. VanDerVoorn, J.-Y. Yeh, P. Bai Logic Technology Development (LTD), Intel Corporation, Hillsboro, Oregon, USA *Integrated Platform Research/Radio Integration Research (RIR), Intel Labs, Intel Corporation, Hillsboro, Oregon, USA Contact: e-mail [email protected]

Abstract tures (<0.13 um), oxide /poly gate structures with strained sili- The impact of silicon technology scaling trends and the con (90 nm/65 nm), and high-k/metal gate technology with associated technological innovations on RF CMOS device charac- strained silicon (45/32 nm, Fig. 2) [1-11]. The corresponding teristics are examined. The application of novel strained silicon transistor pitch scaling has maintained a steady 0.7x per 2 year and high-k/metal gate technologies not only benefits digital sys- trend as shown in Fig. 3. The electrical Tox trend in Fig. 4 also tems, but significantly improves RF performance. The peak cut- followed a 0.7x per generation scaling trend until the 90 and 65 off frequency (fT) doubles from 209 GHz in the 90 nm node to nm nodes, where scaling stalled as further thinning of the silicon 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order dioxide resulted in unacceptably high gate leakage. Performance of magnitude from the 0.13 um node to the 32 nm node. Tran- enhancements at these technology nodes were achieved by the sistor noise figure, high voltage tolerance, and quality factors of incorporation of novel strained silicon technology. High-k/metal RF passives all show similar benefits from technology scaling. gate technology was brought into production starting at the 45 nm node to enable further dielectric scaling along with drive Introduction current and gm improvements as shown in Fig. 5. As silicon technology scaling progresses to the 32 nm node, single chip integration of RF and communication designs 1000 Metal Gate with the micro-processor cores on a common CMOS system-on- chip (SOC) platform has become increasingly appealing. This High - k 0.13 um 0.7x/generation increased attention to RF SOC is driven by both the huge improvements in device performance afforded by Moore’s Law 90 nm Si Ge and by the advantage of higher vertical integration and lower Pitch 65 nm manufacturing cost of mainstream CMOS technology. 45 nm 32 nm Modern technology scaling, however, is no longer a 100 Contacted Gate Pitch (nm) Pitch Gate Contacted simple matter of shrinking device dimensions. Today’s technolo- Fig. 2 State of the art 1995 2000 2005 2010 gy scaling is enabled by introducing disruptive, innovative mate- 32 nm PMOS high- Year of Product ion rials and novel device structures. Examples of these innovations k/metal gate transistor. Fig. 3 Intel CMOS transistor pitch scal- include strained silicon and high-k/metal gates for transistors ing trend and low-k ILD and Cu metallization in the backend. The impact of these new inventions to mixed signal/RF designs needs to be 10 examined with the intent to identify the true promise and chal- Non-st rained Strained Silicon Fig. 4 CMOS transis- lenges of radio integration into a general SOC platform. Oxide/ Ox i de / tor gate dielectric Poly Gat e Poly Gat e High-k/ thickness scaling Met al Gat e trend.

Tox = 0.7 x/ gen

Elect rical (Inv) (nm) Tox 1 0.55 0.35 0.25 0.18 0.13 90 nm 65 nm 45 nm 32 nm um um um um um Tech nology Node While digital systems are continuously benefiting by general CMOS scaling per Moore’s Law, CMOS implementation Fig. 1 Evolution of CMOS transistor architecture in the last decade, from a non-strained oxide/poly gate structure to a high-k/metal gate for RF and mixed signals presents different challenges. Fig. 6 strained silicon transistor at the 32 nm node. shows a typical fully integrated RF architecture, including key sub-systems of switches, PAs, LNAs, mixers, frequency synthe- CMOS Technology Scaling Trend sizers, ADCs, DACs and baseband processors. It can be seen Fig. 1 summarizes the main transistor architecture evo- from Table I that the key RF devices and their characteristics, lutions in the last decade - traditional oxide/poly gate architec- including device matching, linearity, cutoff frequencies, flicker

978-1-4244-7419-6/10/$26.00 ©2010 IEEE 27.2.1 IEDM10-604 noise, thermal noise, on-state and output resistance, and quality ⎛ 4 3 φε ⎞ ⎛ 4 ⎞ ⎛ ⎞ ⎜ q4 BSi ⎟ Tox ⎜ N ⎟ 1 ⎜ c2 ⎟ σVT = ⎜ ⎟ ⋅⋅ = (Eq. 1) factors of RF passives, emphasized in such analog subsystems 2 ε ⎜ ⋅ ⎟ ⎜ ⋅ ⎟ ⎜ ⎟ ox ⎝ LW effeff ⎠ ⎝ LW2 effeff ⎠ are very different from digital system requirements, and neces- ⎝ ⎠ Cut-off frequency f has also steadily improved with drive sitate distinct optimization of process and design methodolo- T current enhancements as shown in Fig. 8. The peak f of the gies. Furthermore, the monolithic integration of noise-sensitive T state of the art 32 nm NMOS is 445 GHz, twice as fast as the analog blocks alongside rapidly switching digital circuits places then-record 209 GHz for 90 nm. The benchmark of f vs. gate demanding requirements on the noise isolation capabilities of a T length in Fig. 9 shows that strained silicon and high-k/metal gate process; while the implementation of higher resistivity sub- implementation has enabled better cut-off frequency perfor- strates, triple-well architectures, and guard-rings can reduce the mance over the ITRS roadmap. This performance improvement impact of digital crosstalk, alternative analog layout techniques, can be explained by the simple analytical form of f in Eq. 2, such as clean power rails and differential circuit designs, are T namely that the transconductance improvement due to transis- often required. tor enhancements is outpacing the increase of the parasitic ca- RF Transistor Scaling Trend pacitance due to device geometry and dielectric scaling. Achiev- RF transistor matching performance has been improved ing higher cutoff frequencies via the scaling of RF CMOS tech- with the advance of technology scaling (Fig. 7). The transistor nologies will be increasingly challenging to maintain the transconductance gain outpacing parasitic increases due to shrinking matching coefficient c2 has been improved 40% since the 0.18 geometry and pitch. Fringing capacitance between the gate and um node, noting that c2 reduction slowed in the 90 and 65 nm nodes due to minimal oxide scaling. Through the implementa- the source/drain contacts will negatively impact Cgg, and gate resistance due to poly line-width scaling will present an obstacle tion of high-k dielectrics, Tox scaling resumed, enabling c2 scaling beyond 45 nm as explained by Eq. 1 [7]. Intra-die process to higher frequency operation. Alternative layout strategies and variations due to oxide thickness, doping profile, and work- transistor architectures will be required to mitigate such parasit- function variation represent another challenge for RF CMOS ic increases and enable cutoff frequencies to continue to scale. scaling. Such variations increase with scaling, and are responsi- gm fT = σ π C2 (Eq. 2) ble for local transistor mismatches. The VT in Fig. 7 shows ex- gg cellent control, remaining flat over the last three nodes.

2 RX Mi x er Table I Key RF device characteristics of Idsat @ 1V, 32nm LNA ADC primary RF circuit blocks 100nA/um Ioff 45 nm 65 nm Key Device 1.5 T/ R RF Devices RF Circuits 90 nm RF Characteristics Sw i t ch Sy n t h PLL MAC/BB, ADC, Logic Transistor Id , Id , V , I 0.13 um DAC sat lin t off 1 PA DAC ADC, DAC, Gm, Rout, Matching, MAC/ Baseband Analog Transistor Relat i ve Gm MAC/BB Linearity, Noise, NF Hi-k/ Met al Gat e TX Mixer min Strained Silicon PA, Mixer, T/R f , f , 1/f Noise, (RF Front End) (RF IC) (MAC/BB) RF Transistor T max NMOS Idsat Switch NF 0.5 Oxide/Poly Gate min Strained Silicon Ron, Linearity, f , f , Oxide/Poly Gate Apps Processor PA Transistors PA T MAX Non-St rained Si Efficiency, Breakdwn V,

Idsat (mA/um) and Relative Gm Relative and (mA/um) Idsat ADC, DAC, BB 0 Precision Resistors R, σR/R, Matching Filter, others 1000 Gate Pitch ( nm ) 100 Fig. 6 Typical fully integrated radio-on-chip Linear Capacitors PLL, VCO C, Q, Matching

architecture, including sub-systems of T/R Varactors PLL, VCO Tuning Ratio, Q, Kvco, Inductor/ PA, LNA, Mixer L, Q Fig. 5 Idsat and Gm scaling trend from switch, PA, LNA, Mixer, RF synthesizer, Transformer/Balun 0.13um to 32nm technology. ADC, DAC and baseband.

1.0 4 500 500 32 nm 3 2 nm ( t his w or k ) HIgh k/ 32 nm [11] (GHz) (peak fT= 445 GHz) 0.9 400 (GHz) 400 Metal Gate T 3 T 45 nm [8] C2 minimal 45 nm oxide scaling unit) (arb. (peak f T= 395 GHz) 65 nm [5] 0.8 T 300

(arb. unit ) 300 V 2 σV 2

T σ 90 nm [2] 65 nm 0.7 200 (peak f T= 360 GHz) 200 1 '09 ITRS 0.6 100 90 nm 100 '07 ITRS Normalized C Normalized NMOS high-k scaling Normalized (peak fT= 209 GHz) 0.5 0 f Frequency, Cut-off

0 f Frequency, Cut-off 0 0.01 0.1 1 0 0.010.020.030.04 Technology Node 1/Lg (nm-1) Ids (mA/um) Fig. 7 Transistor matching metrics, C2 and Fig. 8 State of the art cut-off frequency f scal- Fig. 9 Cut-off frequency f scaling trend vs. σ T T VT, scaling trends from 0.18 um to 32 nm. ing trend vs. Ids for 90nm to 32 nm nodes. 1/Lg for 90nm to 32 nm nodes. [2,5,8,11]

IEDM10-605 27.2.2

The scaling of the core VCC from 5V on the 0.8 um node gate technologies, can be quantified by the dependency of Cox in to less than 1V for the 32 nm node presents another deleterious Eq.4. aspect impacting RF designs. The voltage scaling of I/O and platform peripherals typically lags behind the CPU core voltage, ne- 2 K gm cessitating additional high voltage 1.8V-3.3V native oxide tran- Sid = (Eq. 3) f ⋅⋅ 2 sistors to be supported. PA integration in a monolithic SOC re- CLW ox quires devices that can sustain high voltage swings; a special S K 1 high drain-voltage (> 5 V) tolerant device has been developed Sv g LW id LW =⋅⋅=⋅⋅ which possess performance similar to the native 3.3 V I/O tran- 2 f 2 (Eq. 4) gm Cox sistor but with > 50% higher breakdown voltage (Fig. 10). The scaling trend for well architecture is transitioning from the tradi- The thermal noise trend of the minimum noise figure, tional twin well to triple well/deep n-well structures. The deep NFmin, is shown in Figs. 16 and 17 where a steady improvement n-well, Fig. 11, enables improved substrate noise isolation at low with scaling is observed from 0.18um to the 45nm nodes, but to moderate frequencies. In addition, parasitic NPN BJTs (Fig. saturates at the latest technology node. Fukui’s equation (Eq. 5) 12) and p-ch JFETs (Fig. 13) can be formed for applications which describes that NFmin improves with increasing gm driven by scal- require improved mixed signal/RF circuit noise performance. ing gate length and oxide thickness, but is negatively impacted by increasing parasitic components (i.e. Cgg and Rg) due to higher fringe capacitances and resistances due to the tighter pitch. RF Noise Scaling Trend – Flicker Noise and NFmin

Drain current noises, Sid (Eq. 3), and input referred gate π ⋅Cf2 += f +=+⋅ gg + noises, Svg (Eq. 4), are two key transistor metrics characterizing min K1NF sgm K1)RR(g sg )RR( fT gm (Eq. 5) flicker noise. Figs. 14 and 15 show that normalized Svg is mono- tonically decreasing with each successive technology node, re- sulting in a 10x reduction from the 0.18 um node to the 32 nm node. This benefit from oxide scaling, enabled by high-k/metal

1.E-09 DNW B S GD Substrate Noise 0.5 65 nm N+ Isolat ion 3.3 V I/O N+ P+ N+ N+ N+ p-well (mA) 0.4 I = C B 32 nm Deep n-well 1.E-10 50uA 3.3 V I/O p-epi 0.3 S GD Parasit ic p-JFET 40uA 3.3 V I/O 32 nm 2 Transist or D 30uA 3.3 V PA > 2 V N+ P+ N+ P+ N+ 0.2 1.E-11 1 p-well G Ioff (A/um) Ioff HV PA 20uA

ID [mA/um]ID Deep n-well Transist or 0 p-epi 0.1 0510 S 10uA NMOS @ 3.3 V VDS [V] EBC 1.E-12 Parasit ic NPN BJT I Current, Collector C 0 0.40.50.60.70.80.91 1.11.2 N+ P+ N+ P+ N+ 0123 B Ion (mA/um) p-well Deep n-well Collector-Emitter Voltge, VCE (V) p-epi Fig. 10 Ion/Ioff and breakdown voltage (in- E Fig. 12 Typical electrical characteristics of sert) comparison between native 3.3V I/O Fig.11 The applications of deep n-well ar- the parasitic NPN BJT fabricated with deep and HV PA transistors. chitectures for substrate noise isolation and n-well. additional parasitic devices.

1.E-10 0.1 32 nm, Vds=0.9V 45 nm, Vds=1.0V 1.E-08 65 nm, Vds=1.1V 90 nm, Vds=1.0 V High-k/

0.13 um, Vds = 1.3 V 1 Hz 1.E-11 Met al Gat e /Hz)

VBS = -5 V 2 0.13 um 1.E-09

90 nm @ /Hz) 2 /um

-4 V 2 0.05 1.E-12 65 nm (mA) -um 2 D I -3 V 1.E-10 45 nm 1.E-13

*W*L (V *W*L literature -2 V vg 32 nm

S this work -1 V

Svg* W*1.E-11 L (V 0 1.E-14 012345 10 100 1000 10000 100000 Frequency (Hz) Technology Node VDS (V) Fig. 13 Typical electrical characteristics of Fig. 14 Flicker noise scaling trend of 0.13 Fig. 15 Normalized input-referred flicker the parasitic p-ch JFET fabricated with um, 90, 65, 45 and 32 nm technologies. noise (Svg*W*L extrapolated to @1 Hz) deep n-well. scaling trend.

27.2.3 IEDM10-606 RF Interconnects and Passives Scaling Trend References Interconnect pitch and thickness scaling is part of the [1] S. Thompson et al., IEDM Tech. Digest, p. 61 (2002) continuous dimensional scaling as shown in Figs. 18 and 19. The [2] K. Kuhn et al., VLSI Technology Symp., p. 224 (2004) increased capacitance and resistance associated with interconnect scaling can compromise RF designs due to quality factor [3] P. Bai et al., IEDM Tech. Digest, p. 657 (2004) degradation of the spiral inductors built on the upper metal lay- [4] C.-H. Jan et al., IEDM Tech. Digest, p. 60 (2005) ers of the interconnect stack. At the 45 nm node and beyond, a [5] I. Post et al, IEDM Tech Dig., pp. 1-3 (2006) thick metal (TM) layer was added on top of the standard interconnect layers to serve as power gating devices and to construct [6] K. Mistry et al, IEDM Tech Dig., pp. 247-250 (2007) lower loss inductors to compensate for such interconnect scal- [7] K. Kuhn et al, IEDM Tech Dig., (2007) ing effects (Fig. 20). Inductors fabricated on the TM layer exhi- [8] C.-H. Jan et al, IEDM Tech. Dig., pp. 637-640 (2008) bit excellent performance when benchmarked with literature (Fig. 21). [9] S. Natarajan et al, IEDM Tech. Dig., pp. 941-943 (2008) Summary [10] C.-H. Jan et al, IEDM Tech. Digest, p. 28.1 (2009) RF CMOS technology is shown to benefit from the gen- [11] P. VanDerVoorn et al, VLSI Tech. Symp., p. 137 (2010) eral CMOS technology scaling. The majority of RF device performance metrics have steadily improved by the introduction of innovative transistor and interconnect technologies, including strained silicon and high-k/metal gates in the past decade.

3 0.13 um 6 layers 0.18 um [2] Literature 1 this work 2 90 nm [2] (dB) (dB) (dB) min min 32 nm [11] NF NF 1 32 nm 8 layers

45 nm 0.1 0 0 0.01 0.02 0.03 0.04 0 5 10 15 20 1/ Lgat e (nm-1) Frequency (GH z ) Fig. 16 Minimum noise figure performance Fig. 18 SEM images of 0.13 um 6 layer Fig. 17 Minimum noise figure (NFmin) scal- vs. frequency scaling trend. ing trend. metal stack vs. 32 nm [10] 8 layer interconnect stack.

1500 30 30 Thick Metal Literature This w ork

1000 20 20

Polymer

10 Cu 4.5 um TM 500 10 (Thick Met al) Q ( Qu al i t yFact or ) inductors by top metal layers (peak) Q Inductor M1 – M8 (excluding Thick Metal) 0 0 0

Int erconnect s (nm) Pitch Interconnect Top .13 um 90 nm 65 nm 45 nm 32 nm 0 5 10 15 Induct ance (nH) Fig. 19 SEM images of the 32 nm Thick Technology Node Fig. 21 Inductor Q benchmark as a func- Metal (TM) layer and the inductor made of Fig. 20 Interconnect pitch vs. inductor Q tion of inductance. the TM layer. scaling trend.

IEDM10-607 27.2.4