Potential and limitation of RF CMOS Technology and expectation for new passive devices

Akira Matsuzawa

Department of Physical Electronics Tokyo Institute of Technology

2004. 03. 02 TITech A. Matsuzawa 1 Contents

• Current status of RF CMOS technology • Feature of RF CMOS technology – Comparison with bipolar – Scaling rule – RF CMOS circuits – Architecture • Expectation for new passive devices – Inductor, resonator, switches – Needs for reconfigurable RF circuits • Summary

2004. 03. 02 TITech A. Matsuzawa 2 Current status of RF CMOS chip

RF CMOS was an university research theme, however currently becomes major technologies in the wireless world.

• Current products – Bluetooth: 2.4GHz, CSR etc., major – Wireless LAN: 5GHz, Atheros etc., major – CDMA : 0.9GHz-1.9GHz, Qualcomm, becomes major – Zigbee: 2.4GHz, not yet, however must use CMOS – TAG: 2.4GHz, Hitachi etc., major

Major Cellular phone standard, GSM uses SiGe-BiCMOS technology

2004. 03. 02 TITech A. Matsuzawa 3 Why CMOS?

• Low cost – Must be biggest motivation – CMOS is 30-40% lower than Bi-CMOS • High level system integration – CMOS is one or two generations advanced – CMOS can realize a full system integration • Stable supply and multi-foundries – Fabs for SiGe-BiCMOS are very limited. Æ Slow price decrease and limited product capability • Easy to use – Universities and start-up companies can use CMOS with low usage fee, but SiGe is difficult to use such programs.

2004. 03. 02 TITech A. Matsuzawa 4 Wafer cost example

The wafer cost of SiGe BiCMOS is 30-40% higher than CMOS at the same generation, however almost same as one generation advanced CMOS.

4500 4000 3500 3000 Low cost 30% 7M SiGe 23% 6M 2500 45% 5M 2000 45% 4M 1500 3M 1000 500 0

C 5_C B _C .3 um 0 0.25_C Ge_ 5 i .1 Dataquest March 2001 5S _SiGe_BC 0.18um_C 0 0.13um_C .2 25 +SiGe estimation 0 0. 2004. 03. 02 TITech A. Matsuzawa 5 RF CMOS device technology

RF CMOS needs some process options, however significant cost increase can’t be accepted.

Varactor Hi-Q inductor Thicker Metal

High Rsub Small Mismatch Small loss ESD RFRF High-R CMOSCMOS Higher Larger voltage Cap.

ConventionalConventional CMOSCMOS technologytechnology

2004. 03. 02 TITech A. Matsuzawa 6 MOS vs SiGe-Bip

MOS SiGe-Bip Ids Ids 4x Ids Ids Gm ≈ ≈ ⎛Veff ⎞ 100mV ⎜ ⎟ UT 26mV ⎝ 2 ⎠ Almost same 1 vsat fTpeak ∝ ≈ 2 Wb Lg

Lower and low Id 2 2 2Gp ⎛ f ⎞ Gp ⎛ f ⎞ Fmin 21 ++≈ 7.0 ⎜ ⎟ 21 ++≈ 25.0 ⎜ ⎟ ⎜ ⎟ 2gm fT gm ⎝ fT ⎠ (larger gm) ⎝ ⎠ 2x 200VGHz V*fT 100VGHz

2004. 03. 02 TITech A. Matsuzawa 7 MOS vs SiGe-Bip

MOS SiGe-Bip Same Rg,Rb Much better 1/f noise Better nmTox )( Mismatch mV ≈ umLW )( (SiGe-BiCMOS) Cost Low gm or larger current High gm or smaller current Voltage lowering Low noise and mismatch Geometry dependence Less geometry dependence Low performance and low cost? High performance and high cost?

2004. 03. 02 TITech A. Matsuzawa 8 Feature of CMOS technology

• Pros – Can use a switch and a voltage controlled conductance – Smaller distortion – No carrier accumulation – Can use switched capacitor circuits

– Can increase fT by scaling – Easy use of complementally circuits – Easy integration with digital circuits

• Cons – Low gm/Ids – Larger mismatch voltage and 1/f noise – Lower operating voltage with scaling – Difficult to enable impedance matching – Easily affected by substrate

2004. 03. 02 TITech A. Matsuzawa 9 Principal design for RF CMOS

• Use small size devices and compensate the accuracy and 1/f noise degradation. – Small parasitic capacitance is imperative. • Smaller capacitance is needed to keep higher cutoff frequency under the lower gm condition – Small size results in increase of the mismatch voltage and 1/f noise • Should be addressed by analog or digital compensation, not by increase of device size.

• Keep the voltage swing on ahigh as possible to realize higher SNR – The noise level is higher and gm is lower than those of bipolar.

• Use digital technology rather than analog technology – Performance increase and power and area decrease are promised by scaling. Analog is not so.

2004. 03. 02 TITech A. Matsuzawa 10 Scaling Rule: Basic principle of LSI technology

Scaling rule can improve almost all the performances of LSI Scaling also realizes higher integration and lower LSI cost.

L

W tox Scaling

Device/Circuit parameter Scaling Factor Device dimensions L, W, Tox 1/S S ≈ 2 Doping concentration S Voltage 1/S Field 1 Current 1/S Gate Delay 1/S Power dissipation/device 1/S2

2004. 03. 02 TITech A. Matsuzawa 11 Scaled CMOS technology

Current Scaled CMOS technology is very artistic.

Matsushita’s 0.13um CMOS technology

Gate Seven lattices SiO2

Si

100nm

Transistor Cu Interconnection

2004. 03. 02 TITech A. Matsuzawa 12 Performance trend of micro-processors

Performance of micro-processors has increased with device scaling.

1GHz IBM 21264 Merced

700MHz High-end US-3 P7 PC 21164 21264 500MHz 21164 R14000 400MHz PPC604e P6MMX2 NEC US-2 P6 300MHz P6 R12000 21164 PPC750 R4400 Pentium MMX R10000 Embedded 21064 R10000 SA110 200MHz P6 V830R R4400 R5000 SH4 s US r SA110 a V832 e Operating frequency R4300 y 2 Pentium / R4300 SH3 es 100MHz V830 m ti R4200 2 SH3 SuuperSparc R3900 R3000 V810 SH2 1994 1995 1996 1997 1998 1999 2000 2001 2002 (CY) Year 2004. 03. 02 TITech A. Matsuzawa 13 GHz operation by CMOS

Cutoff frequency of MOS becomes higher along with technology scaling and now attains over 100GHz.

0.13um fT : CMOS 100G gm 0.18um f : Bipolar (w/o SiGe) 0.25um T fT ≡ 50G 2πCin fT /10 (CMOS ) 20G 0.35um RF circuits vsat 10G fTpeak ≈ CDMA 5GHz W-LAN fT /60 (CMOS ) Cellular 2πLeff 5G Digital circuits Phone 2G Frequency (Hz) Frequency

1G

500M IEEE 1394 D R/C for HDD 200M

100M 1995 2000 2005 Year

2004. 03. 02 TITech A. Matsuzawa 14 Vdd and CMOS scaling limits

Lowest analog operating voltage is 1.2V -1.8V. Thus 0.18um – 0.13um must be a scaling limit for analog.

50 GHz-100 GHz is an available fT in CMOS technology. 4 ITRS ‘99 （ ） デジタル（上限）Digital Upper Technologyテクノロジーノード node Analogアナログ（上限） (Upper) 3 Analogアナログ（下限） (Lower)

2

1 Supply voltage (V) Digitalデジタル（下限） (Lower) Technology node (0.1um) Technology node 0 1‘00 2 3 4 5 6‘05 7 8 9 101112131415‘10

2004. 03. 02 TITech A. Matsuzawa 15 Difficulty of low voltage analog

Low voltage swing results in low SNR, because noise can’t be scaled.

N=2 100 95.918 VFS=5V V =3V 90 FS SNR (dB) 14bit 2 nkT VFS=2V Vn = SNRC()12, , C C 80 VFS=1V SNRC()22, , C 12bit SNRC()32, , C 2 70 ⎛CVFS ⎞ SNRC()52, , C SNR dB)( = log10 ⎜ ⎟

SNR (dB) ⎜ ⎟ 10bit ⎝8nkT ⎠ 60

51.938 50 0.1 1 10 100 0.1 1 10 100 0.1 C 100 Capacitance (pF)

2004. 03. 02 TITech A. Matsuzawa 16 Cost up issue by analog parts

The cost of mixed A/D LSI will increase when using deep sub-micron device, due to the increase of the cost of non-scalable analog parts. Large analog may be unacceptable. Some analog circuits should be replaced by digital circuits

I/O Wafer cost increases 1.3x Analog （0.35um : 1） for one generation

1 Digital 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0.35um 0.25um 0.18um 0.13um 0.35um 0.25um 0.18um 0.13um Chip area Chip cost 2004. 03. 02 TITech A. Matsuzawa 17 Minimum noise figure: Fmin

Fmin has been improved , however saturated at 1dB.

2 Technical points γ ⎛ fo ⎞ ⎛ 2 ⎞ αδ F min 1 +≈ ⎜ ⎟ ⎜ + gm R e q ⎟ + α ⎝ fT ⎠ ⎝ κ ⎠ κgm R e q High fT and low gate resistance. Small current in substrate. 8.0 PAD and ESD structure. 7.0 Output 6.0 5.0 M2 4.0 Imput L1 3.0

M1 Fmin (dB) 2.0 Cpi 1.0 Ls 0.0 Rsub 1 0.5 0.35 0.25 0.1 Gate length (μm)

2004. 03. 02 TITech A. Matsuzawa 18 Substrate effect on NF in MOS

NF in MOS is very low at on a chip measurement, But becomes very large when packaged! NFmin@5GHz，0.18um This is due to the substrate RF power loss

Packaged

On chip

MOS （Substrate loss shall be added, when packaged）

・Packaged：NFmin=1.6dB E.Morifuji, et al., SSDM98 pp.80-81 ・On chip：NFmin=0.4dB

2004. 03. 02 TITech A. Matsuzawa 19 Mixer

The passive mixer can be realized by CMOS only. High linearity, no 1/f noise effect, and low power are realized.

Active mixer (same as bipolar) Passive mixer (MOS only)

High conversion gain Larger power Low power No conversion gain High isolation Larger distortion High linearity No isolation, Bi-directional Larger 1/f noise No 1/F noise

Vin R R L L Vo Vo Lo Lo

Vo Vo Lo Lo Lo Lo Lo Vin Vin

Vin

2004. 03. 02 TITech A. Matsuzawa 20 1/f noise

1/f noise of MOS is larger than that of bipolar. For the lower 1/f noise, the larger gate area is needed.

2 Svf Δf 2 V = , vf ∝ TS nf LW f ox

Nch/Pch 0.4um Nch 0.4um/1.0um 1E-13 1E-13

/Hz) nMOS

2 W/L=800/0.4 /Hz)

2 Vdd=3V 1E-14 Vdd=3V 1E-14 Id=1mA Id=1mA

1E-15 1E-15

nMOS L=0.4um 1E-16 1E-16

pMOS 1E-17 1E-17 L=1.0um

1E-18 1E-18 2 Bipolar Bipolar

1E-19 Input referred noise (V voltage 1E-19 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 Input referred noise voltage (V 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07

Frequency (Hz) Frequency (Hz)

2004. 03. 02 TITech A. Matsuzawa 21 CMOS oscillator circuits

E. Hegazi, ISSCC 2001 Basic Low power (gm is higher) Low noise by filtering

Vo L L Vo Vo Vo Vo L L Vo L L C C Vc C C C C Vc Vc

Hi-Z at 2fo Cs Lx Vb Vb Vb Cx (a) (b) (c) 2004. 03. 02 TITech A. Matsuzawa 22 Oscillator phase noise progress

Phase noise in CMOS oscillator becomes lower than that of bipolar. The larger voltage swing in MOS Oscillator realizes lower oscillation phase noise. (High Q inductance is also very effective to reduce phase noise) ◆CMOS 11 ⎛ fo ⎞ -90.0 ■Si-bipolar/BiCMOS fL m)( ⋅⋅∝ ⎜ ⎟ 22 ⎜ ⎟ QV fm ▲SiGe-BiCMOS o ⎝ ⎠ -100.0

-110.0

-120.0 GHz,10mW,600kHz) １ -130.0 SSB Phase Noise

-140.0 [dBc/Hz](@ -150.0 1994 1995 1996 1997 1998 1999 2000 2001 2002

2004. 03. 02 TITech A. Matsuzawa Year 23 Architecture 1

Simpler architecture should be chosen to reduce power, area, and cost.

1) Super Heterodyne （Larger power, cost） RF IRF LNA RF IRF 1st Mixer IF SAW VGA 2nd Mixer LPF ADC To Digital

1-2 GHz 250 MHz 20 MHz 1.2-2.2 GHz 1st Synthesizer 2nd Synthesizer 2) Homodyne (Zero IF) （Lower power and cost, however... , ）

LNA Mixer LPF VGA ADC DC offset To Digital Lo leak 1/f noise 1-2 GHz Synthesizer 1-2 GHz 3) Low IF (Middle position） Digital processing

LNA Mixer BPF VGA ADC Mixer LPF

1-2 GHz 50 MHz Synthesizer 1-2 GHz OSC 2004. 03. 02 TITech A. Matsuzawa 24 Architecture 2

Analog circuits have been replaced by digital circuits. Small analog and big digital is a technology direction.

4) Low IF with ΣΔADC ΣΔADC Digital processing

LNA Mixer BPF Quantizer Mixer LPF

1-2 GHz 50 MHz OSC 1-2 GHz Synthesizer

5) Digital architecture ΣΔADC Digital processing Sampled LPF Quantizer LNA data LPF Mixer LPF Bluetooth receiver 0.13um CMOS 1.5V 1-2 GHz OSC Synthesizer 1-2 GHz

K. Muhammad (TI), et al., ISSCC2004, pp.268 2004. 03. 02 TITech A. Matsuzawa 25 Technology edge RF CMOS LSI

Many RF CMOS LSIs have been developed for many standards

Wireless LAN, 802.11 a/b/g Discrete-time Bluetooth 0.25um, 2.5V, 23mm2, 5GHz 0.13um, 1.5V, 2.4GHz

M. Zargari (Atheros), et al., ISSCC 2004, pp.96 K. Muhammad (TI), et al., ISSCC2004, pp.268

2004. 03. 02 TITech A. Matsuzawa 26 Advantage of SiGe Bi-CMOS

SiGe Bip has a great advantage in power consumption

Alcatel1) Oki Broadcom Conexant Mitsubishi Process CMOS CMOS CMOS SiGe-BiCMOS Si-BiCMOS 0.25um 0.35um 0.35um 0.5um 0.5um Chip sizeﾞ 40.1mm2 18.0mm2 17.0mm2

Rx_Sens. -80dBm -77dBm -80dBm -78dBm -80dBm

Tx_Power +2dBm +2.5dBm +5dBm +2dBm 0dBm

Rx 50mA 47mA 46mA 12mA 34.4mA Id Tx 70mA 66mA 47mA 16.4mA 44.0mA Vdd 2.5V 2.7-3.3V 3V(?) 1.8-3.6V 2.7-3.3V

2004. 03. 02 TITech A. Matsuzawa 27 Potential and limitation of RF CMOS

• Potential – RF CMOS are going to be a major in the wireless products. – SiGe Bi-CMOS technology will be used for only extremely low noise and low power RF products. – 60GHz or 100GHz CMOS circuits has already developed.

• Limitation – For low noise and low power characteristics in RF circuit, SiGe bipolar technology must be better than CMOS. – High power PA will not be integrated on scaled CMOS chip, due to low efficiency and needs low voltage operation. – Use of further advanced technology beyond 90nm would be limited. This is because low analog operating voltage of less than 0.9V and chip and development cost increase.

2004. 03. 02 TITech A. Matsuzawa 28 Expectation for new passive devices

This would sound inconsistent with RF CMOS technology RF CMOS technology is going to reducing analog and passive components. • However, passives are still important – High Q inductance • VCO: reduce power and phase noise • LNA: reduce power and noise figure – Tunable inductor • Multi frequency, yet single inductance. • Reconfigurable RF circuits – RF band pass filter – RF switches • TX/RX • Select frequency bands to address multi-standards • Reconfigurable RF circuits – On chip solid reference Oscillator 2004. 03. 02 TITech A. Matsuzawa 29 Inductor

Q of inductor determines almost all the performance of RF oscillator. Q is conventionally less than 10.

Noise: Vo Vo 1 L L Sφ ∝ Q2

Inductor Vc C C

Current 1 Vb I ∝ Q

RF-CMOS LSI RF-VCO

2004. 03. 02 TITech A. Matsuzawa 30 RF application of flip chip technology

High performance RF circuit has been realized by using the flip chip technology.

Qmax=63 @9.2GHz

W.P.Donnay, et al., ISSCC 2000, WA 19.1

2004. 03. 02 TITech A. Matsuzawa 31 Variable Inductor

Sliding plate can vary inductance by 50%. Wide tunable range VCO (2.4GHz to 5.1GHz) has been realized.

h=10μm TITech. Masu Lab. Sliding Conductor plate 50%

x 20μm 450μm

4μm 2.4GHz to 5.1GHz

2004. 03. 02 TITech A. Matsuzawa 32 RF MEMS switch

Mechanical low-loss integrated switch enables; Select or change inductance and capacitance Select signals and circuits; As a result, enables reconfigurable RF circuits

J. DeNatale, ISSCC 2004, pp. 310

2004. 03. 02 TITech A. Matsuzawa 33 Micromechanical-Disc Reference Oscillator

MEMS technology will realize an on-chip solid reference oscillator

Fo=61MHz Q=48,000 -145dBc/Hz far-end -115dBc/Hz @ 1KHz

Yu-Wei Lin, et al., ISSCC 2004, pp. 322

2004. 03. 02 TITech A. Matsuzawa 34 Multi-standard issue

Reconfigurable RF circuit is strongly needed for solving multi-standard issue. Multi-standards and multi chips Future cellular phone needs IMT-2000 IMT-2000 11 wireless standard!! RF BB Current GSM GSM RF BB

Bluetooth Bluetoth MCU RF BB

GPS GPS Power RF BB

Unification Future

Reconfigurable RF DSP Yrjo Neuvo, ISSCC 2004, pp.32 Unified wireless system

2004. 03. 02 TITech A. Matsuzawa 35 Summary

• RF-CMOS technology – Becomes major • Performance increase and full system integration due to scaling • Development of suitable circuits and architecture • Small analog and large digital is a right way • Low cost and huge supply capacity – However, some issues • For low power and now noise, SiGe Bi-CMOS is better • Limited use of further scaled CMOS beyond 90nm • Expectation of new passive device – Great demand for reconfigurable RF circuits: • Switches for the reconfigurability • On chip RF filter and Oscillator • High quality and tunable inductance

2004. 03. 02 TITech A. Matsuzawa 36