ICs: The Driver for Inform ation Technology www.csl.uiuc.edu

Integrated Circuits: The Driver for Information Technology IC Design High-speed Information Transfer

Project Goal: To demonstrate the benefits in power consumption

CAD and BER offered through the use of Error Correction Coding in the context of high-speed backplane I/O signaling (~5Gb/s).

datapath I/O Link Specs: LDPC Decoder MAP Decoder ECC-based Error-resilient • 5Gb/s data rate. EST On-chip Links FIR Filter • BER < 10-15 (post FEC). Design Estimator 1 • 10”, 20”, 34” channel lengths. devices circuits architectures systems • Power < 5mW/Gb/s. Fusion Estimator 2 Estimator N • µ • Circuits research at UIUC: devices to systems Block 0.18 m RF-CMOS process. st • Overarching themes are • 1 tape-out in 2007. – power minimization Estimator 3 – adapting to and exploiting nanoscale technologyMemory Data Stochastic Sensor Network-on-a-Chip

Data Converters RF Circuits for Wireless Communication FPGA: Field-programmable Gate Arrays

The analog world meets digital processing at the ADC… It is the most prominent and widely used • Today’s deep submicron technology is problematic for ASICs mixed-signal circuit in today’s integrated mixed-signal circuit designs. The ADC is also a useful vehicle DSP RF FRONT END DSP  Device technology scaling into nanometer region IQ Modulator IQ Demodulator – Cost of fabrication facilities and mask making has increased significantly for identifying advantages and limitations of future technologies with respect to system integration. has enabled CMOS design for RF Front End. DAC ADC – Physical effects are increasingly critical for power, reliability and speed  “All CMOS” design gives low-cost chips for next Analog Digital Processing 900 900 PA LNA generation broadband wireless access: 4G – Design complexity is high Ref. Proration Proration DAC ADC • An alternative: FPGA A/D  Nano-scale CMOS designs pose an extreme challenge: trade-off power efficiency, noise and – Short total turnaround time VCO PLL linearity. – No or very low NRE (none-recurring engineering) cost – Field-reprogrammable for upgrade and bug fix A/D1 ADF [S] and [Noise] Parameter Measurement for UWB LNA Power Amplifier for Wimax X – Suitable for low/medium volume production and prototyping applications U X

fclk/m U SHA M • CAD challenges for multi-million gate FPGAs E M Dout Low Noise Amplifier for UWB V . . . . D

in . . . . 1 – Synthesis with complicated clocking and timing constraints

- . . . . m m - 4Gs/s Track & Hold Amplifier – Synthesis for power reduction, e.g., glitch power and leakage power fclk 1 12 6 A/Dm ADF – Process variation-aware synthesis 10

f /m 4 NF50 (dB) • Design challenges for future FPGAs clk Chip layout (2×2 mm 2) 8 – 3D integration SoC Integration 6 S21 (dB) 2 – CMOS/Nanomaterial hybrid FPGAs 4 – Fault tolerance • Digitally equalized 1-GS/s 6-b low-power ADC for UWB radio 2 0 0 2 4 6 8 10 12 • Prototype implemented in 130-nm digital CMOS with 1.2-V supply freq, GHz

CAD: An Enabling Technology for IC Design IC Reliability and Manufacturability Poster Contributors • Charge exchange occurs • Modern complex ICs (nano-scale, between materials with billions of transistors) cannot be dissimilar electron affinities • Deming Chen • Yun Chiu designed without computer-aided Specification • Static discharges are 10 A design (CAD) software. unavoidable during IC • Milton Feng • Elyse Rosenbaum Architecture Design manufacutring, system assembly, product use. Current • Naresh Shanbhag • Martin Wong • Sample CAD research at UIUC: Logic Design • Typical current waveform at an IC pin during an ESD event is – Lithography-aware CAD shown to the right. Physical Design – Faculty members in Electrical and Computer – Chip-level wiring • Such high currents cannot be – Board-level wiring handled by nanoscale Engineering Chip – Chip planning transistors. – Research programs conducted in the – Layout verification • On-chip ESD protection circuits must be used. Coordinated Science Laboratory – CAD for low power design • UIUC research on protection – Research sponsors: NSF, SRC, DARPA, and circuit design, modeling and 1 ns Time test. industry

Global Infotech: Pathways to the Future with Global Partnerships