The Inverter
References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall © UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian, Addison Wesley Regions of Operation
Cutoff Non-saturated Saturated
Vgsp < Vtp Vgsp = Vtp Vgsp > Vtp Vin < Vtp + VDD Vin < Vtp + VDD p-device
Vin > Vtp + VDD Vdsp > Vgsp -Vtp Vdsp < Vgsp -Vtp Vout > Vin -Vtp Vout < Vin -Vtp
Vgsn > Vtn Vgsn > Vtn Vgsn < Vtn Vin > Vtn Vin > Vtn n-device
Vin < Vtn Vdsn < Vgs -Vtn Vdsn > Vgs -Vtn Vout < Vin - Vtn Vout > Vin - Vtn Digital Gates Fundamental Parameters
• Area and Complexity • Robustness and Reliability • Performance • Power Consumption Noise in digital Integrated Circuits
unwanted variations of voltaggges and currents at the logic nodes
V v(t) DD i (t)
(a) Inductive coupling (b) Capacitive coupling (c) Power and ground noise DC Operation: VltVoltage Transf er Ch aract eri iti(VTC)stic (VTC)
Vout
Vout = Vin VOH f
Switching Threshold Voltage VM (≠ Transistor Threshold Voltage)
VOL
VOL VOH Vin
Nominal Voltage Levels Mapping between analog and digital signals
V(y) V dV ‘1’ OH VOH out Slope = -1 = (gain) V1H dVin Undefined Region
dVout VIL Slope = -1 = ‘0’ dVin VOL VOL
VIL VIH V(x)
Undefined Region (Transition width TW) Definitaion of Noise Margins
NMH = VOH - ‘1’ VIH
VOH
NMH VIH Undefined Region
VI NML VO L L ‘0’ NML = VIL - VOL
Gate Output Gate Input Stage M Stage M+1 The Regenerative Property
V V V V V V V 0 1 2 3 4 5 6 A chain of inverters
5
V 3 0
V 1 1 V 2
-1 0246810 Conditions for Regeneration
Vout Vout
V3 f(v) finv(v)
f(V ) V V1 0 1
V3 finv (v ) f(v)
Vin V2 V0 Vin V0 V2 (a) Regenerative gate (b) Non-regenerative gate Fan-in and Fan-out
()F(a) Fan-outNt N
M
N (b) Fan-in M The Ideal Gate
Vout
Ri = ∞
g=g = -∞ Ro = 0
Vin VTC of Real Inverter VDD
5.0
NM 4.0 L
3.0 (V) out V 202.0 VM NMH 1.0
0.0 1.0 2.0 3.0 4.0 5.0
Vin (V) Delay Definitions
Vin
50%
t
t tpHL pLH Vout 90%
50%
10% t
tf tr Ring Oscillator
V V 0 V1 2 V3 V4 V5
V 0 V1 V5
T=2xtT = 2 x tp xNx N
2Ntp >> tf + tr Power Dissipation
P(t) = instantaneous power
Ppeak = ipeakVsupply = max (p(t))
1 T Vsup ply T Pav = p(t)dt = isup ply (t)dt T ∫0 T ∫0
Power-Delay Product
PDP = tp x Pav
= Energy dissipated per operation Static Load MOS Inverters Static Load MOS Inverters
Rload Ibias
Vout Vout
Vin Vin Basic Inverter
VDD
Vout
Vin
•Vin < Vth ; NMOS off; Vout pulled to VDD • Vin > Vth ; NMOS on, curren t fl ows th rough R to ground
• If R is sufficientlyyg large, Vout could be pulled down well below Vth; Stati c L oa d MOS INver ter
Ids R
Vout
Vout = Vds
Ids.R = VDD-Vds VTC of Resistive Load Resistive Load Device
Rload Voh = 5.0V
Vol = ???
Vout I = (Vdd-Vol)/R Vin
2 I = β.((Vdd-Vt)Vol-0.5Vol )
(Vdd −Vol ) R = 2 β.((Vdd −Vt )Vol − 0.5Vol ) Sizing for VOL
(Vdd −Vol ) R = 2 β.((Vdd −Vt )Vol − 0.5Vol )
Assume: Vdd = 5.0V Vt = 1.0V β = 10-4A/V
Proper design: Vol < Vt
Let: Vol = 0.5V
R = 24kΩ Resistor and Current-Source Loads
• RitResistance /lthfii/length of minimum-width lines o f var ious connecting elements is far less than effective resistance of the switched on MOSFET • In some memory processes, resistors are implemented by highly resistive undoped polysilicon • NlltitiCMOStiltNormally use transistors in CMOS to implement resistor and current-source loads • If biased for use as a resistor, called an unsaturated load inverter • If load transistor operates in saturation as a constant current source, called a saturated load inverter Pseudo NMOS Inverter
L = 1 Vout n
Vin
VDD + Vdsp = Vout ⇒ Vdsp = Vout -VDD ⇒ Vdsp = Vout + Vgsp
∴Vdsp > Vgsp -Vtp or Vout > - Vtp ⇒ Non-saturated region DC Transfer Characteristics Pseudo-NMOS Inverter
Vout
Vin
• DC current flows when the inverter is turned on unlike CMOS inverter • CMOS is great for low power unlike this circuit (e.g. watch needs low power lap-tops etc)
• Need to be turned off during IDDQ (VDD Supply Current Quiescent) testing PMOST Load with Constant VGS
Voh = 5.0V
Vol = ???
2 I = 0.5βp.(Vdd-Vtp)
2 Vout I = βn.((Vdd-Vtn)Vol-0.5Vol )
Vin 2 β n 0.5(Vdd −Vtp ) = 2 β p ((Vdd −Vtn )Vol − 0.5Vol ) Sizing for VOL
2 β n 0.5(Vdd −Vtp ) = 2 β p ((Vdd −Vtn )Vol − 0.5Vol )
Assume: Vdd = 5.0V Vtn = Vtp = 1.0V
Proper design: Vol < Vth
Let: Vol = 05V0.5V
β n = 4.26 β p Sizing for Gate Threshold Voltage (Trip Point)
N-device: saturated (Vout >Vin −Vtn) β I = n (V −V )2 dsn 2 in tn P-device: non-saturated
Vgsp = −VDD (V −V )2 I = β [(−V −V )(V −V ) − out DD ] dsp p DD tp out DD 2 Equatingβ the two currents we obtain,
(V −V )2 n (V −V )2 = −β [(−V −V )(V −V ) − out DD ] 2 in tn p DD tp out DD 2 Sizing for Gate Threshold Voltage
Solving for Vout
2 Vout = −Vtp + (VDD +Vtp ) − C
2 Where C = k (Vin -Vtn) β k = n β p
2 2 β n (VDD +Vtp ) − (Vout +Vtp ) Also, = 2 β p (Vin −Vtn )
To make gggate threshold voltage = 0.5VDD β n = 6.11 β p Noise Margin
βn/βp VIL VIH VOL VOH NML NMH 2 34451453.4 4.5 1.4 5 20052.0 0.5 4 1.8 3.3 0.6 5 1.2 2.7 6 1.4 2.8 0.35 5 1.05 3.2 8 112402451.1 2.4 0.24 5 086360.86 3.6 100 0.5 1.1 0.00 5 0.5 3.9 VTC of Pseudo-NMOS Inverter Unsaturated Load Inverter
Vout
Vin
• High is n threshold down from VDD • Used when depletion mode transistors were not available • Low noise margin • Might be used in I/O structures where p-transistors were not wanted VTC of Unsaturated Load Inverters
For k = 4
VOL = 0.24V VIH = 2.2V VOH = 38V3.8V VIL = 0.56V Current Source Load
Ibias
Vout Vout
Vin Vin Saturated Load Inverter
Vout Vin
•Vout > Vin -Vtn ⇒ driver transistor in saturation
– When Vin is small • Load transistor permanently in saturation
–Vdsp = Vgsp
– ∴Vdsp < Vgsp -Vtp or 0 < - Vtp ⇒ Saturated region When Vin is Small
β driver 2 I = (Vin −Vtn ) ds,driver 2
Load in saturation:
βload 2 I = − (Vout −V DD −V ) ds,load 2 tp
Equating the currents:
Vout = VDD +Vtp + k (Vin −Vtn ) β where k = driven βload VTC of Saturated Load Inverter
For k = 4
VOL = 0.24V VIH = 2.1V VOH =44V= 4.4V VIL = 0.5V NMOS Inverter
Use depletion mode transistor as pull-up
Vtdep transistor is < 0V0 V diffusion
VDD (poly) depletion mode transistor
Vout V enhancement mode out in transistor in
The depletion mode transistor is always ON:
gate and source connected ⇒ Vgs = 0
Vin = 0 ⇒ transistor pull down is off ⇒ Vout is high Vout vs Vin using Graphical Method
Ids (dep) Ids (enh)
Vgs =00= 0.0
Vgs = -0.2 VDD
VDD Vds (dep) Ids Ids Ids
Vgs (dep) = 0
Vgs (dep) VDD Vds (dep) VDD - Vds (dep)
Vds (enh) = VDD -Vds (dep) Vds (enh) = Vout VDD -Vds(dep) = Vds(enh) = Vout Therefore V = V -V In a steady state, out DD ds (dep)
Ids of both transistors are equal Gate Threshold Voltage
Gate threshold voltage = Vinv = Input voltage at which Vin = Vout
Assume that both driver and load are in saturation with input Vinv β β I = driver (V −V )2 DS (sat) 2 gs t β ∴ driver (V −V )2 = load (−V )2 2 inv t 2 dep VDD
βload Hence, Vinv = Vt −Vdep Vout β driver Vin
If βdriver is increased relative to βload then, Vinv decreases VTC of NMOS inverter
Slope |G| increases, Vinv decreases
β increasing driver
βload CMOS INVERTER CMOS Inverters The CMOS Inverter: A First Glance
VD D S
V in D Vout
CL
S Switch Model of MOS Transistor
|V| VGS |
|V| V ||V| < | V | GS T | VGS | > | VT | CMOS Inverter: Steady State Response V VDD DD
R on VOH = VDD VOL =0= 0
Vout
VM = f(Ronn,R, Ronp)
V = V in DD Vin = 0 PMOS Load Lines
IDn Vin = VDD -VGSp Idn = -IDP Vout =V= VDD-VDSp
Vout I IDp IDn Dn V = 0 in Vin = 0
Vin =3= 3 Vin =3= 3
V DSp VDSp Vout VGSp = -2
VGSp = -5 Vin = VDD + VGSp Vout = VDD -VDSp IDn = - IDp Construction Of Inverter Curves
Ids
Vds Construction Of Inverter Curves
Ids
Vds Construction Of Inverter Curves
Ids
Vds CMOS Inverter Load Characteristics
In,p Vin =5= 5 Vin = 0
PMOS NMOS
V = 4 Vin = 1 in
Vin = 3 V = 2 Vin = 3 in Vin = 2 Vin = 4
Vin = 3 Vin = 2 Vin = 1 Vin = 5 Vin = 0 CMOS InverterVTC 0.0 V in 5.0
0.0 5.0 Vout Inverter Supply Current ly pp sup =I dp =I nn d I Small Signal Model for an MOS Transistor
•Vsb = 0
• voltage-controlled current source (gm)
• output conductance (gds) • interelectrode capacitance
D Cgd G
gmVgs g Cgs + Cgb ds Cdb
S Output Conductance
• By differentiating Ids w.r.t. Vds • In linear region V 2 I = β[(V −V )V − ds ] ds gs t ds 2 1 gds = β[(Vgs −Vt ) −Vds ] Rlinear = β (Vgs −Vt −Vds ) • In saturation, device behaves like a current source:
the current being almost independent of Vds β I = [ (V −V )2 ] ds 2 gs t β d[ (V −V )2 ] dI gs t ds = 2 = 0 dVds dVds • In realit y, second ary e ffect s result i n a sl ope
gds = Idsλ Transconductance
• Expresses relationship between output current and input voltage
dIds gm = |Vds = constant dVgs
gm (linear) = βVds
gm (sat.) = β (Vgs −Vt ) MOS Transistor Small Signal Model
G + gmvgs r0 vgs -
S
gm ro
-1 Linear kVDS [k(VGS-VT-VDS)]
Saturation k(VGS-VT) 1/λID CMOS Inverter
VDD s Vout = VDD - Vsdp = VDD + Vdsp d Vin = VDD -Vsgp d =V= VDD +V+ Vgsp
V Vin out s
Vin = Vgsn, Vout = Vdsn Regions of Operation
Cutoff Non-saturated Saturated
Vgsp < Vtp Vgsp = Vtp Vgsp > Vtp Vin < Vtp + VDD Vin < Vtp + VDD p-device
Vin > Vtp + VDD Vdsp > Vgsp -Vtp Vdsp < Vgsp -Vtp Vout > Vin -Vtp Vout < Vin -Vtp
Vgsn > Vtn Vgsn > Vtn Vgsn < Vtn Vin > Vtn Vin > Vtn n-device
Vin < Vtn Vdsn < Vgs -Vtn Vdsn > Vgs -Vtn Vout < Vin - Vtn Vout > Vin - Vtn 0.0 Inverter Operating Regions V i n 5.0
0.0 5.0 Vout B: nmostsaturated A: nmostoff E: nmost linear reg. E: nmostlinear reg. D: nmostlinear C: nmostsaturated pmost linear reg. pmost linear p saturated pmost saturated pmost pmos most of tlit
saturated saturated li near reg. f Inverter Operating Regions
A: nmost off pmost linear region
B: nmost saturated pmostlit linear reg ion out out out out out
C: nmost saturated pmost saturated
D: nmost linear region AB CDE pmost saturated
Assume infinite ro E: nmost linear region when a device is in saturation pmost off Region A
(0 ≤ Vin ≤ Vtn)
Idsn = 0 ⇒ n-device is cut-off VDD p-device in linear region
Idsn = - Idsp = 0, as Idsn = 0
Vin Vout Vdsp = Vout -VDD
With Vdsp = 0, Vout = VDD Region B V (V ≤ V ≤ DD ) tn in 2 p-device in non-saturated region (Vds ≠ 0) n-device is in saturation
Idsp
Vin = Vgsn
Vout Idsn β Region B
2 β μ [Vin −Vtn ] nε Wn Idsn = n ; = ( ) 2 tox Ln
Vgsp = (Vin -VDD) & Vdsp = (Vout -VDD)
(V −V )2 ∴I = −β [(V −V −V )(V −V ) − out DD ] dsp p in DD tp out DD 2
μ pt Wp β p = ( ) tox Lp
Equating Idsp = -Idsn
2 VDD β n 2 Vout = (Vin −Vtp ) + (Vin −Vtp ) − 2(Vin − −Vtp )VDD − (Vin −Vtc ) 2 β p Region D V ( DD < V ≤ V −V ) 2 in DD tp p : saturation n : non-saturated Idsp
1 2 I Idsp = − β p (Vin −VDD −Vtp ) dsn 2 Vout V 2 I = β [(V −V )V − out ] dsn n in tn out 2
Idsp = −Idsn
2 β p 2 ∴Vout = (V in−Vtn ) − (Vin −Vtn ) − (Vin −VDD −Vtp ) β n Determining VIH and VIL RiRegion E
(Vin >= VDD -Vtp)
p: cut-off Idsp = 0 n: linear mo de
Vgsp = Vin -VDD → more positive than Vtp
Vout = 0 Region C (Bo th d ev ices in Sa tura tion )
β I = − p (V −V −V )2 dsp 2 in DD tp β I = n (V −V )2 dsn 2 in tn
EtiIEquating Idsp = -Idsn
β n VDD +Vtp +Vtn V = β p in β 1+ n β p Gate Threshold Voltage
If βn = βp & Vtn = -Vtp V V = DD in 2
Region C exists for one value of Vin
Possible values of Vout in region C n-channel Vin -Vout < Vtn Vout > Vin -Vtn saturation conditions p-channel Vin -Vout > Vtp Vout Vin -Vtn < Vout < Vin -Vtp In reality, region C has a finite slope - because in reality Ids increases slightly with Vds in saturation Typical Parameter Values (1μm process) 2 μn = 500cm /V − sec ε = 3.9×8.85×10−14 F / cm tox = 200A β με W n = ( ) tox L 500×3.9×8.85×10−14 W = .2×10−5 L W = 88.5 μA/V 2 L μ ≈180cm2 /V − sec pβ W ∴ = 31.9 μA/V 2 p L β n = 2.8 (The ratio varies from 2-3) β p βn/βp Ratio β n increasing β Vout p Vin Wn increasing Wp Vout Vin Effect of βn/βp Ratio β n Vm dependent on β p β n with change in β p transition still remains sharp and hence switching performance does not deteriorate It is desirable to have β n = 1 β p ⇒ allows capacitance load to change and discharge in equal times by providing equal current source & sink capability Gate Switching Threshold 4.0 3.0 MM V 2.0 1.00.10.31.03.210.0β p kp/kn β n r(VDD +Vtp ) +Vtn β p VM = with r = r +1 β n Effect of Temperature • Temperature similarly affects mobility of holes and eltlectrons • Temperature increases ⇒ μ decreases ⇒ β decreases β ∝ T −1.5 • Ratio βn/βp is independent of temperature to a good approximation • Temperature, however, reduces threshold voltages • Extent of region A reduces and extent of region E increases • VTC shifts to the left as the temperature increases Switching Characteristics • Switching speed - limited by time taken to charge and discharge, CL • Rise time, tr : waveform t o ri se f rom 10% to 90% o f its steady state value • Fall time, t f : 90% to 10% of steady state value • Delay time, td : time difference between input transition (50%) and 50% output level CMOS Inverter: Transient Response VDD tpHL = f(RonCL) = 0.69 RonCL Vout 1 VDD CL R on 0.5 0.36 R C Vin = VDD on L t CM OS Inv er ter Pr opagati on D el ay VDD CLVswing / 2 t pHL = Iav Vout I(V = V ) + I(V = V / 2) I = out DD out DD av 2 CL 2 2 Iav β n ⎛ 7VDD Vtn 3VDDVtn ⎞ = ⎜ + − ⎟ 2 ⎝ 8 2 2 ⎠ Vin = VDD Inverter Propagation Delay • Assume n-device still in saturation at Vout = VDD/2 β I = n (V −V )2 av 2 DD tn CLVDD t pHL = 2 β n (VDD −Vtn ) C ≈ L β nVDD CL t pLHLH ≈ β pVDD C ⎛ 1 1 ⎞ t ≈ L ⎜ β + ⎟ p ⎜ ⎟ 2VDD ⎝ p β n ⎠ Analysis of Fall Time VDD Vin(t) Vout(t) CL non-saturated x2 saturated Ids (Vds = Vgs -Vt) Application of step x1 input x3 Vout (t) VDD Components of Fall Time tf = tf1 + tf2 Vout drops from Vdd -Vt to 0.1 VDD Vout drops from 0.9Vdd to Vdd - Vt 0.9 VDD VDD - Vt 0.1 VDD Vin Vout tf Fall Time for Saturated Region P I Saturated, V ≥ V -V Input rising c out DD tn Vout Idsn C dV β n L C out + n (V −V )2 = 0 L dt 2 DD tn Integrating from t = t1 (corresponding to Vout = 0.9 VDD) to t = t2 (ditV(corresponding to Vout = (VDD - Vtn)) 0.9V CL DD t f 1 = 2 dVout 2 ∫V −V β n (VDD −Vtn ) DD tn 2CL (Vtn − 0.1VDD ) = 2 β n (VDD −Vtn ) Fall Time for Non-Saturated Region p Vout n CL Non-saturated : 0 ≤ Vout ≤ VDD -Vtn 2 dV V out C out + β [(V −V ).V − ] = 0 L dt n DD tn out 2 0.1V CL DD dVout t f 2 = ∫V −V 2 DD tn β n (VDD −Vtn ) V out −Vout 2(VDD −Vtn ) Fall Time for Non-Saturated Region 0.1V CL DD dVout t f 2 = ∫V −V 2 β n (VDD −Vtn ) DD tn V out −Vout 2(VDD −Vtn ) C 19V − 20V = L ln( DD tn ) β n (VDD −Vtn ) VDD C = L ln(19 − 20n) β nVDD (1− n) V where n = tn VDD Fall Time Computation t f = t f 1 + t f 2 CL ⎡(n − 0.1) 1 ⎤ = 2 ⎢ + ln(19 − 20n)⎥ β nVDD (1− n) ⎣ (1− n) 2 ⎦ CL t f ≈ k β nVDD k = 3 ~ 4 for VDD = 3 ~ 5V andVtn = 0.5 ~ 1V Rise Time CL ⎡( p − 0.1) 1 ⎤ tr = 2 ⎢ + ln(19 − 20 p)⎥ β pVDD (1− p) ⎣ (1− p) 2 ⎦ |V | with p = tp VDD CL tr ≈ k β pVDD For equally sized n- and p transistors βn ≈ 2βp t t ≈ r f 2 Sizing for Identical Rise/Fall Time For same tf and tr β n =1 β p Increase the width of p-device to Wp ≈ 2 − 3Wn Delay Time: First Order Approximation • Gate delay is dominated by the output rise and fall time t t = r dr 2 t t = f df 2 General Delay Time Computation • Similar to the computation of rise/fall times – Saturation region from t = t1 (corresponding to Vout = VDD) to t = t2 (corresponding to Vout = (VDD -Vtn)) – Linear region from t = t2 (corresponding to Vout =(V= (VDD - Vtn)) to t = t3 V CL DD t2 − t1 = 2 dVout 2 ∫V −V β n (VDD −Vtn ) DD tn 2CL (Vtn ) = 2 β n (VDD −Vtn ) Delay Time Computation ' V CL out dVout t3 − t2 = ∫V −V '2 β n (VDD −Vtn ) DD tn Vout ' −Vout 2(VDD −Vtn ) C 2V − 2V −V = L ln( DD tn out ) β n (VDD −Vtn ) Vout C 2(1− n) −V = L ln( O ) β nVDD (1− n) VO Vtn Vout where n = , VO = VDD VDD Delay Time CL tDn = t3 − t1 = An β nVDD Delay ∝ CL (optimize CL to decrease delay) 1 ∝ (decrease VDD increases delay) VDD 1 ∝ (if W ↑ or L ↓, delay decreases) β Three major parameters for optimizing speed of CMOS Components of CL Cw = wiring capacitance Cg = gate capacitance = CoxWL Miller Effect • Effective voltage change over the gate-drain capacitor is actually twice the output voltage swing • Contribution of gate-drain capacitor should be counted twice Junction Capacitance • Non-linear capacitor modeled by linear capacitor with the same change in charge for the voltage range of interest φ Ceq = KeqC j0 φ m − 0 1−m 1−m Keq = []( 0 −Vhigh ) − (φ0 −Vlow ) (Vhigh −Vlow )(1− m) • Linearize over the interval {5V, 2.5V} for the high-to- low transition and {0, 2.5V} for the low-to-high transition • Correspond to {Vhigh=-5V, Vlow=-2.5V} and {Vhigh=0, Vlow=-25V}f2.5V} for NMOS Delay in function of VDD Sizing of Inv er ter L oaded by an I den ti cal Gate Load cappg. of first gate: CL = (Cdp1 + Cdn1) + (Cgp2 + Cgn2) + CW where Cdp1, Cdn1 → diffusion capacitance of first gate Cgp2, Cgn2 → gate capacitance of second gate Cw → wiring capacitance If PMOS d evi ces are α times larger than the NMOS ones, (W / L) α = p (W / L)n all transistor capacitances will scale in approximately the same way Sizing of Inverter Cdp1 ≈ αCdn1 Cgp2 ≈ αCgn2 ∴CL = (1+α)(Cdn1 + Cgn2 ) +Cw tr + t f CL An Ap t p = = ( + ) 2 2VDD β n β p CL Ap β n = (An + ) 2VDD .β n β p CL Ap μn (W / L)n = (An + . ) 2VDD .β n μ p (W / L) p CL Ap μn = (An + ) 2VDD .β n μ pα Sizing of Inverter C β Aμ t = L (A + p n ) p n μ 2VDD . n pα (1+α)(C + C ) + C A μ = dn1 gn2 W (A + p n ) 2V .β n μ .α α DD n p ∂t Let p = 0 to get optimal α ∂ μn Ap CW αopt = (1+ ) μ p An Cdn1 +Cgn2 If CW << Cdn1 + Cgn2, Ap = An μ n CtContras tt3hihit to 3 which is norma lly use d α opt ≈ ≈1.73 μ p in the non-cascaded case Impact of Rise Time on Delay 2 2 tPHL (actual) = t pHL (step) +(tr / 2) Minimum-size inverter with fanout of a single gate Velocity Saturation 2 • Under long channel model, saturation current ∝ VDD • In small-geometry devices, this no longer holds: Iav ∝ VDD • Therefore, for VDD >> VT we have, CL 1 1 t p ≈ ( + ) kn, p = κvSAT CoxWn, p 2 k p kn • Running velocity saturated devices at high VDD is not beneficial • Lowering VDD below 2VT sharply increases delay Source/Drain Resistance • In small-geometry devices, source and drain resistance affects switching currents – Source of the transistor is no longer grounded, body effect increases threshold voltage –Vgs is also reduced – Current is reduced Power Consumption • Static Power – Leakage current – Sub-threshold conductance • Dynamic Power – Cappggggpacitive Power due to charging/discharging of capacitive load – Short-circuit power due to direct path currents when there is a temppyorary connection between power and ground Static Power Consumption V DD VDD Vout =V= VDD Diode leakage Vq / kT IO = is (e −1) Sub-threshold current (Vgs −Vt )q / nkT Vdsq / kT I D = K ⋅e (1− e ) Pstatic = Ileakage. VDD Static Consumption • Leakage current through the reverse biased diode junctions • For typical devices it is between 0.1nA - 0.5nA at room temperature • For a die with 1 million devices operated at 5 V, this results in 0.5mW power consumption → not much • Junction leakaggyye current is caused by thermally generated carriers -> therefore is a strong function of temperature • MiMore impor ttibtant is sub-thres ho ld lea kage w hen threshold voltage is close to 0 Dynamic Consumption due to CL VDD Vout - low-to-hig h trans it ion - Assume 0 rise and fall times Dynamic Power due to CL Vout VDD t in iVDD CL t discharge charge Define: EVDD : energy tktaken f rom suppl y d ur ing a transiti on EC: energy stored on capacitor at the end of transition Energy Consumed and Stored ∞∞ dVout EV = iVDD (t)VDDdt = VDD CL .dt DD ∫∫00dt VDD = CLVDD dVout ∫0 2 = CLVDD (= QVDD ) ∞∞ dVout EC = iVDD (t)Vout dt = CL Vout dt ∫∫00dt VDD = CLVDD Vout dVout ∫0 C .V 2 = L DD 2 Half the energy is stored in Capacitor ! Other half is dissipated in the PMOS transistor !! For each switching cycle ( L → H & H → L), amount of energy 2 dissipated in CL. VDD 2 Pdynamic = CL.VDD .f •Example –1.2μ CMOS chip – 100 MHz clock rate – Average load capacitance of 30 fF/gate – 5V power supply • Power consumption/gate = 75 μW • Design with 200,000 gates: 15W ! • Pessimistic evaluation: not all gates switch at the full rate • Have to cons ider th e ac tiv ity fact or α: Effecti ve swit chi ng capacitance = αCL • Reducing VDD has a quadratic effect on Pdynamic Direct Path Current • inputs have finite rise and fall times • Direct current path from VDD to GND while PMOS and NMOS are ON simultaneously for a short period Psc = Imean.VDD tr tf VDD + Vtp Vtn T Imax Imean t1 t2 t3 Symmetrical Inverter Without Load ⎡ 1 t2 1 t3 ⎤ Imean = 2 I(t)dt + I(t)dt ⎢ ∫t ∫t ⎥ ⎣T 1 T 2 ⎦ If Vtn = -Vtp=VT and βn = βp = β and that the behavior around t2 is symmetrical t 2 2 β 2 Imean = 2× (Vin (t) −Vt ) dt T ∫t1 2 VDD with Vin (t) = t tr Vt t1 = .tr VDD t t = r 2 2 tr = t f = trf Symmetrical Inverter Without Load t / 2 2β rf VDD 2 Imean = ( ⋅t −Vt ) dt ∫t V /V T rf T DD trf t / 2 ⎡ ⎤ rf 2β trf VDD 3 = ⎢ ( ⋅t −Vt ) ⎥ T ⎢3VDD trf ⎥ ⎣ ⎦trf VT /VDD 2trf β VDD 3 = ⋅ ( −Vt ) 3T VDD 2 trf β 3 = ⋅ (VDD − 2Vt ) 12T VDD β t P = (V − 2V )3 rf sc 12 DD t T Short Circuit Current with Loads Output Transitions under Different Loads CL Power vs. SC Power under Different Loads CL Power vs. SC Power under Different Inputs Impppact of Load Capacitance on SC Current • Large capacitance – Fast input transition, slow output transition – Input moves through the transient region before output begggins to change – Short-circuit current close to zero • Small capacitance – Relatively slower input transition, fast output transition – Both devices in saturation during most of the transition – Maximum short-circuit current • [Veendrick84]: rise/fall times of all signals should be kept constant within a range to keep SC power minimal, 10%~20% of total dynamic power Technology Evolution Technology Scaling (1) Minimum Feature Size Technology Scaling 108 107 mosfet 106 pp 105 bipolar transistor 104 nents/Chi mesfet oo 103 enhancement Comp 2 mosfet 10 bipolar Transistor 101 IC 1 1950 1960 19701980 1990 YEAR Number of components per chip Proppgagation Dela y Scalin g 1n F/O = 1 R.T. Operation 500p ) ee Ref.[4] 200p 3.5V Ref.[5] (sec/stag d 100p 3.5V DD τ Present Results 2.5V 3.3V Reported Results 50p Ref.[7] 2.5V e Delay: tt VDD VDD=5V Ga 20p Scaling 10p 101.0 0.1 050.5 505.0 10. 0 Channel Length : Left (μm) Technology Scaling Models • Full Scaling (Constant Electrical Field) ideal model — dimensions and voltage scale together by the same factor S • Fixed Voltage Scaling most common model until recently — only dimensions scale, voltages remain constant • General Scaling most realistic for todays situation — voltages and dimensions scale with different factors Scaling Relationships for Long channel Devices Scaling of Short Channel Devices Homework Problem (due next Thursday) • Design a static CMOS inverter with 0.4pF load capacitance. Make sure that you have equal rise and fall times. Layout the inverter using the Mentor tools, extract parasitics, and simulate the extracted circuit on HSPICE to ma ke sure tha t your des ign con forms to the spec ifica tion. • Do the same analysis for a three input NAND gate.