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Logical Effort Logical Effort: Outline Designing for Speed on the Back of an Envelope o Introduction o David Harris Delay in a Logic Gate o Multi-stage Logic Networks [email protected] o Choosing the Best Number of Stages o Example Harvey Mudd College o Asymmetric & Skewed Logic Gates Claremont, CA o Circuit Families o Summary Logical Effort David Harris Page 2 of 56 Introduction Example Chip designers face a bewildering array of choices. ? ? ? Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded processor for automotive applications. Help Ben design the decoder for a o What is the best circuit topology for a function? register file: a<3:0> a<3:0> 32 bits o How large should the transistors be? o How many stages of logic give least delay? Decoder specification: o Register File Logical Effort is a method of answering these questions: 16 word register file 16 o 16 words Each word is 32 bits wide 4:16 Decoder o Uses a very simple model of delay o Each bit presents a load of 3 unit-sized transistors o Back of the envelope calculations and tractable optimization o True and complementary inputs of address bits a<3:0> are available o Gives new names to old ideas to emphasize remarkable symmetries o Each input may drive 10 unit-sized transistors Who cares about logical effort? Ben needs to decide: o Circuit designers waste too much time simulating and tweaking circuits o How many stages to use? o High speed logic designers need to know where time is going in their logic o How large should each gate be? o CAD engineers need to understand circuits to build better tools o How fast can the decoder operate? Logical Effort David Harris Page 3 of 56 Logical Effort David Harris Page 4 of 56 Outline Delay in a Logic Gate o Introduction Let us express delays in a process-independent unit: o τ ≈ 12 ps Delay in a Logic Gate d in 0.18 μm o d = ----------abs- Multi-stage Logic Networks τ technology o Choosing the Best Number of Stages Delay of logic gate has two components: o Example effort delay, a.k.a. stage effort o Asymmetric & Skewed Logic Gates parasitic delay o Circuit Families dfp= + o Summary Effort delay again has two components: logical effort electrical effort electrical effort = Cout/Cin is sometimes fgh= called “fanout” o Logical effort describes relative ability of gate topology to deliver current (defined to be 1 for an inverter) o Electrical effort is the ratio of output to input capacitance Logical Effort David Harris Page 5 of 56 Logical Effort David Harris Page 6 of 56 Delay Plots Delay Plots 6 g = 6 d D p = g = 4/3 : 5 N d y A d = D p = 2 : a N g = 5 N t y A d = (4/3)h + 2 4 u p = a N g = 1 p t n 4 u p = 1 -i d = p 2 n 3 inverter -i d = h + 1 lized del lized 3 2 inverter a effort How about a lized del lized 2 delay 2-input NOR? a effort 2 delay Norm 1 parasitic delay Norm 1 parasitic delay 1 2 3 4 5 1 2 3 4 5 Electrical effort: h = Cout / Cin Electrical effort: h = Cout / Cin o dfp==+ gh+ p o dfp==+ gh+ p o Delay increases with electrical effort o Delay increases with electrical effort o More complex gates have greater logical effort and parasitic delay o More complex gates have greater logical effort and parasitic delay Logical Effort David Harris Page 7 of 56 Logical Effort David Harris Page 45 of 56 Computing Logical Effort A Catalog of Gates DEF: Logical effort is the ratio of the input capacitance of a gate to the input Table 1: Logical effort of static CMOS gates capacitance of an inverter delivering the same output current. Number of inputs Gate type o Measured from delay vs. fanout plots of simulated or measured gates 12345 n o Or estimated, counting capacitance in units of transistor width: inverter 1 NAND 4/3 5/3 6/3 7/3 (n+2)/3 NOR 5/3 7/3 9/3 11/3 (2n+1)/3 a NOR2: multiplexer22222 2 4 C = 5 b in XOR, XNOR 4 12 32 2 2 g = 5/3 x 4 Table 2: Parasitic delay of static CMOS gates x x Gate type Parasitic delay a 2 p ≈ 1 1 inverter pinv inv a 1 n-input NAND npinv parasitic delays Inverter: NAND2: b depend on diffusion 2 1 n-input NOR npinv capacitance C = 3 Cin = 4 in n-way multiplexer 2np g = 1 (def) g = 4/3 inv 2-input XOR, XNOR 4npinv Logical Effort David Harris Page 8 of 56 Logical Effort David Harris Page 9 of 56 Example Example Estimate the frequency of an N-stage ring oscillator: Estimate the frequency of an N-stage ring oscillator: Logical Effort: g = Logical Effort: g1≡ Electrical Effort: h = C Electrical Effort:h ==---------out 1 Parasitic Delay: p = Cin Stage Delay: d = Parasitic Delay: pp= inv ≈ 1 Oscillator Frequency: F = Stage Delay: dghp==+ 2 A 31 stage ring oscillator in a 1 1 0.18 μm process Oscillator Frequency: F ==------------------- ----------- oscillates at about 2Ndabs 4Nτ 670 MHz. Logical Effort David Harris Page 10 of 56 Logical Effort David Harris Page 46 of 56 Example Example Estimate the delay of a fanout-of-4 (FO4) inverter: Estimate the delay of a fanout-of-4 (FO4) inverter: d d Logical Effort: g = Logical Effort: g1≡ Electrical Effort: h = C Electrical Effort: h ==---------out 4 The FO4 inverter delay is a useful Parasitic Delay: Cin p = metric to characterize process performance. Stage Delay: d = Parasitic Delay: pp= inv ≈ 1 Stage Delay: dghp==+ 5 1 FO4 delay = 5τ This is about 60 ps in a 0.18 μm process. Logical Effort David Harris Page 11 of 56 Logical Effort David Harris Page 47 of 56 Outline Multi-stage Logic Networks o Introduction Logical effort extends to multi-stage networks: o Delay in a Logic Gate x o 10 y Multi-stage Logic Networks z 20 o Choosing the Best Number of Stages g = 1 g = 5/3 g = 4/3 g = 1 o Example 1 2 3 4 h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z o Asymmetric & Skewed Logic Gates o Circuit Families o Summary o Path Logical Effort: Gg= ∏ i Don’t define C Hh= o Path Electrical Effort: H = ---------------------out (path)- ∏ i Cin (path) because we don’t know hi until the o design is done Path Effort: Ff==∏ i ∏gihi Can we write FGH= ? Logical Effort David Harris Page 12 of 56 Logical Effort David Harris Page 13 of 56 Branching Effort Branching Effort No! Consider circuits that branch: No! Consider circuits that branch: 15 G = 15 G = 1 H = H = 90 / 5 = 18 90 90 5 GH = 5 GH = 18 h1 = h1 = (15+15) / 5 = 6 15 15 h2 = h2 = 90 / 15 = 6 90 F = = GH? 90 F = 36, not 18! Introduce new kind of effort to account for branching within a network: Con path + C o Branching Effort: b = ----------------------------------------------off path Con path o Path Branching Effort: Bb= ∏ i Note: hi = BH≠ H Now we can compute the path effort: ∏ in circuits that branch o Path Effort: FGBH= Logical Effort David Harris Page 14 of 56 Logical Effort David Harris Page 48 of 56 Delay in Multi-stage Networks Determining Gate Sizes We can now compute the delay of a multi-stage network: Gate sizes can be found by starting at the end of the path and working backward. o o At each gate, apply the capacitance transformation: Path Effort Delay: DF = ∑fi C • g outi i o Path Parasitic Delay: P = p Cin = ----------------------- F ∑ i i ˆf o o Check your work by verifying that the input capacitance specification is satis- Path Delay: DF ==di DF + P ∑ fied at the beginning of the path. We can prove that delay is minimized when each stage bears the same effort: ˆ 1N⁄ f ==gihi F Therefore, the minimum delay of an N-stage path is: 1N NF ⁄ + P o This is a key result of logical effort. Lowest possible path delay can be found without even calculating the sizes of each gate in the path. Logical Effort David Harris Page 15 of 56 Logical Effort David Harris Page 16 of 56 Example Example Select gate sizes y and z to minimize delay z Select gate sizes y and z to minimize delay z 9C 9C from A to B from A to B y z y z A 9C A 9C C C y y Logical Effort: G = z B 3 z B 9C Logical Effort: G43= ()⁄ 9C Electrical Effort: H = C Electrical Effort: H ==---------out 9 Branching Effort: B = Cin Path Effort: F = Branching Effort: B23==• 6 ˆ Best Stage Effort:f = Path Effort: F== GHB 128 ˆ 13⁄ Work backward for sizes: Delay: D = Best Stage Effort: f = F ≈ 5 9C43 z ==-----------------------------• ()⁄ 2.4C Work backward for sizes: 5 z = Delay: D3532==• + • 21 3z 4 3 y ==---------------------------• ()⁄ - 1.92C y = 5 Logical Effort David Harris Page 17 of 56 Logical Effort David Harris Page 49 of 56 Outline Choosing the Best Number of Stages o Introduction How many stages should a path use? o Delay in a Logic Gate o Delay is not always minimized by using as few stages as possible o Multi-stage Logic Networks o Example: How to drive 64 bit datapath with unit-sized inverter o Choosing the Best Number of Stages 1 111 o Initial driver Example 842.8 o Asymmetric & Skewed Logic Gates 16 8 o Circuit Families o Summary 22.6 Datapath load 64 64 64 64 Fastest N: 1 2 3 4 f: 64 8 4 2.8 D: 65 18 15 15.3 1N⁄ 1N⁄ DNF==+ P N64() + N assuming polarity doesn’t matter Logical Effort David Harris Page 18 of 56 Logical Effort David Harris Page 19 of 56 Derivation of the Best Number of Stages Best Number of Stages (continued) Suppose we can add inverters to the end of a path without changing its function.
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