Fundamentals of Microelectronics
CH1 Why Microelectronics? CH2 Basic Physics of Semiconductors CH3 Diode Circuits CH4 Physics of Bipolar Transistors CH5 Bipolar Amplifiers CH6 Physics of MOS Transistors CH7 CMOS Amplifiers CH8 Operational Amplifier As A Black Box CH16 Digital CMOS Circuits
1 Chapter 16 Digital CMOS Circuits
16.1 General Considerations 16.2 CMOS Inverter 16.3 CMOS NOR and NAND Gates
2 Chapter Outline
CH 16 Digital CMOS Circuits 3 Inverter Characteristic
XA
An inverter outputs a logical “1” when the input is a logical “0” and vice versa.
CH 16 Digital CMOS Circuits 4 Examples 16.1 & 16.2: NMOS Inverter
Vout=Vin-VTH
VVVVin TH: out DD 1 W VVVVVVVIRVCRVV, : ( )2 in TH out in TH out DD D D DD2 n oxL D in TH
VVVVVin TH, out in TH : 1 W VVIRVCRVVVV [2( ) 2 ] out DD D D DD2 n oxL D in TH out out 112V VVVVV ()() 2 DD out in THWWW in TH CRCRCR n oxLLL D n ox D n ox D
CH 16 Digital CMOS Circuits 5 Example 16.1 & 16.2: NMOS Inverter (cont’d)
Vout is at the lowest when Vin is at VDD.
VVRIout min DD D D max 1 W VCRVVVV [2( ) 2 ] DD2 n oxL D DD TH out min out min If we neglect the second term in the square brackets, then W [1 CVV ( )]1 V n ox DD TH VVDD L out minWW DD 1CRVVRCVV ( ) [ ( )]1 n oxLL D DD TH D n ox DD TH This is equivalent to viewing M1 as a resistor of value
1 RCWLVVon1 [ n ox ( )( DD TH )]
The CS stage resembles a voltage divider between RD and Ron1 when M1 is in deep triode region. It produces VDD when M1 is off.
CH 16 Digital CMOS Circuits 6 Transition Region Gain
Infinite Transition Region Gain Finite Transition Region Gain
Ideally, the VTC of an inverter has infinite transition region gain. However, practically the gain is finite.
CH 16 Digital CMOS Circuits 7 Example 16.3: Gain at Transition Region
Transition Region: 50 mV Supply voltage: 1.8V
1.8 V – V : Transition Region A 36 0 2 v 0.05
CH 16 Digital CMOS Circuits 8 Logical Level Degradation
Since real power buses have losses, the power supply levels at two different locations will be different. This will result in logical level degradation.
CH 16 Digital CMOS Circuits 9 Example 16.4: Logical Level Degradation
If inverter Inv1 produces a logical ONE given by the local value of VDD, determine the degradation as sensed by inverter Inv2.
V 5A 25mΩ 125mV
Supply B=1.675V Supply A=1.8V
CH 16 Digital CMOS Circuits 10 The Effects of Level Degradation and Finite Gain
In conjunction with finite transition gain, logical level degradation in succeeding gates will reduce the output swings of gates.
CH 16 Digital CMOS Circuits 11 Example 16.5: Small-Signal Gain Variation of NMOS Inverter
Sketch the small-signal voltage gain for the characteristic shown in
Fig.15.4 as a function of Vin.
Fig.15.4
the small-signal gain is the largest in the transition region.
CH 16 Digital CMOS Circuits 12 Example 16.6: Small-Signal Gain Above Unity
Prove that the magnitude of the small-signal gain obtained in Example 15.5 must exceed unity at some point.
The transition region at the input spans a range narrower than
0 to VDD.
CH 16 Digital CMOS Circuits 13 Noise Margin
Noise margin is the amount of input logic level degradation that a gate can handle before the small-signal gain becomes -1.
CH 16 Digital CMOS Circuits 14 Example 16.7: NMOS Inverter Noise Margin
W g R C( V V ) R 1 1.Using the small-signal gain : m D n ox IL TH D 1 L NM V V V W L ILW TH out CRVV( ) 1 CR 2.Using differentiation : n ox D IL TH n oxL D VLin
As Vin drives M1 into the triode region, 1 W VVCRVVVV 2 2 out DD2 n oxL D in TH out out
VVVout1 W out out nCRVVVV ox D2 out 2( in TH ) 2 out with Vout V in 1 VLVVin2 in in
1 VVin TH Vout NMVV W VVin IH H DD IH 2 CR 2 n oxL D
CH 16 Digital CMOS Circuits 15 Example 16.8: Minimum Vout
The output low level of an NMOS inverter is always degraded. Derive a relationship to guarantee that this degradation remains below 0.05VDD.
Ron1 VVVout min DD0.05 DD RRD on1 W RRCVV19 19 [ ( )]1 D on1 n oxL DD TH
CH 16 Digital CMOS Circuits 16 Example 16.9: Dynamic Behavior of NMOS Inverter
V V (0 ) DD t out W Vout( t ) V out (0 ) [ V DD V out (0 )] 1 exp , t 0 1 CRVV ( ) RCDL n oxL D DD TH
T 0 05V 0 95VVVV (0 ) [ (0 )] 1 exp 95% DD DD out DD out TRC95%DL ln RCDL VVDD out (0 )
Assuming VVVTRCDD out (0 ) DD , 95 % 3 D L
Since digital circuits operate with large signals and experience nonlinearity, the concept of transfer function is no longer meaningful. Therefore, we must resort to time-domain analysis to evaluate the speed of a gate.
CH 16 Digital CMOS Circuits 17 Rise/Fall Time and Delay
CH 16 Digital CMOS Circuits 18 Example 16.10: Time Constant
Assuming a 5% degradation in the output low level, determine the time constant at node X when VX goes from low to high.
Assuming CX WLC ox and R D 19 R on1 , 19 R C WLC D XW ox CVV() n oxL DD TH 19L2 n()VV DD TH
CH 16 Digital CMOS Circuits 19 Example 16.11: Interconnect Capacitance
What is the interconnect capacitance driven by Inv1?
Wire Capacitance per Mircon: 50 aF/µm, (1aF=1x10-18F)
Total Interconnect Capacitance: 15000x50x10-18 =750 fF
2 Equivalent to 640 MOS FETs with W=0.5µm, L=0.18µm, Cox =13.5fF/µm
CH 16 Digital CMOS Circuits 20 Power-Delay Product
TT PDP Power PHL PLH 2 2 VVDD DD (IVRCRCID DD ) ( D X ) ( D X ) with D RRRRD on11 D on 2 VDD ()()()IVRCRCD DD D X D X RRD on1 2 VCRRDD X, since typically D on1 . The power delay product of an NMOS Inverter can be loosely thought of as the amount of energy the gate uses in each switching event.
CH 16 Digital CMOS Circuits 21 Example 16.12: Power-Delay Product
Assuming TPLH is roughly equal to three time constants, determine the power-delay product for the low-to-high transitions at node X
TRCPLH 3 D X
PDP ID V DD3 R D C X
2 PDP 3 VDD WLC ox
CH 16 Digital CMOS Circuits 22 Drawbacks of NMOS Inverter
Because of constant RD, NMOS inverter consumes static power even when there is no switching.
RD presents a tradeoff between speed and power dissipation.
CH 16 Digital CMOS Circuits 23 Improved Inverter Topology
A better alternative would probably have been an “intelligent”
pullup device that turns on when M1 is off and vice versa.
CH 16 Digital CMOS Circuits 24 Improved Fall Time
This improved inverter topology decreases fall time since all of
the current from M1 is available to discharge the capacitor.
CH 16 Digital CMOS Circuits 25 CMOS Inverter
A circuit realization of this improved inverter topology is the CMOS inverter shown above. The NMOS/PMOS pair complement each other to produce the desired effects.
CH 16 Digital CMOS Circuits 26 CMOS Inverter Small-Signal Model
vout gm1 g m 2 r O 1|| r O 2 vin
When both M1 and M2 are in saturation, the small-signal gain is shown above.
CH 16 Digital CMOS Circuits 27 Voltage Transfer Curve of CMOS Inverter
Region 1: M1 is off and M 2 is on. V out =V DD .
Region 2: M12 is in saturation and M is in triode region.
Valid only when Vout V in + |V TH2 |.
1 WW 22 CVVCVVVVVVV 2 | | n ox in TH12 p ox DD in TH DD out DD out 2 LL 12
Vout V DD f1( V in ), solving the quadratic equation.
CH 16 Digital CMOS Circuits 28 Voltage Transfer Curve of CMOS Inverter
Region 3: M12 and M are in saturation. Apperas as vertical line assuming no channel-length modulation. Valid when Vin - V TH1 V out V in + |V TH2 |.
11WW 22 Solving nCVVCVVV ox in TH12 p ox DD in | TH | , 22LL 12 WW n VVV TH12 p DD || TH LL 12 Vin WW np LL 12 CH 16 Digital CMOS Circuits 29 Voltage Transfer Curve of CMOS Inverter
Region 4: Similar to Region 2. M1 is in triode region and
M2 is in saturation. Valid only when V out V in - V TH1 .
1 WW 2 2 nCVVVVCVVV ox 2 in TH12 out out p ox DD in | TH | 2 LL 12
Vout f2 ( V in ), solving the quadratic equation.
Region 5: M1 is on and M 2 is off. V out =0.
CH 16 Digital CMOS Circuits 30 Example 16.14: Switching Threshold
The switching threshold or the “trip point” of the inverter is when Vout equals Vin. Determine a relationship between (W/L)1 and (W/L)2 that sets the trip point of the CMOS inverter to VDD/2, thus providing a “symmetric” VTC
22 WW VVVVDD DD DD DD nCVCV ox TH1 11 1 p ox TH 2 2 LL 122 2 2 2
VVWDD DD 1 p Assuming 112 1 , 22 W2 n CH 16 Digital CMOS Circuits 31 Example 16.15: VTC
W2
As the PMOS device is made stronger, NMOS device requires
higher input voltage to establish ID1=ID2. Thus, the VTC is shifted to the right.
CH 16 Digital CMOS Circuits 32 Noise Margins
VIL is the low-level input voltage at which (δVout/ δVin) = -1
In Region 2,
11WW 22 CVVCVVVVVVV 2 | | n ox in TH12 p ox DD in TH DD out DD out 22LL 12
Differentiating both sides with respect to Vin , W nCVV ox in TH1 L 1
1 W VVout out pCVVVVV ox2 DD out 2 DD in | TH2 |2 VV DD out 2 L 2 VVin in V With out 1, Vin WW n VVVVVV in TH12 p 2 out in | TH | DD LL 12
CH 16 Digital CMOS Circuits 32 Noise Margins
WW Assuming a np , we must solve LL 12 a Vin V TH12 2 V out V in | V TH | V DD and
a 221 VVVVVVVVV 2 | | 22in TH12 DD in TH DD out DD out 1 Deleting V , we get A V2 B V C 0, where A= ( a 1)( a 3), out in in 8 1 1 B (a3)( V aV | V |), C [3( V | V |)222 aV ( V | V |)(4) a a V ]. 4 DD TH1 TH 28 DD TH 2 TH 1 DD TH 2 TH 1 1 B a( a 3)( V V | V |)2 B B2 4 AC DD TH12 TH V 4 IL 22AA 11 (3)(a VDD aV TH1 | V TH 2 |) a (3)( a V DD V TH 1 | V TH 2 |) 42 1 2 (aa 1)( 3) 8 (V aV |V |) 2 a ( V V | V |) DD TH1 TH 2 DD TH 1 TH 2 a 1 (aa 1) 3 CH 16 Digital CMOS Circuits 33 Noise Margins
2 a VDD V TH12 V TH V aV V V NM DD TH12 TH IL L aa13 a 1 W n 3VVDD TH 2 a a 4 V L =TH1 , where a 1 . a3 2 a a 3 a 3 2 a a a 3 W p L 2
Assuming symmetry, (a 1, VTH12 | V TH | V TH ), 31 V NM V V . IL L84 DD TH
CH 16 Digital CMOS Circuits 34 Noise Margins
VIH is the high-level input voltage at which (δVout/ δVin) = -1.
W 41a V V n DD TH 2 3aVTH1 L 1 VaIH , where 3a 1 2 a 1 3 a 3 a 1 2 3 a 1 W p L 2
WW Assuming symmetry, VVVTH12 | TH | TH and n p , LL 12 51 VVV IH84 DD TH 31 NMVVVV H DD IH84 DD TH CH 16 Digital CMOS Circuits 35 Example 16.17: Noise Margins of Ideal Inverter
If VDD = 2 VTH ,
V NMNMDD Hideal,, Lideal 2
CH 16 Digital CMOS Circuits 37 Example 16.18: Floating Output
If VDD < VTH1 + VTH2 = 2 VTH ,
VVTH1 DD /2
VVTH2 DD /2
When Vin=VDD/2, M1 and M2 will both be off and the output floats.
CH 16 Digital CMOS Circuits 38 Charging Dynamics of CMOS Inverter
As Vout is initially charged high, the charging is linear since M2 is in saturation. However, as M2 enters the triode region the charge rate becomes sublinear.
CH 16 Digital CMOS Circuits 39 Example 16.19: Charging Current
The current of M2 is initially constant as M2 is in saturation. However as M2 enters the triode region, its current decreases.
CH 16 Digital CMOS Circuits 40 Example 16.20: Variation of Output Waveform
As the PMOS size is increased, the output exhibits a faster transition.
CH 16 Digital CMOS Circuits 41 Discharging Dynamics of CMOS Inverter
VDD- VTH1
Similar to the charging dynamics, the discharge is linear when
M1 is in saturation and becomes sublinear as M1 enters the triode region.
CH 16 Digital CMOS Circuits 42 Rise Delay
Initially, M2 is in saturation, W 2 ||ICVVD22 p ox DD TH L 2
||ID2 Vout( t ) t ,only up to V out | V TH 2 |. CL
2 |VCTHL2 | Thus, TPLH1 W 2 pCVV ox DD TH 2 L 2
CH 16 Digital CMOS Circuits 43 Rise Delay
Thereafter M 2 operates in the triode region, dV ||IC out DL2 dt 1 W 2 dV CVVVVVVC2 out p ox DD TH2 DD out DD out L 2 L2 dt
dVout1 C ox W p dt 2 2 CL 2VVVVVVDD TH2 DD out DD out L 2
Integrating from VVVout TH2 to DD / 2,
CL VVTH22 TH TRCPLH22ln 3 4 on L ln 3 4 W VVDD DD pCVV ox DD TH 2 L 2 Thus,
TTTPLH PLH12 PLH
2 VVTH22 TH RCon2 L ln 3 4 VVVDD TH2 DD
CH 16 Digital CMOS Circuits 44 Fall Delay
Similarly,
CVL2 VTH1 TH1 TPHL ln 3 4 W VVVDD TH1 DD nCVV ox DD TH1 L 1
2 VTH1 VTH1 RCon1 L ln 3 4 VVVDD TH1 DD Fall Time Delay
CH 16 Digital CMOS Circuits 45 Example 16.22: Delay vs. Threshold Voltage
Compare the two terms inside the square brackets as VTH1 varies from zero to VDD/2
CL 2 VTH 2/1 VTH 2/1 TPLH/ HL ln 3 4 W VVVDD TH2/1 DD p/ nCVV ox DD TH 2/1 L 2/1
The sum of the 1st and 2nd terms of the bracket is the smallest
when VTH is the smallest, hence low VTH improves speed. CH 16 Digital CMOS Circuits 46 Example 16.23: Effect of Series Transistor
M1’ appears in series with M1 and is identical to M1. Explain what happens to the output fall time.
RRRon on1 on 1' 11 WW CVVCV()()(()) V TH1 n oxLL11 DD TH n ox1 DD
2Ron1 Since pull-down resistance is doubled, the fall time is also doubled.
CH 16 Digital CMOS Circuits 47 Power Dissipation of the CMOS Inverter
Energy stored in CL 1 ECV 2 1 2 L DD
Energy consumed by M2 dV E( V V )( Cout ) dt 2 t0 DD out L dt VV Cout DD () V V dV LV 0 DD out out out 1 CV2 2 L DD Thus, total energy consumed in one cycle is
EEEtot 12 2 CVL DD
48 CH 16 Digital CMOS Circuits Power Dissipation of the CMOS Inverter
1 P C V2 f Dissipation_ PMOS2 L DD in
2 Psupply C L V DD f in 1 P C V2 f Dissipation_ NMOS2 L DD in
CH 16 Digital CMOS Circuits Example 16.24: Energy Calculation
Compute the energy drawn from the supply as Vout =0 →VDD.
1 ECV 2 stored2 L DD 1 ECV 2 dissipated2 L DD 2 ECVdrawn L DD
CH 16 Digital CMOS Circuits 50 Power Delay Product
CL 2 VTH 2/1 VTH 2/1 TPLH/ HL ln 3 4 W VVVDD TH2/1 DD p/ nCVV ox DD TH 2/1 L 2/1
Assuming TTRRPHL PLH , on12 on
222 VTH1 VTH1 PDP Ron1 C L V DD ln 3 4 VVVDD TH1 DD
CH 16 Digital CMOS Circuits 51 Example 16.25: PDP
Consider a cascade of two identical inverters, where the PMOS device is three times as wide as the NMOS transistor to provide a symmetric VTC. For simplicity, assume the capacitance at node X is equal to 4WLCOX. Also, VTHN=|VTHP| ≈ VDD/4. Compute the PDP.
1 R on W CVV( )( ) n oxL DD TH 41 3 W nCV ox DD L
7.25WL22 C f V PDP ox in DD n
CH 16 Digital CMOS Circuits 52 Crowbar Current
When Vin is between VTH1 and VDD-|VTH2|, both M1 and M2 are on and there will be a current flowing from supply to ground.
CH 16 Digital CMOS Circuits 53 NMOS Section of NOR
When either A or B is high or if both A and B are high, the output will be low. Transistors operate as pull-down devices.
CH 16 Digital CMOS Circuits 54 Example 16.26: Poor NOR
The above circuit fails to act as a NOR because when A is high
and B is low, both M4 and M1 are on and produces an ill-defined low.
CH 16 Digital CMOS Circuits 55 PMOS Section of NOR
When both A and B are low, the output is high. Transistors operate as pull-up devices.
CH 16 Digital CMOS Circuits 56 CMOS NOR
Combing the NMOS and PMOS NOR sections, we have the CMOS NOR.
CH 16 Digital CMOS Circuits 57 Example 16.27 & 16.28: Three-Input NOR
Select the relative widths of the transistors in the 3-input NOR gate for equal rise and fall times. Assume np 2 and equal channel lengths.
For equal rise & fall time,
make the M5-M7 equivalent to one device with a width of W.
W1=W2=W3=W W4=W5=W6=6W
VABCout
CH 16 Digital CMOS Circuits Drawback of CMOS NOR
Due to low PMOS mobility, series combination of M3 and M4 suffers from a high resistance, producing a long delay. The widths of the PMOS transistors can be increased to counter the high resistance, however this would load the preceding stage and the overall delay of the system may not improve.
CH 16 Digital CMOS Circuits 59 NMOS NAND Section
When both A and B are high, the output is low.
CH 16 Digital CMOS Circuits 60 PMOS NAND Section
When either A or B is low or if both A and B are low, the output is high.
CH 16 Digital CMOS Circuits 61 CMOS NAND
Just like the CMOS NOR, the CMOS NAND can be implemented by combining its respective NMOS and PMOS sections, however it has better performance because its PMOS transistors are not in series. CH 16 Digital CMOS Circuits 62 Example 16.29: Three-Input NAND
Select the relative widths of the transistors in the 3-input NAND gate for equal rise and fall times. Assume np 2 and equal channel lengths.
For equal rise & fall time,
make the M1-M3 equivalent to one device with a width of W.
W1=W2=W3=3W W4=W5=W6=2W
Vout ABC
CH 16 Digital CMOS Circuits 63 Example 16.30: NMOS and PMOS Duality
C is in “series” with the “parallel” combination of A and B
C is in “parallel” with the “series” combination of A and B
In the CMOS philosophy, the PMOS section can be obtained from the NMOS section by converting series combinations to the parallel combinations and vice versa.
CH 16 Digital CMOS Circuits 64