Fundamentals of Microelectronics CH1 Why Microelectronics? CH2 Basic Physics of Semiconductors CH3 Diode Circuits CH4 Physics of Bipolar Transistors CH5 Bipolar Amplifiers CH6 Physics of MOS Transistors CH7 CMOS Amplifiers CH8 Operational Amplifier As A Black Box CH16 Digital CMOS Circuits 1 Chapter 16 Digital CMOS Circuits 16.1 General Considerations 16.2 CMOS Inverter 16.3 CMOS NOR and NAND Gates 2 Chapter Outline CH 16 Digital CMOS Circuits 3 Inverter Characteristic XA An inverter outputs a logical “1” when the input is a logical “0” and vice versa. CH 16 Digital CMOS Circuits 4 Examples 16.1 & 16.2: NMOS Inverter Vout=Vin-VTH VVVVin TH: out DD 1 W VVVVVVVIRVCRVV, : ( )2 in TH out in TH out DD D D DD2 n oxL D in TH VVVVVin TH, out in TH : 1 W VVIRVCRVVVV [2( ) 2 ] out DD D D DD2 n oxL D in TH out out 112V VVVVV ()() 2 DD out in THWWW in TH CRCRCR n oxLLL D n ox D n ox D CH 16 Digital CMOS Circuits 5 Example 16.1 & 16.2: NMOS Inverter (cont’d) Vout is at the lowest when Vin is at VDD. VVRIout min DD D D max 1 W VCRVVVV [2( ) 2 ] DD2 n oxL D DD TH out min out min If we neglect the second term in the square brackets, then W [1 CVV ( )]1 V n ox DD TH VVDD L out minWW DD 1CRVVRCVV ( ) [ ( )]1 n oxLL D DD TH D n ox DD TH This is equivalent to viewing M1 as a resistor of value 1 RCWLVVon1 [ n ox ( )( DD TH )] The CS stage resembles a voltage divider between RD and Ron1 when M1 is in deep triode region. It produces VDD when M1 is off. CH 16 Digital CMOS Circuits 6 Transition Region Gain Infinite Transition Region Gain Finite Transition Region Gain Ideally, the VTC of an inverter has infinite transition region gain. However, practically the gain is finite. CH 16 Digital CMOS Circuits 7 Example 16.3: Gain at Transition Region Transition Region: 50 mV Supply voltage: 1.8V 1.8 V – V : Transition Region A 36 0 2 v 0.05 CH 16 Digital CMOS Circuits 8 Logical Level Degradation Since real power buses have losses, the power supply levels at two different locations will be different. This will result in logical level degradation. CH 16 Digital CMOS Circuits 9 Example 16.4: Logical Level Degradation If inverter Inv1 produces a logical ONE given by the local value of VDD, determine the degradation as sensed by inverter Inv2. V 5A 25mΩ 125mV Supply B=1.675V Supply A=1.8V CH 16 Digital CMOS Circuits 10 The Effects of Level Degradation and Finite Gain In conjunction with finite transition gain, logical level degradation in succeeding gates will reduce the output swings of gates. CH 16 Digital CMOS Circuits 11 Example 16.5: Small-Signal Gain Variation of NMOS Inverter Sketch the small-signal voltage gain for the characteristic shown in Fig.15.4 as a function of Vin. Fig.15.4 the small-signal gain is the largest in the transition region. CH 16 Digital CMOS Circuits 12 Example 16.6: Small-Signal Gain Above Unity Prove that the magnitude of the small-signal gain obtained in Example 15.5 must exceed unity at some point. The transition region at the input spans a range narrower than 0 to VDD. CH 16 Digital CMOS Circuits 13 Noise Margin Noise margin is the amount of input logic level degradation that a gate can handle before the small-signal gain becomes -1. CH 16 Digital CMOS Circuits 14 Example 16.7: NMOS Inverter Noise Margin W g R C( V V ) R 1 1.Using the small-signal gain : m D n ox IL TH D 1 L NM V V V W L ILW TH out CRVV( ) 1 CR 2.Using differentiation : n ox D IL TH n oxL D VLin As Vin drives M1 into the triode region, 1 W VVCRVVVV 2 2 out DD2 n oxL D in TH out out VVVout1 W out out nCRVVVV ox D2 out 2( in TH ) 2 out with Vout V in 1 VLVVin2 in in 1 VVin TH Vout NM V V W VVin IH H DD IH 2 CR 2 n oxL D CH 16 Digital CMOS Circuits 15 Example 16.8: Minimum Vout The output low level of an NMOS inverter is always degraded. Derive a relationship to guarantee that this degradation remains below 0.05VDD. Ron1 VVVout min DD0.05 DD RRD on1 W RRCVV19 19 [ ( )]1 D on1 n oxL DD TH CH 16 Digital CMOS Circuits 16 Example 16.9: Dynamic Behavior of NMOS Inverter V V (0 ) DD t out W Vout( t ) V out (0 ) [ V DD V out (0 )] 1 exp , t 0 1 CRVV ( ) RCDL n oxL D DD TH T 0 05V 0 95VVVV (0 ) [ (0 )] 1 exp 95% DD DD out DD out TRC95%DL ln RCDL VVDD out (0 ) Assuming VVVTRCDD out(0 ) DD , 95 % 3 D L Since digital circuits operate with large signals and experience nonlinearity, the concept of transfer function is no longer meaningful. Therefore, we must resort to time-domain analysis to evaluate the speed of a gate. CH 16 Digital CMOS Circuits 17 Rise/Fall Time and Delay CH 16 Digital CMOS Circuits 18 Example 16.10: Time Constant Assuming a 5% degradation in the output low level, determine the time constant at node X when VX goes from low to high. Assuming CX WLC ox and R D19 R on1 , 19 R C WLC D XW ox CVV() n oxL DD TH 19L2 n()VV DD TH CH 16 Digital CMOS Circuits 19 Example 16.11: Interconnect Capacitance What is the interconnect capacitance driven by Inv1? Wire Capacitance per Mircon: 50 aF/µm, (1aF=1x10-18F) Total Interconnect Capacitance: 15000x50x10-18 =750 fF 2 Equivalent to 640 MOS FETs with W=0.5µm, L=0.18µm, Cox =13.5fF/µm CH 16 Digital CMOS Circuits 20 Power-Delay Product TT PDP Power PHL PLH 2 2 VVDD DD (IVRCRCID DD ) ( D X ) ( D X ) with D RRRRD on11 D on 2 VDD ()()()IVRCRCD DD D X D X RRD on1 2 VCRRDD X, since typically D on1. The power delay product of an NMOS Inverter can be loosely thought of as the amount of energy the gate uses in each switching event. CH 16 Digital CMOS Circuits 21 Example 16.12: Power-Delay Product Assuming TPLH is roughly equal to three time constants, determine the power-delay product for the low-to-high transitions at node X TRCPLH 3 D X PDP ID V DD3 R D C X 2 PDP 3 VDD WLC ox CH 16 Digital CMOS Circuits 22 Drawbacks of NMOS Inverter Because of constant RD, NMOS inverter consumes static power even when there is no switching. RD presents a tradeoff between speed and power dissipation. CH 16 Digital CMOS Circuits 23 Improved Inverter Topology A better alternative would probably have been an “intelligent” pullup device that turns on when M1 is off and vice versa. CH 16 Digital CMOS Circuits 24 Improved Fall Time This improved inverter topology decreases fall time since all of the current from M1 is available to discharge the capacitor. CH 16 Digital CMOS Circuits 25 CMOS Inverter A circuit realization of this improved inverter topology is the CMOS inverter shown above. The NMOS/PMOS pair complement each other to produce the desired effects. CH 16 Digital CMOS Circuits 26 CMOS Inverter Small-Signal Model vout gm1 g m 2 r O 1|| r O 2 vin When both M1 and M2 are in saturation, the small-signal gain is shown above. CH 16 Digital CMOS Circuits 27 Voltage Transfer Curve of CMOS Inverter Region 1: M1 is off and M 2 is on. V out =V DD . Region 2: M12 is in saturation and M is in triode region. Valid only when Vout V in + |V TH2 |. 1 WW 22 CVVCVVVVVVV 2 | | n ox in TH12 p ox DD in TH DD out DD out 2 LL 12 Vout V DD f1( V in ), solving the quadratic equation. CH 16 Digital CMOS Circuits 28 Voltage Transfer Curve of CMOS Inverter Region 3: M12 and M are in saturation. Apperas as vertical line assuming no channel-length modulation. Valid when Vin - V TH1 V out V in + |V TH2 |. 11WW 22 Solving nCVVCVVV ox in TH12 p ox DD in | TH | , 22LL 12 WW n VVV TH12 p DD || TH LL 12 Vin WW np LL 12 CH 16 Digital CMOS Circuits 29 Voltage Transfer Curve of CMOS Inverter Region 4: Similar to Region 2. M1 is in triode region and M2 is in saturation. Valid only when V out V in - V TH1 . 1 WW 2 2 nCVVVVCVVV ox 2 in TH12 out out p ox DD in | TH | 2 LL 12 Vout f2 ( V in ), solving the quadratic equation. Region 5: M1 is on and M 2 is off. V out =0. CH 16 Digital CMOS Circuits 30 Example 16.14: Switching Threshold The switching threshold or the “trip point” of the inverter is when Vout equals Vin. Determine a relationship between (W/L)1 and (W/L)2 that sets the trip point of the CMOS inverter to VDD/2, thus providing a “symmetric” VTC 22 WW VVVVDD DD DD DD nCVCV ox TH1 11 1 p ox TH 2 2 LL 122 2 2 2 VVWDD DD 1 p Assuming 112 1 , 22 W2 n CH 16 Digital CMOS Circuits 31 Example 16.15: VTC W2 As the PMOS device is made stronger, NMOS device requires higher input voltage to establish ID1=ID2.