Data Sheet Rev. B

10 GHz to 21.7 GHz, Tunable

Band-Pass Filter Data Sheet ADMV8420

FEATURES FUNCTIONAL BLOCK DIAGRAM

NIC NIC NIC NIC NIC

Amplitude settling time: 200 ns NIC

21 22

23 20 Wideband rejection: ≥20 dB 19 Single-chip implementation NIC 1 18 NIC 24-lead, 4 mm × 4 mm, RoHS-compliant LFCSP ADMV8420 GND 2 17 GND APPLICATIONS RFIN 3 16 RFOUT Test and measurement equipment GND 4 15 GND Military radar and electronic warfare systems NIC 5 14 NIC Very small aperture terminal (VSAT) communications NIC 6 13 NIC

8 9

11 PACKAGE 12

10 BASE

NIC

NIC NIC NIC NIC

FCTL GND V

NIC = NOT INTERNALLY CONNECTED. 17199-001 Figure 1. GENERAL DESCRIPTION The ADMV8420 is a monolithic microwave integrated circuit voltage between 0 V to 15 V. The usable pass band corner (MMIC), tunable band-pass filter that features a user-selectable frequencies (fCORNER) span from 10 GHz to 21.7 GHz. This tunable pass band frequency. The 3 dB filter bandwidth is approximately filter is a smaller alternative to switched filter banks and cavity 20%, and the 20 dB filter bandwidth is approximately 40%. tuned filters. The ADMV8420 has minimal microphonics due Additionally, the center frequency (fCENTER) varies between to the monolithic design and provides a dynamically adjustable 11.1 GHz to 19.6 GHz by applying a center frequency control solution in advanced communications applications.

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2019–2020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADMV8420 Data Sheet

TABLE OF CONTENTS Features ...... 1 Interface Schematics ...... 5 Applications ...... 1 Typical Performance Characteristics ...... 6 Functional Block Diagram ...... 1 Theory of Operation ...... 10 General Description ...... 1 Applications Information ...... 11 Revision History ...... 2 Typical Application Circuit ...... 11 Specifications ...... 3 Evaluation Printed Circuit Board (PCB) ...... 12 Absolute Maximum Ratings ...... 4 Outline Dimensions ...... 14 ESD Caution...... 4 Ordering Guide ...... 14 Pin Configuration and Function Descriptions ...... 5

REVISION HISTORY 10/2020—Rev. A to Rev. B Changes to Figure 16 ...... 7 Changes to Product Title and General Description Section ...... 1 Changes to Figure 25 ...... 9 Changes to Table 1 ...... 3 Changes to Typical Application Circuit Section and Figure 26 ..... 11 Changes to Theory of Operation Section ...... 10 Changes to Figure 28 ...... 12 Added Figure 29; Renumbered Sequentially ...... 13 8/2019—Rev. 0 to Rev. A Moved Table 4 ...... 13 Changes to Figure 1 ...... 1 Change to Ordering Guide ...... 14 Changes to Table 1 ...... 3 Changes to Figure 2 and Table 3 ...... 5 6/2019—Revision 0: Initial Version Changes to Figure 7, Figure 8, and Figure 9 ...... 6

Rev. B | Page 2 of 14 Data Sheet ADMV8420

SPECIFICATIONS

TA = 25°C and center frequency control voltage (VFCTL) is swept from 0 V to 15 V.

Table 1. Parameter Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE

fCENTER 11.1 19.6 GHz

3 dB fCORNER 10 21.7 GHz BANDWIDTH 3 dB 20 % REJECTION

Low-Side 0.8 × fCENTER GHz ≥20 dB

High-Side 1.2 × fCENTER GHz ≥20 dB

Reentry 2.3 × fCENTER GHz ≤30 dB LOSS Insertion Loss 5 dB Return Loss 8.5 dB DYNAMIC PERFORMANCE

Input Power at 5° Shift in Insertion Phase (VFCTL = 0 V) 10 dBm Input Third-Order Intercept (IP3) 31 dBm Group Delay 0.5 ns

Phase Sensitivity 1.3 Rad/V At VFCTL = 7 V Amplitude Settling 200 ns Time to settle to minimum insertion loss, within ≤0.5 dB of static insertion loss Drift Rate −1.1 MHz/°C RESIDUAL PHASE NOISE 1 MHz Offset −161 dBc/Hz TUNING

VFCTL 0 15 V

Center Frequency Control Current (IFCTL) ±1 mA

Rev. B | Page 3 of 14 ADMV8420 Data Sheet

ABSOLUTE MAXIMUM RATINGS Table 2. ESD CAUTION Parameter Rating Tuning

VFCTL −0.5 V to +15 V IFCTL ±1 mA RF Input Power 27 dBm Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +150°C Junction Temperature for 1 Million Mean 150°C Time to Failure (MTTF) Nominal Junction Temperature 108°C (Temperature at Ground Pad = 85°C, Input Power (PIN) = 27 dBm) Electrostatic Discharge (ESD) Rating Human Body Model (HBM) 1000 V Field Induced Charge Device Model 1250 V (FICDM) Moisture Sensitivity Level (MSL) Rating MSL3 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Rev. B | Page 4 of 14 Data Sheet ADMV8420

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NIC

20 19

NIC 1 18 NIC GND 2 17 GND RFIN 3 ADMV8420 16 RFOUT GND 4 TOP VIEW 15 GND (Not to Scale) NIC 5 14 NIC

NIC 6 13 NIC

NIC

NIC NIC

FCTL V

NOTES 1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA SHOWN HEREIN WAS MEASURED WITH THESE CONNECTED TO RF AND DC GROUND. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND. 17199-002 Figure 2. Pin Configuration

Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 5 to 8, 10 to 14, and 18 to 24 NIC Not Internally Connected. These pins are not connected internally. All data shown is measured with these pins connected to the RF and dc ground. 2, 4, 15, and 17 GND Ground. These pins must be connected to the radio frequency (RF) and dc ground. 3 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. Do not apply an external voltage to this pin.

9 VFCTL Center Frequency Control Voltage. This pin controls the fCENTER of the device. 16 RFOUT RF Output. This pin is dc-coupled and matched to 50 Ω. Do not apply an external voltage to this pin. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.

INTERFACE SCHEMATICS

4Ω 0.4nH 100Ω RFIN VFCTL

20pF 27pF 17199-005

17199-003 Figure 3. VFCTL Interface Schematic Figure 5. RFIN Interface Schematic

GND RFOUT

17199-006

17199-004 Figure 4. GND Interface Schematic Figure 6. RFOUT Interface Schematic

Rev. B | Page 5 of 14 ADMV8420 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS 0 0 0V 7V –10 15V –5

–20 –10

–30 –15

–40 –20

–50 –25 INSERTION LOSS (dB) LOSS INSERTION –60 –30 S11, 0V S22, 0V BROADBAND RETURN LOSS (dB) S11, 7V –70 –35 S22, 7V S11, 15V S22, 15V

–80 –40 10 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 1 17199- RF FREQUENCY (GHz) 17199-107 RF FREQUENCY (GHz) Figure 7. Broadband Insertion Loss vs. RF Frequency at Various Voltages Figure 10. Broadband Return Loss vs. RF Frequency at Various Sxx and Voltages

0 0 0V 7V 15V –5 –5 –10 –10 –15

–15 –20

–25

–20 RETURN LOSS (dB) INSERTION LOSS (dB) LOSS INSERTION –30 S11, 0V S22, 0V –25 S11, 7V –35 S22, 7V S11, 15V S22, 15V

–30 –40 1 5 10 15 20 25 30 7 9 11 13 15 17 19 21 23 25 27 11

RF FREQUENCY (GHz) 17199- RF FREQUENCY (GHz) 17199-108 Figure 8. Insertion Loss vs. RF Frequency at Various Voltages Figure 11. Return Loss vs. RF Frequency at Various Sxx and Voltages

0 0 –40°C +25°C –2 +85°C –5 –4

–6 –10 –8

–15 –10

–12 –20 RETURN LOSS (dB)

INSERTION LOSS (dB) LOSS INSERTION –14 S11, –40°C –16 S22, –40°C –25 S11, +25°C S22, +25°C –18 S11, +85°C S22, +85°C –30 –20 12 5 10 15 20 25 30 10 12 14 16 18 20 22 24 26 28 30 1 17199- RF FREQUENCY (GHz) 17199-109 RF FREQUENCY (GHz) Figure 9. Minimum Insertion Loss vs. RF Frequency at Various Temperatures, Figure 12. Return Loss vs. RF Frequency at Various Temperatures, VFCTL = 7 V VFCTL = 7 V

Rev. B | Page 6 of 14 Data Sheet ADMV8420

25 0 –40°C –40°C +25°C +25°C +85°C +85°C –2 20

–4 15 (GHz) –6

CENTER 10 f –8 INSERTION LOSS (dB) LOSS INSERTION

5 –10

0 –12 16 13 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

V (V) 17199-

17199- V (V) FCTL FCTL

Figure 13. fCENTER vs. VFCTL at Various Temperatures Figure 16. Minimum Insertion Loss vs. VFCTL at Various Temperatures

30 0 –40°C –40°C +25°C +25°C +85°C +85°C 25 –3

20 –6

–9 10 3dB BANDWIDTH (%)

MAXIMUM RETURN LOSS (dB) RETURN MAXIMUM –12 5

0 17 14 –15 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 V (V) 17199- FCTL 17199- VFCTL (V)

Figure 14. 3 dB Bandwidth vs. VFCTL at Various Temperatures Figure 17. Maximum Return Loss in a 2 dB Bandwidth vs. VFCTL at Various Temperatures

1.00 1.40 –40°C –40°C +25°C +25°C +85°C 1.35 +85°C 0.95 TIO TIO 1.30 A A 0.90 1.25

0.85 1.20

1.15 0.80 -SIDE REJECTION R W 1.10 LO HIGH-SIDE REJECTION R 0.75 1.05

0.70

15 1.00 18 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 V (V) FCTL 17199- V (V) FCTL 17199-

Figure 15. Low-Side Rejection Ratio vs. VFCTL at Various Temperatures Figure 18. High-Side Rejection Ratio vs. VFCTL at Various Temperatures

Rev. B | Page 7 of 14 ADMV8420 Data Sheet

1200 0.8 –40°C 0V +25°C 7V +85°C 15V 1000 0.7

800 0.6 (MHz/V) (ns) Y Y A

600 0.5 DEL P

400 GROU 0.4 TUNING SENSITIVIT TUNING 200 0.3

0 0.2 19 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

V (V) RF FREQUENCY (GHz) 17199-122 FCTL 17199-

Figure 19. Tuning Sensitivity vs. VFCTL at Various Temperatures Figure 22. Group Delay vs. RF Frequency at Various Voltages

1.0 40 –40°C +25°C +85°C 35 0.8 30

(ns) 25

Y 0.6 A 20 DEL P 0.4 15 INPUT IP3 (dBm) GROU 10 0.2 5 –40°C +25°C +85°C 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 V (V) V (V) 17199-120 FCTL FCTL 17199-123

Figure 20. Group Delay vs. VFCTL at Various Temperatures Figure 23. Input IP3 vs. VFCTL at Various Temperatures, PIN = 20 dBm

–100 0V 7V –110 15V

–120

–130

–140

PHASE NOISE (dBc/Hz) PHASE –150 L

–160 RESIDUA –170

–180 10 100 1k 10k 100k 1M 10M 100M

OFFSET FREQUENCY (Hz) 17199-121 Figure 21. Residual Phase Noise vs. Offset Frequency at Various VFCTL Voltages

Rev. B | Page 8 of 14 Data Sheet ADMV8420

22 5.5 VFCTL = 0V VFCTL = 1V 20 5.0 VFCTL = 3V APPROXIMATE V = 7V FCTL 18 fCENTER 4.5 VFCTL = 10V VFCTL = 15V 16 4.0 (GHz) 14 3.5 CENTER

f 12 3.0 TE 2.5 PHI (RAD/V) A 10 A

8 2.0 LT DE

PHASE SHIFT (Degrees) DELTA PHI 6 1.5 APPROXIM 4 1.0

2 0.5

0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17199-124 INPUT POWER (dBm) VFCTL 17199-125

Figure 24. Phase Shift vs. Input Power Figure 25. Phase Sensitivity vs. VFCTL Voltages

Rev. B | Page 9 of 14 ADMV8420 Data Sheet

THEORY OF OPERATION The ADMV8420 is a MMIC band-pass filter that features a user-selectable pass band frequency. Varying the applied analog tuning voltage between 0 V and 15 V at VFCTL varies the fCENTER between 11.1 GHz and 19.6 GHz.

Rev. B | Page 10 of 14 Data Sheet ADMV8420

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

20 19 Figure 26 shows the typical application circuit for the ADMV8420. 1 18 ADMV8420 The RFIN and RFOUT pins are dc-coupled and external voltage C1 2 17 C2 100pF 100pF must not be applied. It is recommended to install 100 pF series RFIN 3 16 RFOUT capacitors (C1 and C2) on the RF traces to prevent any prestage 4 15 or poststage interaction with the filter. 5 14

On the VFCTL control port, the C3 decoupling capacitor is 6 13

9 12 shown with 100 pF as the typical value. However, the selection 10 C3 PACKAGE of the C3 capacitor is determined based on the system design 100pF BASE criteria for phase noise and tuning speed. That is, there is a GND

VFCTL baseband noise characteristic for a particular control voltage, 17199-026 which can translate into additive phase noise within the filter. Figure 26. Typical Application Circuit Minimizing baseband noise on the control voltage can be done by capacitive means at the expense of voltage rise time, which impacts the tuning speed of the filter. Carefully consider the control voltage baseband noise and rise time performance to ensure that system performance metrics are met.

Rev. B | Page 11 of 14 ADMV8420 Data Sheet

EVALUATION PRINTED CIRCUIT BOARD (PCB) The circuit board in this application uses RF circuit design techniques. Signal lines must have 50 Ω impedance. The package All RF traces are routed on Layer 1 (primary side). The remaining ground leads and exposed pad must connect directly to the ground three layers are ground planes that provide a solid ground for RF plane (see Figure 27). A sufficient number of via holes connect the transmission lines, as shown in Figure 27. The top dielectric top and bottom ground planes. The evaluation circuit board material is Rogers 4350, which offers low loss performance. The shown in Figure 28 is available from Analog Devices, Inc. upon prepreg material in Layer 2 attaches the Isola 370HR core layer to request. copper traces layers. Both the prepreg material and the Isola 370HR core layer achieve the required board finish thickness. PRIMARY SILKSCREEN

PRIMARY SOLDER MASK

0.5oz Cu PRIMARY SIDE (LAYER 1) NOMINAL ARLON OR ROGERS CORE 10MILS ±1MIL (CRITICAL) FINISHED BOARD 0.5oz Cu L2_GND PLANE (LAYER 2) THICKNESS 0.062" PREPREG AS REQUIRED ±10% 0.5oz Cu L3_GND PLANE (LAYER 3) 370HR 0.5oz Cu SECONDARY SIDE (LAYER 4) 17199-028 Figure 27. The Cross Sectional View of the ADMV8420-EVALZ PCB Layers

17199-126 Figure 28. Evaluation PCB Layout, Top View

Rev. B | Page 12 of 14 Data Sheet ADMV8420

PAD 24 23

20 19

21 22

NIC NIC

NIC NIC PAD

1 18 NIC NIC 2 ADMV8420 17 J1 GND GND J2 1 3 16 1 RFIN U1 RFOUT 4 15 GND GND 2 3 4 1492-04A-5 5 14 1492-04A-5 4 3 2 NIC NIC 6 13 NIC NIC

AGND AGND

FCTL

NIC NIC NIC

V NIC NIC

7 8

11 10 12

AGND DNI DNI J8 J5 1492-04A-5 WHT WHT DNI DNI DNI DNI DNI DNI P P + C1 C3 C4 C6 C7 + C9 N 4.7µF 1000pF 100pF 100pF 1000pF N 4.7µF

AGND AGND AGND AGND AGND AGND

J7 WHT

P + C8 C5 C2 N 4.7µF 1000pF 100pF

AGND AGND AGND 17199-127 Figure 29. ADMV8420-EVALZ Evaluation Board Schematic

Table 4. Bill of Materials for the ADMV8420-EVALZ Reference Designator Description J1 and J2 PCB mount, southwest 2.4 mm connector J7 and GND Test points C2 Capacitor, 100 pF, 0402 C5 Capacitor, 1000 pF, 0603 C8 Capacitor, 4.7 µF, 3216 U1 ADMV8420 PCB1 08-0512982 evaluation PCB

1 Circuit board material is Arlon 25FR or Rogers 25FR. Rogers 4350 is the laminate on top of Arlon 25FR or Rogers 25FR. 2 The raw, bare PCB identifier is 08-051298.

Rev. B | Page 13 of 14 ADMV8420 Data Sheet

OUTLINE DIMENSIONS

DETAIL A (JEDEC 95) 4.10 0.30 4.00 SQ PIN 1 0.25 INDICATOR 3.90 0.18 AREA PIN 1 IN D IC ATO R AR E A OP TIO N S 19 24 (SEE DETAIL A) 18 1

0.50 BSC 2.70 EXPOSED PAD 2.60 SQ 2.50

13 6 0.50 12 7 TOP VIEW BOTTOM VIEW 0.20 MIN 0.40 0.30 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW THE EXPOSED PAD, REFER TO 0.05 MAX 0.70 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF 09-07-2018-A PKG-004273/5069 COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8 Figure 30. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-15) Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADMV8420ACPZ −40°C to +85°C 24-Lead LFCSP CP-24-15 ADMV8420ACPZ-R5 −40°C to +85°C 24-Lead LFCSP, 7” Tape and Reel CP-24-15 ADMV8420-EVALZ Evaluation Board

1 All models are RoHS-compliant parts.

Rev. B | Page 14 of 14