Digital Low-Level Radio Frequency Control and Microphonics Mitigation of Superconducting Cavities
By
Nathanael Robert Usher
A THESIS
Submitted to Michigan State University in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE
Department of Electrical and Computer Engineering
2007 ABSTRACT
Digital Low-Level Radio Frequency Control and Microphonics Mitigation of Superconducting Cavities
By
Nathanael Robert Usher
Superconducting Radio Frequency (SRF) cavities designed for proposed linear reaccel- erators at the National Superconducting Cyclotron Laboratory (NSCL) have an unloaded quality factor (Q) on the order of 109. The high Q results in a very narrow bandwidth, so small perturbations in the cavity’s resonant frequency result in large changes in the mag- nitude and phase of its electric field for a fixed frequency driving signal. As a result, it is necessary to use a controller that can compensate for perturbations as they occur.
This project develops a new digital low-level radio frequency (LLRF) controller for this application, including DSP-based hardware, software algorithms, and a graphical user interface. The digital LLRF controller provides two types of control over cavity pertur- bations. The LLRF implements a PID control on the cavity driving signal to compensate for nonlinearities and small random disturbances. Significant cavity detuning caused by narrow-band vibrations, referred to as “microphonics,” are reduced by the LLRF controller using a piezoelectric tuner controlled by an adaptive feedforward cancellation algorithm.
The completed prototype is a small, standalone, economically viable, ethernet con- nected controller. Through a MATLAB interface, it will allow advanced algorithm devel- opment by control engineers who are not necessarily familiar with the low-level workings of the controller. ACKNOWLEDGMENTS
I would like to thank my advisor Dr. Xiaobo Tan and Dr. John Vincent of the National
Superconducting Cyclotron Laboratory (NSCL) for giving me the opportunity to work on this project. I would also like to thank everyone in the electronics department at the NSCL for their help. Without help from Mark Davis and John Priller, I would not have been able to develop the network interface and graphical front-end. Adam Molzahn laid the groundwork for this project with his digital phase meter and introduced me to the fundamentals of how the system works. Without Adam’s work to build upon and the help and guidance of the
NSCL staff, I would not have been able to complete this project.
iii TABLE OF CONTENTS
ABSTRACT ...... ii
ACKNOWLEDGMENTS ...... iii
LIST OF TABLES ...... vi
LIST OF FIGURES ...... vii
1 Introduction ...... 1
2 Signal Digitization and Interlocks ...... 9 2.1 Collecting Input Samples ...... 9 2.2 CORDIC Algorithm ...... 12 2.3 DSP Interface ...... 15 2.4 RF Output Creation ...... 18 2.5 Interlocks ...... 19
3 Tasks Performed by the Digital Signal Processor ...... 21 3.1 DSP Peripherals ...... 21 3.2 Control Program Overview ...... 22 3.3 Data Received From Host Processor ...... 23 3.4 Control Thread ...... 24 3.5 Status Thread ...... 25 3.6 Software Interrupts ...... 26
4 Control ...... 28 4.1 RF Amplitude and Phase Control ...... 28 4.2 Cavity Tuning ...... 29
5 The ZWorld RabbitCore Host Processor and Graphical User Interface ...... 32 5.1 Module Initialization ...... 32 5.2 User Interface ...... 33 5.3 Main Screen ...... 34 5.4 PID Screen ...... 36 5.5 AFC Screens ...... 37 5.6 Startup Screen ...... 40 5.7 Advanced Screen ...... 40
6 Testing and Performance ...... 42 6.1 Cavity Simulation Circuit ...... 42
iv 7 Conclusion and Future Work ...... 50 7.1 Conclusion ...... 50 7.2 Required Changes ...... 51 7.3 Future Hardware Upgrades ...... 52 7.4 Future Software Upgrades ...... 53
A FPGA Implementation of a CORDIC Algorithm ...... 55
B DSP Daughter Board Schematics ...... 59
BIBLIOGRAPHY ...... 71
v LIST OF TABLES
2.1 CORDIC algorithm example...... 15
2.2 Description of FPGA memory locations...... 16
3.1 Responses from the DSP are received by the host two words after the com- mand was transmitted...... 24
vi LIST OF FIGURES
1.1 Overview of the LLRF controller as it will be connected to an SRF cavity. The LLRF controller consists of everything inside of the dashed lines. . . . 4
1.2 LLRF controller motherboard. DSP daughter board is attached on the lower right corner. Host processor board attaches to back side. Front side contains the reference phase-locked loop and all input signal conditioning compo- nents. Back side contains the high-speed ADCs and DAC, FPGA, and output signal conditioning components...... 5
1.3 DSP daughter board. DSP is underneath the large black heat sink...... 6
1.4 ZWorld RabbitCore daughter board...... 6
2.1 Sampling a 50 MHz signal at 40 MSPS produces a 10 MHz alias whose phase is measured relative to the phase of the 10 MHz reference signal. . . 11
2.2 DAC output spectrum when producing output at 40 MSPS (left) and IF after 50 MHz band-pass filter (right)...... 19
2.3 DAC output spectrum when producing output at 80 MSPS (left) and IF after 50 MHz band-pass filter (right)...... 20
4.1 Block diagram of PID control. The cavity behaves linearly when operat- ing near its resonant frequency, so it can be approximated by the transfer function, G(s)...... 29
4.2 Adaptive feedforward cancellation control for the cancellation of a single sinusoidal disturbance [22]...... 30
5.1 Main controller screen...... 35
5.2 PID tuning screen...... 37
5.3 AFC screen...... 38
5.4 FFT screen shows FFT of cavity output in dBm, cavity magnitude response, and cavity phase response in degrees. All plots show 0 to 1000 Hz linear scale...... 39
5.5 Startup screen...... 40
5.6 Advanced screen...... 41
6.1 Block diagram of circuit used for cavity simulation. The two transfer func- tions are replaceable RC networks...... 43
vii 6.2 Each of the transfer function blocks is made up of a replaceable RC net- work...... 44
6.3 Ideal magnitude response (top) and magnitude response calculated by LLRF controller (bottom)...... 46
6.4 Ideal phase response (top) and phase response calculated by LLRF con- troller (bottom)...... 47
6.5 FFT of RF input with 60 Hz sinusoidal disturbance. Because the magnitude of the disturbance is large, its third harmonic is also present...... 49
B.1 System Overview...... 60
B.2 Voltage regulation and clock generation...... 61
B.3 DSP power connections...... 62
B.4 DSP bypass capacitors, UTOPIA port, HPI port and reserved pins...... 63
B.5 DSP serial connections...... 64
B.6 DSP JTAG emulation port and general purpose port...... 65
B.7 DSP external memory interface A...... 66
B.8 External SDRAM...... 67
B.9 DSP external memory interface B...... 68
B.10 External non-volatile memory and FPGA connection...... 69
viii CHAPTER 1
Introduction
The desire to do further research into particle physics has driven a demand for new high- energy accelerators. The reduced surface resistances of superconducting cavities make them capable of supporting high fields with low power losses. The quality factor (Q) of a cavity of given geometry is an indicator of how high a field it can achieve. While cavities with high quality factors can achieve higher internal fields, this comes at the expense of narrower bandwidth. The very narrow bandwidth associated with high Q cavities makes maintaining amplitude and phase control in the presence of perturbations increasingly dif-
ficult [1].
Feedback control is required to maintain a stable cavity field in the presence of a distur- bance. One can apply a PID control to maintain the amplitude and phase of the cavity field at a given set point. As perturbations shift the cavity’s resonant frequency away from the
RF driving frequency, the low-level radio frequency (LLRF) controller measures the error in the cavity field and compensates. Although this method works well for small perturba- tions, it will not work for large perturbations, since the required input power to maintain the cavity field will be too high. Therefore, for high-Q superconducting cavities, it is nec- essary to have an active tuning mechanism to cancel the disturbances to keep the driving frequency within the cavity’s bandwidth.
1 A properly designed continuous wave system will only have limited narrowband si- nusoidal disturbances due to vibrations (microphonics). Simrock et al. were the first to demonstrate using a piezoelectric actuator to cancel these disturbances [2]. Due to the com- plex transfer functions of multi-cell superconducting cavities, a feedback control would be exceedingly difficult to implement. However, Kandil et al. demonstrated an adaptive feed- forward cancellation (AFC) algorithm capable of canceling narrow-band vibrations in a multi-cell cavity using a dSpace development board connected to a PC [3]. Although the
AFC algorithm was shown to work, the implementation required a PC and several other pieces of equipment to control a single cavity. Therefore, it was not practical for use in a running linear accelerator, which will have many cavities that need to be controlled. The control needs to be implemented on a low-level radio frequency (LLRF) controller to be useful, which is the subject of this work. The LLRF controller will use the AFC algorithm to attenuate cavity detuning from significant narrow-band disturbances, and use a PID con- trol to continuously adjust the amplitude and phase of the RF driving signal to compensate for other disturbances.
Digital LLRF controllers are currently being designed at several accelerator labs to replace analog controls. Implementing controls in the digital domain reduces the size and cost of the hardware and allows the implementation of controls that are not feasible on analog systems [9]. Most of the new LLRF controllers being developed for applications that do not require a lot of computing power rely on a field programmable gate array (FPGA) to perform the RF measurements and control algorithms. The controllers being developed for the Spallation Neutron Source (SNS) accumulator ring [5] and International Linear
Collider (ILC) [6] are both based on FPGAs. For applications that require more processing
2 power, an FPGA with an embedded processor is commonly used [7]. Although some of the other LLRF controller designs provide a lot of the functionality required for the linear reaccelerator upgrade to the NSCL and could possibly be adapted if necessary, they do not meet all of the requirements for the reaccelerator upgrade. The problem with either of these designs is that upgrading the software for the system requires extensive knowledge of the
LLRF controller and experience with FPGA programming. One of the requirements for the
LLRF controller for the NSCL is that it must be possible for control engineers to update the software controls using tools they are familiar with, without needing to know the details about how the hardware is set up. Other requirements are that the LLRF controller must be completely standalone, requiring only a network connection to communicate with the
EPICS control system [8], it needs to provide tuner outputs for microphonics mitigation, and it needs to have a user-friendly interface for setup and monitoring.
Figure 1.1 shows an overview of the LLRF controller developed here, which was in- spired by the LLRF controller designed by Lawrence Berkeley National Laboratory [9].
The LLRF controller consists of a motherboard (Figure 1.2), a DSP daughter board (Fig- ure 1.3), and a control host board (Figure 1.4). The input signal conditioning portion of the motherboard is unchanged from the previous iteration of the project: the digital phase meter developed by Adam Molzahn [10]. However, there have been major changes to the digital sections. The biggest change is that a high-performance DSP has been added to the controller. All of the digital processing is now done by the DSP, so all data is sent from the FPGA directly to the DSP instead of the host processor. The DSP runs the PID based amplitude and phase control algorithms and feedforward based microphonics mitigation algorithms and sends data to the control host processor as necessary. This frees up enough
3 Figure 1.1. Overview of the LLRF controller as it will be connected to an SRF cavity. The LLRF controller consists of everything inside of the dashed lines.
FPGA logic to allow it to perform a 16-bit coordinate rotation digital computer (CORDIC) algorithm [11] on all incoming channels to obtain their phase and magnitude information.
The parallel nature of the FPGA makes it the ideal place for doing the phase and amplitude conversions, since it can do all input channels simultaneously without slowing down the rest of the system. By converting all input channels simultaneously, we guarantee that a read of all input channels returns amplitude and phase information taken at the same sample time.
There are five RF inputs on the front of the controller module. One is a reference signal
(10 MHz), used to control the sample clock for the high-speed analog-to-digital converters
4 Figure 1.2. LLRF controller motherboard. DSP daughter board is attached on the lower right corner. Host processor board attaches to back side. Front side contains the reference phase-locked loop and all input signal conditioning components. Back side contains the high-speed ADCs and DAC, FPGA, and output signal conditioning components.
5 Figure 1.3. DSP daughter board. DSP is underneath the large black heat sink.
Figure 1.4. ZWorld RabbitCore daughter board.
6 (ADCs) used to digitize the inputs and to synchronize multiple modules when they are implemented together in an accelerator. Three of the RF inputs are the input signals to be measured (forward power, reflected power, and cavity output). Depending on mixer and
filter parts selection when assembling the modules, the inputs can be between 2 MHz and
1.5 GHz, with power levels from -7 dBm to +33 dBm. However, there are some frequencies within that range that will not work well due to interactions of the harmonics that may be present within the intermediate frequency. The final RF input is the local oscillator (LO) input, which must be at a frequency 50 MHz higher or lower than the RF input frequency and phase-locked to the reference signal. The LO signal is mixed with each RF input to convert them to the 50 MHz intermediate frequency (IF) for sampling. The fixed 50 MHz intermediate frequency is used, because it is easier to digitize a signal with a fixed, known frequency. An ideal mixer produces frequencies which are the sum and difference of its two input signals as shown in Equation (1.3). Since the LO signal is chosen 50 MHz higher or lower than the RF frequency, one of the components of the mixer output is at 50 MHz, and the other is filtered out using a 50 MHz band pass filter. Also, since the LO is phase-locked to the reference signal, θ2 is fixed and can be calibrated out. Therefore, phase changes in the RF input directly affect the phase of the IF signal.
RF = A1sin(ω1t + θ1) (1.1)
LO = A2sin(ω2t + θ2) (1.2)
A A A A RF ∗ LO = 1 2 cos((ω + ω )t + θ + θ ) − 1 2 cos((ω − ω )t + θ − θ ) (1.3) 2 1 2 1 2 2 1 2 1 2
7 The remaining front panel connectors are the RF output, a tuner output, RF On/Off input, reset input, and a fault output. The RF output is produced by creating an output at the IF, then mixing it with the LO to produce a signal at the desired frequency. The fast tuner output is an analog signal that is designed to cancel microphonics up to 1 kHz. A slow tuner output is provided that can be used to compensate for slow drifts in the resonant frequency of the cavity. The rest of the signals are digital control signals.
8 CHAPTER 2
Signal Digitization and Interlocks
The field programmable gate array’s (FPGA) primary task is to collect the data sampled by the high-speed ADCs and buffer it until it is requested by the DSP. The configurability and parallel nature of the FPGA makes it ideal for collecting and buffering the sampled RF signals. The FPGA’s other tasks include setting the digital attenuators on the input channels and taking care of some of the interlock signals. The FPGA used in this project is a Xilinx
Spartan-II XC2S150. Although it is adequate for this project, future versions will probably move to a newer, faster FPGA with more available logic.
2.1 Collecting Input Samples
To be able to calculate the amplitude and phase of the signal, we need a vector-based measurement of the signal with respect to a reference. If the samples are taken at 90◦ intervals, then the vector realizations can be equated to the real and imaginary components of a vector in the complex plane. If the first sample is taken as the real component of the signal, then the second sample is 90◦ lagging and is equated to the imaginary component of the signal. In the absence of a DC sampling error, the third sample is the negative of the first sample and the fourth sample is the negative of the second sample. The first and
9 third and second and fourth samples can be averaged to remove any DC sampling error.
Once the real (I) and imaginary (Q) components are known, the phase and magnitude can be computed using: Q Phase = tan−1 (2.1) I
p Magnitude = I2 + Q2 (2.2)
The phase information gathered with this method can be used to tell the relative phase between inputs, but is not meaningful when using multiple LLRF controllers in a system, since the first sample is taken at an arbitrary time. Therefore, one of the RF inputs is used as a reference signal. The phase of the reference signal is subtracted from the phase of each input to produce phases relative to the reference signal, which allows multiple LLRF controllers to be synchronized with each other.
In a variable frequency system, it can be difficult to take samples every 90◦ since the time delay between samples depends on the signal frequency. However, since all of our inputs have been mixed to 50 MHz, we have a known frequency, and just need to choose an appropriate sample rate [10]. To take samples every 90◦ of the input signal, we need four samples per period, and therefore, a sample rate of 200 MSPS. ADCs that can sample at 200 MSPS are expensive, so it is not cost-effective to use them, and it was necessary to
find another way to get the I and Q values. By removing the condition that all four samples in a measurement must come from the same period of the input signal, we can use a lower speed, less expensive ADC. Therefore, a sample rate of 40 MSPS was chosen. Sampling at
40 MSPS produces a 10 MHz alias with the same amplitude and phase as the 50 MHz IF signal (Figure 2.1) and gives us samples taken every 90◦ as desired.
10 Figure 2.1. Sampling a 50 MHz signal at 40 MSPS produces a 10 MHz alias whose phase is measured relative to the phase of the 10 MHz reference signal.
11 Each ADC samples its input on the rising edge of the 40 MHz sample clock. The FPGA reads the 14-bit data output of each ADC on the falling edge of the clock, when the data becomes valid. The FPGA samples all inputs simultaneously, so the relative phases of each channel are preserved, even if one or more of the input channels are drifting in phase.
As seen in Figure 2.1, by sampling the intermediate frequency (50 MHz) at 40 MHz, the system produces samples that are 90◦ apart, and if the phase of the input is constant, the input sequence will repeat every four samples. The FPGA passes every input through a 10
MHz first-order digital band-pass filter to try to remove noise that might have been picked up by the ADC during sampling [12]. Next, each set of samples is saved as either I, Q, −I, or −Q, depending on the value of a 2-bit counter. The FPGA then averages the I and −I and Q and −Q pairs and buffers them so they can be accessed by the DSP. The averaging removes any DC offset from the samples, to give the real and imaginary components of the vector.
2.2 CORDIC Algorithm
Since most vector calculations done by the DSP need to be done in polar coordinates, it is necessary to implement an efficient algorithm for conversion between the rectangular and polar coordinates. In the previous iteration of this project [10], these conversions were done by the host processor using equations (2.1) and (2.2). However, doing the conver- sions in the host processor is much too slow to be reused here. One option to speed up the conversions was to implement the same conversion in the DSP. However, implement- ing the conversion in the DSP uses a surprisingly large amount of CPU time and would
12 greatly reduce the amount of computing time available for the control algorithms. The best
option is to implement the conversions in the FPGA using the Coordinate Rotation Dig-
ital Computer (CORDIC) algorithm. The CORDIC algorithm was designed in the early
days of digital computers as a way to perform conversions between polar and rectangular
coordinates quickly using a small number of gates. It uses a series of multiplications by
known complex numbers to shift the input vector to 0◦, while keeping a running total of the
amount of phase shift it has added. After shifting the input vector to 0◦, we know that the
output vector’s real component is the input vector’s magnitude, and the input vector’s phase
is the negative of the total phase shift. By selecting the phase shifts carefully, each step of
the algorithm can be implemented using only right-shifts and addition or subtraction [13].
Another advantage of the CORDIC algorithm is that it does not have to produce its
output in any particular type of unit, so we are not restricted to using radians or degrees to
represent the phase. To speed DSP calculations, the system represents phase as a raw 16-bit
360 value, with each bit representing 65536 degrees. This is advantageous because the DSP no
longer has to check whether its results are between 0◦ and 360◦, since any result that would
normally fall outside this range simply overflows and wraps around to the desired value.
In each stage of the CORDIC algorithm, we check the sign of the Q value to decide
whether to add or subtract phase. The first stage is a 90◦ shift. If Q is positive, the I and
Q values are swapped and the new Q value is negated to produce a −90◦ shift, and 90◦ is added to the cumulative phase. If Q is negative, the I and Q values are swapped, the new I
value is negated to produce a +90◦ shift, and 90◦ is subtracted from the cumulative phase.
(I + Q j)(0 + j) = −Q + I j (2.3)
13 (I + Q j)(0 − j) = Q − I j (2.4)
In subsequent stages, the shifts are performed by multiplying the intermediate vector by a vector of the form 1 + 2−n j or 1 − 2−n j, depending on the sign of Q.
(I + Q j) 1 + 2−n j = I − 2−nQ + Q + 2−nI j (2.5)
(I + Q j) 1 − 2−n j = I + 2−nQ + Q − 2−nI j (2.6)
Since the FPGA stores numbers in binary format, 2−nI is equal to I shifted to the right by n bits, and 2−nQ is equal to Q shifted to the right by n bits. The second stage of the algorithm uses n = 0, and n is increased by 1 in each subsequent stage. The algorithm gains approximately 1 bit of resolution in each stage it performs, so it runs 16 stages as set up in the FPGA. The FPGA performs each stage of the routine on the rising edge of the ADC sample clock, and it does 16 stages per conversion, so the FPGA is able to convert every fourth set of I, Q, −I, and −Q values for each channel. This produces phase and magnitude pairs 2,500,000 times per second, which is much faster than the DSP will request them.
One issue that needs to be taken into account with this algorithm is that after the first stage, each multiplication changes the magnitude of the vector being converted, not just the phase. However, the total magnitude scaling is a constant dependent only on the number of iterations of the algorithm. Therefore, the magnitude scaling inverse can be calculated ahead of time and can be used to cancel the scaling effect. Table 2.1 shows an example conversion including the magnitude scaling constant. The cumulative phase converges toward the actual phase of 53.8◦, and I (divided by the magnitude constant) converges to
14 Table 2.1. CORDIC algorithm example.
Stage I Q Cum. Phase Mag. Constant Next Phase Shift 0 150 205 0◦ 1 −90◦ 1 205 -150 90◦ 1 45◦ 2 355 55 45◦ 1.41421 −26.565◦ 3 382.5 -122.5 71.565◦ 1.58114 14.036◦ 4 413.125 -26.875 57.529◦ 1.62980 7.125◦ 5 416.484 24.766 50.404◦ 1.64248 −3.576◦ 6 418.032 -1.265 53.98◦ 1.64569 1.790◦
the actual magnitude of 254.02.
In order to produce the high-speed DAC output from the desired phase and magnitude information, it is necessary to perform the CORDIC algorithm in the reverse direction. The algorithm is almost identical, except that the FPGA starts with the desired magnitude in I, the desired phase in the phase accumulator, and Q = 0. Then, it performs shifts based on the sign of the phase value until the phase is shifted to 0. Again, there is a scaling factor in the conversion, so the DSP must multiply the desired magnitude by the scaling factor’s inverse before sending the phase and magnitude pair to the FPGA.
2.3 DSP Interface
The fastest way to transfer data between the DSP and a peripheral is through one of its two external memory interfaces (EMIF). To connect the FPGA to the DSP, I set up the FPGA to appear as a 16-bit asynchronous RAM, then defined memory locations that the DSP can read or write to send or receive data [14]. Because of the small number of available pins on the FPGA, I could only set up 32 memory locations, but this is sufficient for the current system. The memory locations are shown in Table 2.2.
15 Table 2.2. Description of FPGA memory locations.
Add. Description Read/Write Add. Description Read/Write 0 Ch1 - Ref. Phase Read-only 16 Ch1 I Read-only 1 Ch1 Amplitude Read-only 17 Ch1 Q Read-only 2 Ch2 - Ref. Phase Read-only 18 Ch2 I Read-only 3 Ch2 Amplitude Read-only 19 Ch2 Q Read-only 4 Ch3 - Ref. Phase Read-only 20 Ch3 I Read-only 5 Ch3 Amplitude Read-only 21 Ch3 Q Read-only 6 Always Outputs 0 Read-only 22 Ref I Read-only 7 Ref. Amplitude Read-only 23 Ref Q Read-only 8 Output Phase R/W 24 Output I Read-only 9 Output Amplitude R/W 25 Output Q Read-only 10 Error Register Read-only 26 I Input R/W 11 Digital Attenuator R/W 27 Q Input R/W 12 Ref. Phase Read-only 28 I Input R/W 13 Unused R/W 29 Q Input R/W 14 Output (shifted 225◦) I Read-only 30 Phase Output Read-only 15 Output (shifted 225◦) Q Read-only 31 Magnitude Output Read-only
The phase and magnitude information discussed in the previous section is available to the DSP in memory locations 0 to 7. When the DSP performs a sequential read of the input channels, the FPGA temporarily stops updating the data. This guarantees that the data from each channel was obtained at the same time. The FPGA begins updating the data when the
DSP reads or writes any other location. The phase of each channel is given to the DSP relative to the reference phase. As a result, the reference phase in register 6 is always 0. In the event that the absolute phase of the reference signal is desired, it is available in register
12. The I and Q values for each input channel are available in memory locations 16 to 23.
The DSP sets the RF output by writing a desired phase and amplitude to registers 8 and 9. The FPGA automatically runs the new settings through its CORDIC routine and produces corresponding I and Q values in locations 24 and 25. The I and Q values are sent to the high-speed DAC to produce the RF output. When producing the output at 80 MSPS,
16 the FPGA uses a total of 8 samples, and therefore needs two sets of I and Q pairs. The
extra pair is produced by adding 225◦ to the desired output phase before passing it through the CORDIC routine. The extra I and Q values are available in locations 14 and 15.
Six of the memory locations (26 to 31) are for an additional CORDIC routine. When the DSP writes a set of I, Q, −I, and −Q values to registers 26 through 29, the FPGA runs the CORDIC algorithm on the set of input data and produces a phase and magnitude pair in registers 30 and 31. These registers are used when the DSP is measuring the transfer func- tion of the cavity, to find the value of the phase shift and magnitude at each measurement frequency.
The value of the digital attenuators is controlled by register 11. The digital attenuators have six control bits, so the uppermost ten bits of this register are not used and are read as
0. A value of 0 corresponds to the minimum attenuation, and a value of 63 corresponds to the maximum attenuation.
Memory location 10 shows the over-voltage status of each ADC and the status of each interlock. Each ADC has a pin that is set high if the input voltage to the ADC is too high to produce a valid reading. The over-voltage pins are connected to the 4 least significant bits of register 10. If the digital attenuators are set up correctly and there is no malfunction in the module, these bits will read 0. Bits 4 and 5 correspond to the reset signal and on/off signal, respectively. During normal operation, these bits will both read 0.
There is one unused register, in location 13. It can be read from and written to by the
DSP, but currently does not perform any function in the FPGA.
17 2.4 RF Output Creation
The input sampling process can be reversed to produce the RF output. Since the DSP
provides the output set points as phase and amplitude pairs, the FPGA first passes the set
points through the CORDIC routine to produce the I and Q values. Since it takes 400 ns
for the FPGA to complete a single CORDIC conversion, and the FPGA is set up to con-
tinuously perform conversions on the values stored in the phase and amplitude registers, it
takes between 400 ns and 800 ns before a new setting affects the output. The −I and −Q values are created by negating the I and Q values. The final step necessary before sending the values to the output DAC is to convert them into the proper format. The FPGA repre- sents numbers internally as 16-bit two’s complement numbers (-32768 to 32767), while the
DAC expects 14-bit straight binary numbers (0 to 16383). The FPGA converts each output sample by complementing the most significant bit to put each sample into 16-bit straight binary format and ignores the two least significant bits to shrink the number to the required
14 bits.
The FPGA passes the I/Q/−I/−Q values to the output DAC at 40 MSPS to produce the RF output. The DAC produces a square wave, so the output is not made up of a single frequency component; the output contains a 10 MHz signal and its odd harmonics (30
MHz, 50 MHz, 70 MHz, etc.) as shown in Figure 2.2. Since we only want the 50 MHz signal to be present, the DAC output is passed through a 50 MHz filter, which attenuates the unwanted frequencies.
Increasing the sampling rate of the DAC should provide both a better signal-to-noise ratio and increase the power of the 50 MHz signal [15]. The output DAC supports sample
18 Figure 2.2. DAC output spectrum when producing output at 40 MSPS (left) and IF after 50 MHz band-pass filter (right).
rates up to 165 MSPS, but the current RF board design limits the DAC sample rate to
80 MSPS [16]. To create the RF output at 80 MSPS, we need to cycle through eight samples, taken at 0◦, 225◦, 90◦, 315◦, 180◦, 45◦, 270◦, and 135◦. Four of these samples
(0◦, 90◦, 180◦, and 270◦) correspond to the I/Q/−I/−Q samples used when producing the output at 40 MSPS. To produce the other four samples, the FPGA adds 225◦ to the desired phase value and then sends the new phase and amplitude pair through the CORDIC routine.
Producing the RF output at 80 MSPS yielded an approximately 5.3 dB increase in power at the intermediate frequency and approximately a 3.0 dB improvement in the signal-to-noise ratio as shown in Figure 2.3.
2.5 Interlocks
The module has three external connections for safety interlocks: RF enable, fault, and reset. All of the interlocks are TTL signals that are connected through the FPGA so that
19 Figure 2.3. DAC output spectrum when producing output at 80 MSPS (left) and IF after 50 MHz band-pass filter (right).
their behavior can be reconfigured if necessary. The module’s RF output must be disabled unless the RF enable interlock is low. This is accomplished by tying the RF enable signal to the power down pin on the high-speed DAC. The fault interlock is an output, which can be used to signal the rest of the RF control system. It is currently unused, since the module is not programmed to detect faults. If the module were to detect a fault, it would disable the
RF output, set the fault signal, and wait for a reset signal. When a rising edge is detected on the reset input, the module will reset the fault signal, and enable the RF output (if the
RF enable interlock is low).
20 CHAPTER 3
Tasks Performed by the Digital Signal
Processor
The control processing is performed by a Texas Instruments TMS320C6414T fixed-point
DSP. It was chosen because of its high speed and available software tools. In the current iteration of the module, the DSP is running at 360 MHz, but if more performance is required in the future, the DSP clock speed can be increased to 1 GHz. Although all of the current code is written in C and assembly, code can be generated from MATLAB using the Real-
Time Workshop Embedded Coder. This will allow control engineers using the module to change control algorithms using tools they are familiar with.
3.1 DSP Peripherals
The DSP has two 4 MB flash EEPROM modules connected via the same memory bus the FPGA uses. The first is an 8-bit wide memory divided into four 1 MB pages and is used to store the programs. After reset, the DSP checks the status of two of the host processor output pins to determine which program it should boot. Then, it sets the page of the program ROM accordingly and loads the program into internal RAM. The second
21 module is 16 bits wide and is divided into two 2 MB pages. It is used as storage for large lookup tables and any measurements that need to be stored in non-volatile memory, but need to be accessed quickly. The current program stores a 16-bit sine lookup table and the measured cavity transfer function in this ROM.
One of the DSP’s serial ports is connected to a Texas Instruments DAC8554 4-output digital-to-analog converter. The DAC has a maximum sample rate of 200 KSPS on all outputs [17]. Output A is used to produce driving signal for the cavity’s piezoelectric tuner, and output B can be used to produce a slow tuning signal, which can be used to compensate for slow drifts in the resonant frequency of the cavity. The other two outputs are currently unused and are available for future applications. The cavity tuner signals are connected to an operational amplifier to amplify their signals.
Although the DSP has 1 MB of internal RAM, an external 16 MB SDRAM is provided in case future programs need more memory for their calculations. The SDRAM is 32-bits wide and operates at 125 MHz.
The DSP printed circuit board also includes a temperature sensor to measure the tem- perature inside the module. It is used as a status indicator to signal if the module is not getting enough airflow to prevent overheating.
3.2 Control Program Overview
The control program is set up as a multi-threaded program; with each thread being triggered by a different hardware or software interrupt as necessary. Higher priority interrupts are allowed to preempt lower priority threads. Receiving a data word from the host processor
22 triggers the highest priority thread. The main control thread has the second highest priority, and is triggered by a counter, so that it runs at fixed intervals. The final hardware-triggered thread runs much less frequently than the other two, and does some low-priority status calculations. The threads triggered by software interrupts are used for routines that take a long time to perform and need to be done outside the hardware interrupt threads to prevent them from missing their deadlines.
3.3 Data Received From Host Processor
The serial connection between the DSP and host processor is full duplex and uses the same clock and synchronization signals for data traveling in both directions [18]. This means that the DSP must have data buffered and ready to transmit back to the host processor when the next word is received, because data is transmitted simultaneously in both directions as shown in Table 3.1. If the DSP is unable to respond to a command before the next command is received, incorrect data could be displayed on the user interface, so the thread that processes host commands was given the highest possible priority. This guarantees that the DSP will finish processing the current command and have a response ready for the host processor before the next command is received.
Each data word sent between the DSP and host processor is 32-bits, and is sent most significant bit first over the host processor’s SPI port. Each command from the host is broken into three parts: the first bit is a 0 for a write and 1 for a read (this bit is ignored for read-only registers), the next 15 bits are a register address, and the last 16 bits are an optional argument. The exception to this format is when the host is sending a new program
23 Table 3.1. Responses from the DSP are received by the host two words after the command was transmitted.
Transmission Word Command to DSP Response to DSP 1 Command 1 Null Response 2 Command 2 Null Response 3 Command 3 Response 1 4 Command 4 Response 2 5 Command 5 Response 3 6 Command 6 Response 4 7 Command 7 Response 5 8 Null Command Response 6 9 Null Command Response 7
to the DSP. In this case, the host initiates the transfer by writing the program number and block number to register 0x0102, and then it sends a 64 kB block of the new program to the DSP. After the block of data is done being programmed, the host processor repeats the process for the remaining blocks (if necessary).
The DSP response format varies depending on the command it has received. If it re- ceives a command to update a setting, it echoes back the setting to acknowledge that the setting has been updated, or in cases where the setting cannot be changed, the DSP replies with −1. If the host processor reads a register, the DSP simply sends back the value of that register in whatever format it uses for calculations; the host must then convert the value to a meaningful format before sending it to the GUI.
3.4 Control Thread
The control thread has the second-highest priority. It runs at fixed intervals based on one of the DSP’s internal timers. In the current setup, this thread runs 16,387 times per second,
24 but the timer can be modified to run at virtually any interval. The primary tasks for this thread are to perform the phase PID, amplitude PID, and adaptive feedforward cancellation
(AFC) algorithms. Additional lower priority tasks are performed by other threads..
The control thread begins by reading the phase and amplitude of each input channel from the FPGA. It also stores the I and Q values of the cavity output in a buffer so that a fast Fourier transform (FFT) can be computed. If the FFT buffer is full, this thread posts the software interrupt that initiates calculation of the FFT. The FFT is used to identify low frequency (0 to 1000 Hz) sinusoidal disturbances affecting the cavity. Next, if a user is tuning the PID parameters and has pulsing enabled, the thread takes care of switching between the two phase or amplitude set points. After this is done, the thread runs the PID, cavity transfer function measurement, and AFC algorithms (if enabled) and updates the output phase and amplitude and sets the fast tuner. The cavity transfer function cannot be calculated correctly if either PID or AFC control is enabled, so logic is implemented to prevent them from being enabled at the same time. This is because the cavity transfer function algorithm assumes the cavities RF input has constant amplitude and phase, and it uses the fast tuner output to shake the cavity.
3.5 Status Thread
The final hardware thread runs much less frequently than the other two, and performs some low-priority tasks. It is triggered by a read from the ADC connected to the temperature sensor on the DSP’s circuit board. The read occurs at the maximum possible interval al- lowed by the DSP’s serial port hardware. This thread calculates the board temperature in
25 Celsius and the average DSP load over the previous interval and stores the values until the
host processor requests them.
3.6 Software Interrupts
There are several threads that are implemented as software interrupts. They are used to
perform tasks that take a long time to run and are not time critical. If any of these tasks were
implemented within the hardware threads that initiate them, the hardware thread would fail
to complete in its allotted time.
The highest priority software thread is the one that computes an FFT on a set of complex
data samples. It is based on the DSP fft16x32 function included with the DSP program- ming tools [19]. The function computes an FFT on 32-bit complex data samples and uses a 16-bit “twiddle factor” look-up table to speed up processing. There are two versions of this function included with the DSP programming tools. The first is a hand-optimized as- sembly language version that is extremely fast, but is not interruptible. The second is an implementation of the same algorithm written in C. Although the C version is not as fast as the optimized version, it is interruptible, and is therefore the better choice for this system.
The FFT has complex output, but we are only interested in seeing the magnitude response in the GUI, so as a final step, the FFT thread runs a 32-bit CORDIC routine on the complex
FFT output to find the magnitude for each frequency. The output is saved until the host processor reads it and initializes the next FFT calculation.
The last two threads are used to program memory into the flash EEPROMs that are connected to the DSP. One thread programs the measured cavity transfer function into
26 ROM, so it is not lost at reset or power down. The other thread programs a 64 KB block of the program ROM. Although these threads have almost no calculations in them, they take the longest to complete. Before programming a ROM, the corresponding memory block must be erased, which typically takes around 800 ms. Then, each word can be programmed at a typical rate of approximately 10 µs [20]. As a result, the time spent in these threads is mostly spent in an idle loop, polling the ROMs to find out when they are ready for the next word to be programmed.
27 CHAPTER 4
Control
4.1 RF Amplitude and Phase Control
Cavity control is typically done using a PI controller, so a PID control was implemented to control the RF output, using feedback via the controller’s cavity input. The DSP program allows separate PID control of the phase and amplitude of the signal, and some other tools have been included in the GUI to ease the PID tuning process. When operating at RF frequencies near a cavity’s resonant frequency, the cavity behaves approximately linearly, so we can model the relationship between the RF driving signal and the cavity output using a transfer function. Figure 4.1 shows the closed-loop system. During operation, the RF frequency is fixed, but the amplitude and phase can be adjusted. Therefore, the system input and output are complex numbers. Since the system has a pole at s = 0, the system is type 1 and values can be chosen for kp, ki, and kd to ensure the system response to a step input has zero steady-state error [21].
The transfer functions of the cavities being controlled vary dependent on the cavity type and amplifier system used, so the PID parameters must be tuned when equipment is changed. This tuning has historically been done by manually turning the RF output on and off, measuring the system response, and adjusting the PID parameters as necessary.
28 complex complex set point 2 kps+ki+kds output + G(s) - s controller plant
Figure 4.1. Block diagram of PID control. The cavity behaves linearly when operating near its resonant frequency, so it can be approximated by the transfer function, G(s).
The DSP speeds up this process by automatically stepping between two set points and displaying the step response in the GUI. As the users change the PID parameters, they can immediately see the change in the system response. The PID loop compensates for small non-linearities and slowly varying drifts.
4.2 Cavity Tuning
We expect that most disturbances, not controlled by the PID alone, that will affect the cavities in the reaccelerator will be of the narrowband sinusoidal variety and due to rotating machinery, such as vacuum pumps. In order to cancel out these disturbances, the adaptive feedforward control developed by Tarek Kandil [22] was implemented in this module. The
DSP is programmed to cancel disturbances at up to 10 frequencies. A block diagram of a single-frequency control is shown in Figure 4.2. GT (s) is the transfer function from the cavity tuner output to the phase error seen in the cavity output signal. The tuner has the affect of shifting the cavity resonant frequency, which results in an error in amplitude and phase as seen by the controller. When operating at RF frequencies near the cavity resonant
29 Figure 4.2. Adaptive feedforward cancellation control for the cancellation of a single sinu- soidal disturbance [22].
frequency, a given change in tuner output has a relatively large effect on the phase error compared to its effect on the amplitude error, so the phase error is used for the adaptive feedforward cancellation algorithm.
The disturbances we expect to encounter are made up of multiple sinusoidal signals:
n n de f d = ∑ Aisin(ωit + βi) = ∑ aicos(ωit) + bisin(ωit) (4.1) i=1 i=1
Before the adaptive feedforward cancellation algorithm can be applied, we need to know the frequency of the disturbance to be cancelled and the phase of GT (s) at that frequency.
To calculate the phase of GT (s), we start with the RF amplitude and phase set to fixed values (PID disabled), and drive the tuner while measuring the cavity response. The tuner is driven in 1 Hz increments from 1 Hz to 1 kHz, and the magnitude and phase response of the
30 cavity phase error is measured at each frequency. The measured Bode plot is representative
of the system transfer function, GT (s). The plot is stored in non-volatile memory so it is not
necessary to calculate it every time the controller is powered down or reset. The disturbance
filters use this information from the measured Bode plot to stably apply the feed-forward
algorithm. The value of each ωi is determined by performing an FFT on the cavity error
signal ψ and looking for the frequencies with the highest magnitudes. However, ai and bi
are unknown, and must be estimated. We estimate these two parameters by multiplying the
error signal by a gain factor and two orthogonal signals of known phase and then integrating
the results. The control output is then created from the estimated values as:
n n ˆ de f ˆ ˆ u = ∑ aˆicos(ωit) + bisin(ωit) = ∑ Aisin ωit + βi (4.2) i=1 i=1
As long as the measured phase delay θ is within 90◦ of the actual phase delay and γ is chosen sufficiently small, the estimated valuesa ˆi and bˆi will converge to the actual values
ai and bi, as shown in Chapter 3 of [22]. γ controls the rate at which the estimated param- eters adapt to changes in the actual values, so increasing γ can cause the control to also
dampen disturbances that are close in frequency to ωi [23]. This occurs because the large γ
allows the adaptive parameters to continuously change phase to match the frequency of the
disturbance, even though it is not the exact frequency the algorithm is set up to cancel.
31 CHAPTER 5
The ZWorld RabbitCore Host Processor and Graphical User Interface
The ZWorld RabbitCore 3200 microprocessor acts as the host processor for the module.
The RabbitCore 3200 was selected because of the large amount of code already developed for it for other systems at the NSCL, but any other processor that supports the serial periph- eral interface (SPI) protocol and has a sufficient number of I/O pins could be used instead.
The host performs initial chip configuration for all the integrated circuits used in the mod- ule. After configuration is complete, the host processor acts as an interface between the
GUI and the DSP. It forwards commands received via its network interface to the DSP and passes data received from the DSP over Ethernet back to the GUI. In addition, it also supplies an interface based on the Modbus protocol to the main EPICS control system [8].
5.1 Module Initialization
After the system powers up, the host processor must initialize all of the other chips in the module. Most of this is done using the SPI before data transfer can begin. The high-speed
ADCs must be set from test mode to normal operating mode, and the phase-locked loop
32 must be set to the correct multiplier value. The SPI interface is also used to program the
FPGA. The RabbitCore module contains a large enough flash ROM to hold both its code and the FPGA’s code in compressed format, so it is not necessary to download the FPGA code every time the module is powered up.
After the first three initialization steps are completed, the SPI is used for transmitting commands and data between the host processor and the DSP. The DSP has its own non- volatile memory for program storage, so the host processor does not need to send the DSP its program at startup as it does with the FPGA. The DSP is set up to select between up to four programs when it is reset to make testing and debugging easier. When modifications are made to the DSP program, the new code can be downloaded without erasing the previ- ous versions. Programmers can then quickly switch between different versions of the code to verify that bugs in one version are not present in others. In its initial boot stages, the
DSP checks the status of two of the RabbitCore’s output pins to determine which program to load.
5.2 User Interface
After module initialization is complete, the host processor’s primary task is to act as an interface between the user and the DSP. It passes user commands to the DSP using its SPI interface and passes data back to the user. Unlike previous versions of this project, which used a telnet interface, this version has a graphical user interface. It was written in QT so that it will compile and run on all major operating systems [24]. The GUI is much easier to use than the older telnet interface, since the user no longer needs to memorize all of the
33 commands. The GUI also has much more functionality, since it can display graphs of the input, cavity transfer function, and FFT of the cavity output.
5.3 Main Screen
A screenshot of the main controller screen is shown in Figure 5.1. The top part of the screen shows the amplitude and phase of each input channel. The phase is shown relative to the reference channel, and the reference phase is always shown as 0.
Below the input status is the attenuator setting. It accepts values between 0 dB and
63 dB. For maximum measurement accuracy, the attenuator should be set to a value that allows the inputs to be as close as possible to 2.3 V without going over.
Below the attenuator box are the RF output control settings. In the open-loop mode, I and Q values are calculated from the phase and amplitude set points and are sent directly to the high-speed output DAC. In the closed-loop mode, a PID control algorithm is used to set the cavity output to the desired settings. The phase and amplitude controls can be set to open-loop or closed-loop independently of each other.
The two graphs on the bottom show the CPU load for the DSP and the ZWorld host processor. The DSP load should appear fairly constant, with the exception that it will spike to 100% when calculating an FFT or writing data to a ROM. The spikes are normal and will not affect the ability of the DSP to run the control algorithms, because the control thread has higher priority than the other threads and will interrupt them as necessary.
The ZWorld Save button saves the current settings as the defaults to load after a power up or reset. The settings include all settings on the main screen, PID screen, and AFC
34 Figure 5.1. Main controller screen.
35 screen, with the exception of the RF On/Off status. The RF is always off by default after power up. The ZWorld Reload button returns all settings to their defaults without resetting the system. The ZWorld Reset and DSP Reset buttons allow individual resets of the ZWorld host processor and DSP. The DSP Reset button also allows the user to select which program to run on the DSP. The DSP can hold four different programs in separate pages of its program ROM. This allows new DSP code to be downloaded to the DSP’s program ROM without overwriting the previous version of the program. If there is a problem with the new program, the DSP can be reset and told to reload the old version without putting the module into an unusable state. The rest of the buttons open screens discussed below.
5.4 PID Screen
The PID tuning screen was designed to ease tuning of the PID control loops by making it possible to see the system response in real-time as the control parameters are modified.
The phase and amplitude PID control constants can be tuned independently of each other.
To see the response of the cavity, the user simply has to set a nominal and pulsed value and click the run button to start stepping between the two set points. The controller will automatically step between the two set points and the GUI will show the step response.
The stepping frequency can be changed to affect how much of the waveform appears on the screen at a time. Figure 5.2 shows the amplitude PID being tuned. It is best to turn off the AFC algorithm when tuning the PID parameters, because the error signal affects both the PID and AFC algorithms. Although the DSP code was written to minimize the effect of the step signal on the AFC algorithm, there is still some ringing produced by the tuner if
36 Figure 5.2. PID tuning screen.
it is enabled while tuning the PID parameters.
5.5 AFC Screens
There are three main parts of the AFC screens, the FFT magnitude plot, cavity transfer function, and the AFC cancellation screen. The DSP measures the cavity transfer function by outputting a sine wave on the cavity tuner and measuring the cavity’s response. The tuner output is swept from 1 Hz to 1 kHz to produce the graphs shown in the GUI. The cavity transfer function is also stored in non-volatile memory to prevent it from being lost
37 Figure 5.3. AFC screen.
during a reset. Automatic disturbance detection and cancellation has not been implemented yet, so it is up to the user to identify the frequencies at which disturbances are occurring.
This is done by finding peaks on the FFT magnitude plot and entering their frequency into the AFC Cancellation Frequency box. The DSP automatically loads the previously calculated cavity phase delay for that frequency, and when enabled, outputs a disturbance cancellation signal at the selected frequency. Up to 10 frequencies can be enabled at a once.
There are master enable and disable buttons for the tuner, which can be used to enable or disable the tuner without having to manually select every cancellation frequency.
38 Figure 5.4. FFT screen shows FFT of cavity output in dBm, cavity magnitude response, and cavity phase response in degrees. All plots show 0 to 1000 Hz linear scale.
39 Figure 5.5. Startup screen.
5.6 Startup Screen
The module has a start-up mode, where its RF output gradually ramps to its set point after enabled. The user can specify an initial RF output level, the amount of time to stay at that level, and a ramp time to the amplitude set point. This feature allows the RF system to tune-up gradually before going full-scale and removes the initial overshoot that will occur if the PID parameters are under damped.
5.7 Advanced Screen
The Advanced screen contains features that are not used during normal operation. This screen contains buttons for downloading a new DSP program and calibrating the input channels. Program download is done over Ethernet, and can be done without affecting the program currently running on the controller. The DSP’s program ROM can contain up to four independent programs, so a new program can be downloaded without overwriting
40 Figure 5.6. Advanced screen.
the one that is being run. When a program is being sent to the DSP, the GUI screens will temporarily stop updating, and commands sent via the GUI will be queued, but the module will continue to run as normal. When the download completes, GUI updates will resume and any queued commands will be sent to the module.
The channel calibration button will run a software routine that attempts to remove any constant phase or amplitude measurement errors between the three input channels, when it is implemented. These errors are primarily caused by slightly mismatched impedances on the input channels on the PCB, which prevent the amplifiers and attenuators from perform- ing ideally. These variances cause each of the input channels to have a slightly different level of gain, which results in a fixed error factor between channels. Similarly, the digital attenuators do not attenuate in exact 0.5 dB steps, so at different levels of attenuation the amplitude error may vary. Also, during testing, a very small amount of phase error was measured depending on the attenuation setting for the digital attenuators.
41 CHAPTER 6
Testing and Performance
6.1 Cavity Simulation Circuit
SRF cavities are rarely available for testing purposes, so I built a test circuit to simulate a cavity with a known transfer function and known disturbances. A block diagram of the simulation circuit is shown in Figure 6.1. The test circuit has inputs for a disturbance signal, tuner signal from the LLRF controller, and the RF output from the LLRF controller.
The disturbance signal and tuner signal are added together with a fixed DC voltage offset after the tuner signal passes through a transfer function block. The transfer function is designed to simulate a mass-spring model of the tuner arm. The DC offset is necessary to prevent the simulated disturbance signal from changing signs before it is multiplied with the RF signal, since a sign change would result in a 180◦ jump in phase of the output signal. In a real cavity, the disturbances cause the cavity resonant frequency to shift away from the driving frequency, in both amplitude and phase error. The phase error is typically used for disturbance identification, because it is relatively large compared to the amplitude error. The changes in phase cannot be easily modeled in a test circuit, so the test circuit simply performs amplitude modulation by multiplying the RF signal with the sum of the disturbance and tuner signals and the amplitude error is used for disturbance identification.
42 Figure 6.1. Block diagram of circuit used for cavity simulation. The two transfer functions are replaceable RC networks.
After modulation, the RF signal passes through another transfer function block before being amplified and sent back to the LLRF controller.
In order for the controller to perform the adaptive feedforward algorithm described in
Section 4.2, it must be able to accurately calculate the phase response of the cavity. To test this, several different transfer function models were placed in the circuit, and MATLAB was used to calculate the phase response of the system. Each transfer function module consists of an RC network as shown in Figure 6.2.
By defining x1 as the voltage across capacitor C1 and x2 as the output voltage, we can write the circuit’s state equations [25]:
u − x1 x1 − x2 x˙1 = + (6.1) C1R1 C1R2
43 Figure 6.2. Each of the transfer function blocks is made up of a replaceable RC network.
x1 − x2 x˙2 = (6.2) C2R2
y = x2 (6.3)
The state model is then:
R1−R2 −1 −1 C1R1R2 C1R1 C1R1 x˙ = x + u (6.4) 1 −1 0 C2R2 C2R2
y = 0 1 x (6.5)
This leads to a transfer function of:
1 H (s) = 2 (6.6) C1C2R1R2s + (C1R1 +C2R1 +C2R2)s + 1
Using this information, MATLAB can calculate the ideal phase response of the ampli- tude error of the circuit, which can then be compared to the phase response of the amplitude
44 error as calculated by the LLRF controller. The LLRF controller calculates the phase re- sponse of the amplitude error signal by slowly sweeping its fast tuner output from 0 Hz to
1 kHz. For each frequency, it records the incoming RF amplitude at four points, spaced
90 degrees apart, from which it can calculate the phase and magnitude response. During cavity sweep, there is assumed to be no disturbance and ωT is much smaller than ωRF , so the circuit’s output can be approximated as:
VOut = AT sin(ωT )G1 ( jωT ) +VO f f set ARF sin(ωRF )G2 ( jωRF ) (6.7)
Since ωT is much smaller than ωRF , the tuner component can be viewed as a scaling con- stant on the RF signal, and the tuner input will cause a sinusoidal error in the amplitude of the RF output. Therefore, for the test circuit, GT (Figure 4.2) can be approximated by
G1(s). Figures 6.3 and 6.4 show the ideal amplitude and phase response and the response calculated by the LLRF controller in the presence of the disturbances it will attempt to cancel. The phase plots match very closely, with the calculated plot staying within approx- imately five degrees of the ideal plot for frequencies below 500 Hz and within ten degrees for frequencies between 500 Hz and 1,000 Hz. The saw tooth pattern seen in the plot cre- ated by the LLRF controller starting at about 600 Hz is an artifact of algorithm used to calculate the phase. To speed processing and make sure there were no errors in the original implementation of the phase calculation algorithm, the algorithm was implemented using integer intermediate values, instead of floating point variables. Although the phase calcu- lation is accurate enough for the AFC algorithm to work, it can be made more accurate by using more precise intermediate results or filtering the output data to produce a smoother
45 Figure 6.3. Ideal magnitude response (top) and magnitude response calculated by LLRF controller (bottom).
curve; so later versions of the DSP code will be modified to do so.
After verifying that the cavity transfer function calculation was accurate enough to work with the AFC algorithm, the controller was tested with known disturbances. In testing, the
AFC algorithm was able to reduce the effect of disturbances to the noise floor with an appropriate value of the adaptation gain γ, regardless of the amplitude of the disturbance.
Increasing the value of γ improves the effectiveness of the AFC algorithm by allowing the estimated parameters to converge faster to the actual parameters (Figure 6.5), but setting γ
46 Figure 6.4. Ideal phase response (top) and phase response calculated by LLRF controller (bottom).
47 too high can cause instability, so its value must be chosen carefully. The spikes seen at 189
Hz, 378 Hz, and 568 Hz are caused by some unterminated digital connections within the controller. Those connections will be fixed in the next update of the circuit board.
48 No disturbance cancellation.
1 AFC cancellation at 60 Hz, γ = 0.125. Disturbance power is reduced to 16 of its original level.
1 AFC cancellation at 60 Hz, γ = 0.25. Disturbance power is reduced to 64 of its original level.
Figure 6.5. FFT of RF input with 60 Hz sinusoidal disturbance. Because the magnitude of the disturbance is large, its third harmonic is also present.
49 CHAPTER 7
Conclusion and Future Work
7.1 Conclusion
A new prototype LLRF controller has been created for use with high-Q superconducting cavities. In addition to the digital PID amplitude and phase control provided by typical
LLRF controllers, the new prototype implements an adaptive feedforward cancellation al- gorithm for microphonics mitigation with a piezoelectric tuner, and is the first LLRF con- troller to do so. Microphonics mitigation is necessary, because the narrow bandwidth of high-Q cavities allows microphonics to perturb the resonant frequency of the cavity too far for the PID feedback control alone to work.
Testing was done to make sure that the AFC control does not conflict with the LLRF amplitude and phase control, and there were no conflicts during normal operation. How- ever, during PID tuning the AFC can make it difficult to select the correct parameters.
During PID tuning, the RF output steps between two set points so the system response can be seen. If the AFC control is enabled when tuning, it also tries to compensate for the error, since the step function has components at all frequencies. The result is what appears to be some ringing after each set point transition. Although steps were taken in software to minimize the effect on the AFC algorithm, it is currently not possible to completely prevent
50 the change in output set point from affecting the AFC algorithm.
7.2 Required Changes
Although the LLRF controller was shown to work in testing, there are several modifications that need to be made to the DSP daughter card before the module is ready for production.
The biggest problem with the current version of the circuit board is that it runs very hot.
The DSP and its voltage regulator are both designed to dissipate heat through the circuit board. However, the circuit board is simply not large enough to get enough airflow for the heat generated. On the prototype, heat sinks were added to the DSP and the voltage regulator to attempt to solve the problem. The heat sink on the DSP was able to sufficiently cool it, but there is not enough surface area on the top of the voltage regulator to add a sufficiently large heat sink to it. In order to solve the cooling problem, the DSP daughter card must be increased in area, and the voltage regulator should be moved farther from the
DSP, since those two ICs produce almost all of the heat on the board.
In addition to the cooling problem, there were several minor errors made in the board schematic that made their way into the board layout. There were three pull-up resistors on the control lines for the DSP external memory interface that were mistakenly connected to ground instead of +3.3 V. Also, when programming the EEPROMs, it was found that it is better to let the software check the status of the EEPROMs during program and erase than to use the hardware control pins, so the busy pins should be disconnected from the
EEPROMs.
Finally, DIP switches should be added to make it easier to change DSP hardware set-
51 tings. Switches should be added for the following settings: DSP clock multiplier, JTAG mode, DSP endian mode, DSP boot mode, SDRAM clock select, EEPROM and FPGA clock select, and default program.
7.3 Future Hardware Upgrades
During software development, several potential changes to the hardware were identified that would help improve data flow within the module as well as make sure that parts are available in the future. The FPGA currently used in the module is a Xilinx Spartan-II, which is an older model, which is not as fast and does not have as much logic as the newer
Spartan-3 and Spartan-3E FPGAs. The Spartan-II will likely be phased out in the next few years, so it will be a good idea to migrate to the newer model.
Several signal routing changes could be made to the module to improve device utiliza- tion. There is an 8-pin DIP switch used to set the device address. In the current version, it is connected through the FPGA to the host processor. By connecting the DIP switch di- rectly to the host processor, 16 FPGA I/O pins would be freed. By connecting these pins to the DSP to change its interface from 16 bits to 32 bits wide, the data throughput would be doubled. Currently, the DSP and host processor both have a free serial port, which could be connected to each other. The addition of a second serial connection between the de- vices would allow the large block data transfers (program download, FFT plot, etc.) and the control commands to be sent on different serial ports. Doing so would remove the lag in response to user commands during block transfers, since the host processor would no longer have to wait until the block transfer finishes to send the command.
52 The pass band of the RF output filter must be chosen based on the operating frequency range of the module. The current version of the RF circuit board accepts filters in the
YY161 surface-mount package, but for higher frequencies there is not a very good selection of available filters. As a result, for some applications, it is necessary to add an external filter on the output to get adequate filtering. By changing the board layout to accept filters in a more common package, the need for external filters can be eliminated for the whole range of frequencies the module is designed to work with (2 MHz to 1.5 GHz).
7.4 Future Software Upgrades
In future versions of the LLRF control, the PID feedback control will be combined with a feedforward control to improve the system response. This will allow higher gain PID parameters to be used to improve accuracy without affecting the stability of the system.
In addition, integrator anti-windup will be implemented to prevent the system output from saturating.
53 APPENDICES
54 APPENDIX A
FPGA Implementation of a CORDIC
Algorithm
/********************************************************************/ /* CORDIC section (written in Verilog) */ /* */ /* A 16-bit CORDIC routine is used to convert sampled I/Q values */ /* for each input channel to phase/magnitude (’A’ registers). A */ /* second implementation operates in the reverse direction to */ /* convert the desired output phase and magnitude to I/Q (’O’ */ /* registers). */ /********************************************************************/ // Counter to keep track of stage of routine reg [3:0] ctr;
// Phase look-up table // Each bit is 360 / 65536 degrees wire [14:0] lut; wire [15:0] lutn; // Negative of look-up table assign lutn = -lut;
ROM16X1 #(.INIT(16’h8000)) lut14 (.O(lut[14]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0001)) lut13 (.O(lut[13]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0002)) lut12 (.O(lut[12]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0004)) lut11 (.O(lut[11]), .A0(ctr[0]),
55 .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0008)) lut10 (.O(lut[10]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0012)) lut9 (.O(lut[9]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h002C)) lut8 (.O(lut[8]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0056)) lut7 (.O(lut[7]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h00A6)) lut6 (.O(lut[6]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0146)) lut5 (.O(lut[5]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h028C)) lut4 (.O(lut[4]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0514)) lut3 (.O(lut[3]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h0A22)) lut2 (.O(lut[2]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h1474)) lut1 (.O(lut[1]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3])); ROM16X1 #(.INIT(16’h79DC)) lut0 (.O(lut[0]), .A0(ctr[0]), .A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3]));
// Input I and Q read from high-speed ADC reg [15:0] AI, AQ;
// Input registers written by DSP reg [15:0] Op, Oa; // Output phase and amplitude
// CORDIC outputs reg [15:0] Ap, Aa; // Input phase and amplitude reg [13:0] OI, OQ; // Output I and Q
// Intermediate values reg [15:0] AI2; reg signed [15:0] AQ2; reg [15:0] Ap2; reg signed [15:0] OI2, OQ2; reg [15:0] Op2;
// Possible values for first stage of CORDIC routines wire [15:0] AI1; wire signed [15:0] AQ1; wire signed [15:0] OQ1;
56 // Possible values for stages 2-16 of CORDIC routines wire [15:0] AI3; wire signed [15:0] AQ3; wire signed [15:0] OI3, OQ3;
// First stage depends on the sign of the input Q value assign AI1 = AQ[15] ? -AQ : AQ; assign AQ1 = AQ[15] ? AI : -AI;
// First stage depends on the sign of the input phase assign OQ1 = Op[15] ? -Oa : Oa;
// Stages 2-16 depend on the sign of the intermediate Q value assign AI3 = AQ2[15] ? (AI2 - (AQ2 >>> ctr)) : (AI2 + (AQ2 >>> ctr)); assign AQ3 = AQ2[15] ? (AQ2 + (AI2 >> ctr)) : (AQ2 - (AI2 >> ctr));
// Stages 2-16 depend on the sign of the intermediate phase value assign OI3 = Op2[15] ? (OI2 + (OQ2 >>> ctr)) : (OI2 - (OQ2 >>> ctr)); assign OQ3 = Op2[15] ? (OQ2 - (OI2 >>> ctr)) : (OQ2 + (OI2 >>> ctr)); always @(posedge clk40out) begin ctr <= ctr + 1;
// First stage: shift input +90 or -90 degrees // First stage occurs when counter = -1 if (&ctr) begin AI2 <= AI1; AQ2 <= AQ1; Ap2 <= AQ[15] ? lutn : lut; OI2 <= 16’h0000; OQ2 <= OQ1; Op2 <= Op[15] ? (Op + lut) : (Op + lutn);
// Store completed conversion values from last clock cycle Ap <= Ap2; Aa <= AI2;
// Store completed conversion values from last clock cycle OI <= OI2;
57 OQ <= OQ2; end
// stage 2-16: perform shift and update intermediate registers else begin AI2 <= AI3; AQ2 <= AQ3; Ap2 <= AQ2[15] ? (Ap2 + lutn) : (Ap2 + lut);
OI2 <= OI3; OQ2 <= OQ3; Op2 <= Op2[15] ? (Op2 + lut) : (Op2 + lutn); end end
58 APPENDIX B
DSP Daughter Board Schematics
59 +12V-12V +6V J1 DSP Power Sheet2.SchDoc 40 39 38 37 36 ROM/FPGA Interface 35 Sheet4.SchDoc 34 33 BA1 32 BA2 31 BA3 30 BA4 29 BA5 SDRAM 28 R/~W Sheet5.SchDoc 27 BD0 26 BD1 25 BD2 AECLKIN 24 BD3 23 BD4 22 BD5 21 BD6 20 BD7 19 BD8 18 BD9 BOOT_PAGE0 17 BD10 BOOT_PAGE1 16 BD11 PROG_PAGE 15 BD12 14 BD13 13 BD14 12 BD15 11 ~BCE0 10 ~RESET 9 8 Power/Clocks 7 Sheet1.SchDoc 6 5 NMI 4 ~RESETAECLKIN 3 2 S1 1 SW- CON40 SPST DSP GPIO/Serial Sheet3.SchDoc
SCLK0 PROG_PAGE DX0 BOOT_PAGE1 DR0 BOOT_PAGE0 DSPEN PL1 CLK40 1 2 3 DSPGP1 4 DSPGP2 Header 4 DSPGP3 DSPGP4 FASTTUNE
LOCKED SLOWTUNE
Figure B.1. System Overview.
60 K 1
T 3
JP SM
D
A C
D 3 1 B DV N I 2 K K 1
L T 8 4
C7 10uF
AEC JP SM
A C
DD 3 1 B DV 2 F 0 u C77 .1 R49 10 G1 H2 J6 1 0 V E E L 3 3 1 Z PL L 0 MOD MOD 0 U T 0 O 3 K K TG
0 P 4
1 1
D GN OU EOH CL CL
T 4 DS m 7 2 6 i 25M0 T C 1 CE R3 Tr F - E N 0 T I I C u S 2 3 E 0 K 3 - E I S S EX V C73 10 M E E1 C ~R NMI CL L D 3 0 D U1 TM ~R N 1 VC GND S U1 CB 1 7 DV 2 B4 H4 DD 2 4 2 AC K G 5 0 P DV 1 R3 25 2 F u 2 M 0 uF C7 10 L2 BL C75 .1 D 4 D 250K R3 CV DVDD Hz I M
5 22 23 14 15 19 18 21 16 50 NM 1 1 2 2 1 1 2 A4 B5 D6 T T T T T E E E S PG U U U U MR2 Z NS NS
8 2 1 0
0 L E E
RE NC VO VO VO VO T T T
F
20 8 R3 10
r U U U
u TG VS VS
NC e F 4
17 C6 .1
E 1 m
TO TO TO NC i
4 R 4 T 6
V C P 5 3 1 0 2 1 0 F 2. 1 1 2 2 2 P P P 1 DS u 3 Q N N N N N N N S 0 C67 10 L 0 VI VI VI VI MR SE EN GND GND GND GND GND TI TI TI 0 U6 U1 TM 0 OUT EOH M 2 3 6 8 7 1 9 0 10 11 12 13 24 C5 C6 5 A5 - 2 I 3 - V D C L 3 0 V
8 VC GN
Vout
5 Gnd +6 1 U9 CB 0 3 F D A C7 1u 21SN C7 1uF 4 2 2 G Vs P U7 1 F 2 u 9 F 0 4 1 M u C6 10 C7 .1 D L1 BL V +6 DVD
Figure B.2. Voltage regulation and clock generation.
61 U1B DSP Core CVDD A1 CVDD A26 CVDD B2 CVDD B25 CVDD C3 CVDD C24 U1A DVDD CVDD D4 DSP I/O CVDD D23 Supply U1C CVDD E5 A2 DSP GND CVDD DVDD E22 A25 A8 CVDD DVDD GND F6 B1 A19 AF19 CVDD DVDD GND GND F7 B14 B3 AF8 CVDD DVDD GND GND F20 B26 B13 AE24 CVDD DVDD GND GND F21 E7 B24 AE14 CVDD DVDD GND GND G6 E8 C2 AE3 CVDD DVDD GND GND G7 E10 C4 AD25 CVDD DVDD GND GND G8 E17 C23 AD23 CVDD DVDD GND GND G10 E19 C25 AD4 CVDD DVDD GND GND G11 E20 D3 AD2 CVDD DVDD GND GND G13 F3 D5 AC24 CVDD DVDD GND GND G16 F9 D22 AC22 CVDD DVDD GND GND G17 F12 D24 AC5 CVDD DVDD GND GND G19 F15 E4 AC3 CVDD DVDD GND GND G20 F18 E6 AB23 CVDD DVDD GND GND G21 G5 E9 AB21 CVDD DVDD GND GND H20 G22 E18 AB18 CVDD DVDD GND GND K7 H5 E21 AB9 CVDD DVDD GND GND K20 H22 E23 AB6 CVDD DVDD GND GND L7 J21 F5 AB4 CVDD DVDD GND GND L20 K5 F8 AA22 CVDD DVDD GND GND N7 K22 F10 AA19 CVDD DVDD GND GND P20 L5 F11 AA17 CVDD DVDD GND GND T7 M5 F13 AA16 CVDD DVDD GND GND T20 M6 F14 AA14 CVDD DVDD GND GND U7 M21 F16 AA13 CVDD DVDD GND GND U20 N2 F17 AA11 CVDD DVDD GND GND W7 P25 F19 AA10 CVDD DVDD GND GND W20 R5 F22 AA8 CVDD DVDD GND GND Y6 R21 G9 AA5 CVDD DVDD GND GND Y7 T5 G12 Y18 CVDD DVDD GND GND Y8 U5 G15 Y15 CVDD DVDD GND GND Y10 U22 G18 Y12 CVDD DVDD GND GND Y11 V6 H1 Y9 CVDD DVDD GND GND Y14 V21 H6 W26 CVDD DVDD GND GND Y16 W5 H21 W21 CVDD DVDD GND GND Y17 W22 H26 W6 CVDD DVDD GND GND Y19 Y5 J5 W1 CVDD DVDD GND GND Y20 Y22 J7 V22 CVDD DVDD GND GND Y21 AA9 J20 V20 CVDD DVDD GND GND AA6 AA12 J22 V7 CVDD DVDD GND GND AA7 AA15 K21 V5 CVDD DVDD GND GND AA20 AA18 L6 U21 CVDD DVDD GND GND AA21 AB7 L21 U6 CVDD DVDD GND GND AB5 AB8 M7 T21 CVDD DVDD GND GND AB22 AB10 M20 T6 CVDD DVDD GND GND AC4 AB17 N6 R20 CVDD DVDD GND GND AC23 AB19 N21 R7 CVDD DVDD GND GND AD3 AB20 N25 P21 CVDD DVDD GND GND AD24 AE1 P2 P6 CVDD DVDD GND GND AE2 AE13 CVDD DVDD AE25 AE26 TMS320C6414TGLZ CVDD DVDD AF1 AF2 CVDD DVDD AF26 AF25 CVDD DVDD TMS320C6414TGLZ TMS320C6414TGLZ
Figure B.3. DSP power connections.
62 CVDD
C1 C2 C3 C4 C9 C10 C11 C12 C13 C14 C15 C16 100uF 100uF 100uF 100uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF
U1D C17 C18 C19 C20 C21 C22 C23 C24 DSP HPI / RSV(PCI) .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF AA4 RSV (PCI_EN) R4 ~HINT R1 C25 C26 C27 C28 C29 C30 C31 C32 HCNTL1 T4 .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF HCNTL0 R3 HHWIL P1 HR T3 C33 C34 C35 C36 C37 C38 C39 C40 ~HAS R2 DVDD .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF ~HCS T1 ~HDS1 T2 ~HDS2 P4 C41 C42 C43 C44 C45 C46 C47 C48 ~HRDY J2 .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF HD31 K3 HD30 J1 HD29 K4 C49 C50 C51 C52 C53 C54 C55 C56 HD28 K2 .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF HD27 L3 HD26 K1 HD25 L4 C57 C58 C59 C60 C61 C62 C63 C64 HD24 L1 .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF HD23 M4 HD22 M2 HD21 N4 C5 C6 C7 C8 C65 C66 HD20 M1 100uF 100uF 100uF 100uF .1uF .1uF HD19 N5 HD18 N1 U1E HD17 P5 DSP RSV U1F HD16 U4 DVDD DSP RSV(TEST) HD15 (UTOPIA) U1 AB14 AF14 A3 HD14 NC NC NC U3 AC11 AF13 R6 G2 HD13 NC NC DVDD NC U2 AC12 AF12 CVDD H3 HD12 NC NC NC V4 AC13 AF10 G14 J4 HD11 NC NC CVDD NC V1 AC14 AF9 H7 K6 HD10 NC NC CVDD NC V3 AD7 AF7 N20 N3 HD9 NC NC CVDD NC V2 AD8 AE15 P7 P3 HD8 NC NC CVDD NC W2 AD9 AE12 Y13 W25 HD7 NC NC CVDD NC W4 AD10 AE11 HD6 NC NC Y1 AD13 AE10 TMS320C6414TGLZ HD5 NC NC Y3 AD14 AE9 HD4 NC NC Y2 AE8 HD3 NC Y4 AD11 AE7 HD2 10K PD NC AA1 AD12 AD15 HD1 10K PD NC AA3 HD0 W3 R39 R40 TMS320C6414TGLZ RSV (PCBE0) AD1 10K 10K RSV (XSP_CS) TMS320C6414TGLZ
Figure B.4. DSP bypass capacitors, UTOPIA port, HPI port and reserved pins.
63 F F 4 6 u u F F C8 10 C8 10 E E R R V V D 3 2.5 2.5 0 K N D F F 5 7 2 K E R3 10 0 0 P C8 .1u C8 .1u R3 10 DV SCLK DR DX DS 3 F 33 1 R2 7 8 9 0 C9 .1u V R1 R1 R1 R2 33 33 33 33 +12 2 33 7 5 8 6 R2 3 1 1 1 9 10 12 3 5 11 4 6 B B B E T V+ E F4 AF E1 D2 C1 AC9 AB1 AB1 D1 E2 E3 N -IN N +IN U OU L C U D D K N H T F F L T 7 N D D 0 1 0 0 1 0 0 0 1 E DI W E 7 T A GND V S R X X X 2 Z S A SC O T SY A AV 2 K L DR0 DR1 l K DX DX K VR N IO VR FSR FSR FS FS a A 4 G SL FA i r OU -IN +I V- CL CL T CL e 4 N U1 OP S
1 E 4 P _ F 1 2 3 4 6 E 4 P2 A B C D C 2 1 L 2 1 DS 1 C88 .1u 5 0 S T T T T C B R X S R X 2 5 2 2 B 2 U U U U A A 8 K K K K K 3 R X C 3 K MC CL CL DX FS FS CL CL CL VO VO VO VO LD EN DR2 A1 A0 V U1 DA U1 TMS 0 2 K F -1 R3 10 2 1 2 7 8 3 0 2 E 1 14 13 16 15 R 33 D AF AB1 AC2 AB3 AC1 AB2 AC8 AA V R2 AC1 AB1 D 5 K 2. R31 10 DV 4 5 6 R1 33 R1 33 R1 33 4 5 5 8 4 1 D N W GN O K N O D CS L T AI K SD U G SC D SH 1 4 F 5 2 5 1 V S 3 VRE FS VDD GND P 2 U1 TL VOUT NC +V U1 TM 7 6 2 3 K 1 2 3 3 10 R1 3 .1uF C8 1 9 F C8 .1uF C7 .1uF E D D F 2 R D D u V C8 10 5 DV DV F 2. 0 u C8 10
Figure B.5. DSP serial connections.
64 DVDD U1G J2 DSP JTAG 1 2 AB16 TMS 3 4 AE19 TDO 5 6 AF18 TDI 7 8 AF16 TCK 9 10 AB15 ~TRST 11 12 AC18 EMU11 13 14 AD18 EMU10 AE18 JTAG Header EMU9 AC17 EMU8 AF17 EMU7 AD17 EMU6 AE17 R12 EMU5 AC16 1K EMU4 AD16 EMU3 2 AE16 DVDD EMU2 AC15 3 1
EMU1 C B A AF15 EMU0 JP2 TMS320C6414TGLZ R11 SMT 33OHM 1K
2 DVDD R27 BOOT_PAGE1 3 1 33 C B A JP1 R28 BOOT_PAGE0 SMT 33OHM 33 R41 R29 LOCKED PROG_PAGE U1H R42 33 33 DSPGP1 DSP GPIO AF6 G3 33 GP0 GP15 AE6 F2 GP1 GP14 R43 AD6 G4 DSPGP2 GP2 GP13 AC6 J3 33 GP3 GP12 AF5 F1 GP4 GP11 R44 AE5 L2 R24 R25 R26 DSPGP3 GP5 GP10 AD5 M3 10K 10K 10K 33 GP6 GP9 R45 AF4 AE4 DSPGP4 GP7 CLKS2/GP8 33 TMS320C6414TGLZ R46 CLK40 33
Figure B.6. DSP JTAG emulation port and general purpose port.
65 U1I AF24 DSP EMIFA H25 AED63 AECLKIN AF23 L26 AED62 ~ACE3 AE23 K23 AED61 ~ACE2 AECLKIN AE22 K24 AED60 ~ACE1 AD22 M22 AED59 ~APDT AF22 N22 AED58 ~AHOLDA AD21 V23 AED57 ~AHOLD AE21 P22 AED56 ABUSREQ AC21 J23 AED55 AECLKOUT2 AF21 R22 AED54 ~ASOE3 AD20 L22 AED53 AARDY AE20 AED52 AC20 K25 4 13 ~ACE0 AED51 ~ACE0 AF20 T23 AED50 ~ABE7 AC19 T24 AED49 ~ABE6 AD19 R25 AED48 ~ABE5 W24 R26 AED47 ~ABE4 W23 M25 6 11 ~ABE3 AED46 ~ABE3 Y26 M26 7 10 ~ABE2 AED45 ~ABE2 Y23 L23 8 9 ~ABE1 AED44 ~ABE1 Y25 L24 7 10 ~ABE0 AED43 ~ABE0 Y24 J26 3 14 SDCLK AED42 AECLKOUT1 AA26 J25 2 15 ~AARE AED41 ~AARE AA23 J24 1 16 ~AAOE AED40 ~AAOE AA25 K26 5 12 ~AAWE AED39 ~AAWE AA24 L25 6 11 SDCKE AED38 ASDCKE AB26 AED37 AB24 T22 AED36 AEA22 AB25 V24 AED35 AEA21 AC25 V25 AED34 AEA20 AC26 V26 AED33 AEA19 AD26 U23 AED32 AEA18 AD31 9 8 C26 U24 AED31 AEA17 AD30 10 7 D26 U25 7 10 AA16 AED30 AEA16 AD29 11 6 D25 U26 6 11 AA15 AED29 AEA15 AD28 12 5 E25 T25 5 12 AA14 AED28 AEA14 AD27 13 4 E24 T26 4 13 AA13 AED27 AEA13 AD26 14 3 E26 R23 8 9 AA12 AED26 AEA12 AD25 15 2 F24 R24 3 14 AA11 AED25 AEA11 AD24 16 1 F25 P23 4 13 AA10 AED24 AEA10 AD23 9 8 F23 P24 5 12 AA9 AED23 AEA9 AD22 10 7 F26 P26 2 15 AA8 AED22 AEA8 AD21 11 6 G24 N23 2 15 AA7 AED21 AEA7 AD20 12 5 G25 N24 1 16 AA6 AED20 AEA6 AD19 13 4 G23 N26 8 9 AA5 AED19 AEA5 AD18 14 3 G26 M23 3 14 AA4 AED18 AEA4 AD17 15 2 H23 M24 1 16 AA3 AED17 AEA3 AD16 16 1 H24 AED16 AD15 9 8 C19 B21 8 9 AD7 AED15 AED7 AD14 10 7 D19 C21 7 10 AD6 AED14 AED6 AD13 11 6 A20 A22 6 11 AD5 AED13 AED5 AD12 12 5 D20 C22 5 12 AD4 AED12 AED4 AD11 13 4 B20 B22 4 13 AD3 AED11 AED3 AD10 14 3 C20 B23 3 14 AD2 AED10 AED2 AD9 15 2 A21 A23 2 15 AD1 AED9 AED1 AD8 16 1 D21 A24 1 16 AD0 AED8 AED0 TMS320C6414TGLZ
Figure B.7. DSP external memory interface A.
66 DVDD
C100 C101 C102 C103 C104 C105 10uF .1uF .1uF .1uF .1uF .1uF
U5 DVDD ~ACE0 20 1 ~CS VDD ~AAWE 17 15 ~WE VDD ~AARE 18 29 ~CAS VDD ~AAOE 19 43 ~RAS VDD ~ABE3 59 3 DQM3 VDDQ ~ABE2 28 9 DQM2 VDDQ ~ABE1 71 35 DQM1 VDDQ ~ABE0 16 41 DQM0 VDDQ SDCLK 68 49 CLK VDDQ SDCKE 67 55 CKE VDDQ 14 75 NC VDDQ AD31 56 81 DQ31 VDDQ AD30 54 30 DQ30 NC AD29 53 57 DQ29 NC AD28 51 23 AA16 DQ28 BA1 AD27 50 22 AA15 DQ27 BA0 AD26 48 21 AA14 DQ26 A11 AD25 47 24 AA13 DQ25 A10 AD24 45 66 AA12 DQ24 A9 AD23 42 65 AA11 DQ23 A8 AD22 40 64 AA10 DQ22 A7 AD21 39 63 AA9 DQ21 A6 AD20 37 62 AA8 DQ20 A5 AD19 36 61 AA7 DQ19 A4 AD18 34 60 AA6 DQ18 A3 AD17 33 27 AA5 DQ17 A2 AD16 31 26 AA4 DQ16 A1 AD15 85 25 AA3 DQ15 A0 AD14 83 69 DQ14 NC AD13 82 70 DQ13 NC AD12 80 73 DQ12 NC AD11 79 6 DQ11 VSSQ AD10 77 12 DQ10 VSSQ AD9 76 32 DQ9 VSSQ AD8 74 38 DQ8 VSSQ AD7 13 46 DQ7 VSSQ AD6 11 52 DQ6 VSSQ AD5 10 78 DQ5 VSSQ AD4 8 84 DQ4 VSSQ AD3 7 44 DQ3 VSS AD2 5 58 DQ2 VSS AD1 4 72 DQ1 VSS AD0 2 86 DQ0 VSS MT48LC4M32B2TG-6
Figure B.8. External SDRAM.
67 5 4 3 2 1 0 W 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 ~ R/ BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BA BA BA BA BA 5 4 3 2 1 Y E BA BA BA BA BA 6 D K O 5 4 3 2 1 0 W R 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 A R5 10 ~ R/ BA ~B BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 1 0 5 K E E R5 10 16 9 16 15 14 13 12 11 10 9 16 15 14 13 12 10 11 9 AG 4 PAG P K _ R5 10 OT OT 3 BO BO 1 8 1 2 3 4 5 6 7 8 1 2 3 4 5 7 6 8 1 2 0 1 0 1 1 9 0 0 1 3 4 5 C1 B1 D7 B6 C7 A6 D8 B7 E1 E1 D1 D1 B1 E1 A1 A1 C8 A7 C9 B8 D9 B9 C1 A9 D1 B1 E1 9 8 7 6 5 4 3 2 1 0 3 5 4 3 2 1 0 2 1 E E E A Q Y D N 1 1 1 1 1 1 I E T T D D D D D D D D D D R O E L D D W D D D D D D K O A R L O A R Z A S L BE BE BE BE BE BE BE BE BE BE S OU OU O H 9 10 L BE BE BE BE BE BE C FB ~B ~B U K K I ~B H BA G ~B L L ~B T BE M C C BB ~B E 14
4 BE BE NC NC 6 C DSP 0 9 8 7 6 5 4 3 2 1 0 1 0 3 2 1 0 0 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 2 DT 3 A A A A A A A A A A A A A A A A A A A A BE BE CE CE CE CE P S ~B ~B ~B ~B ~B ~B ~B BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE U1J TM B 3 2 2 8 8 7 7 6 6 5 5 4 ~ E E12 E16 C1 C1 B1 C1 B1 C1 B1 C1 B1 C1 B1 C1 R/ D13 A13 A12 D18 A18 D17 A17 D16 A16 D15 A15 D14 A14 U3 7 2 3 4 6 5 1 2 8 7 3 4 2 1 8 4 3 7 6 6 5 5 26 15 1 E BC ~ K 9 9 R3 10 10 15 14 13 11 12 16 15 10 14 13 15 16 13 14 10 11 11 12 12 1 2 0 9 8 7 6 5 4 3 2 1 0 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 CE CE BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA ~B ~B K D R2 10 D Y 0 2 D DV K CE BCE R1 10 BAR ~B ~ 5 1 26
Figure B.9. DSP external memory interface B.
68 1 0 E E 3 uF C9 .1 PAG PAG D _ _ D OT OT DV BO BO 0 9 8 7 6 5 4 3 2 1 0 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA 7 8 18 19 20 21 22 23 24 25 17 48 1 2 3 4 5 6 37 10 9 16 14 45 7 6 5 4 3 2 1 0 1 C - A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 NC NC NC NC A1 A1 A1 A1 A1 A1 A1 A1 5A VC 1 DQ T D 00 E 4 4 3 2 1 0 T B 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 P Y W ~ 9 R/ ~E ~G ~W NC DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ ~R VSS VSS ~B U3 M2 15 26 28 11 13 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 12 46 27 47 1 7 6 5 4 3 2 1 0 CE T ~B BD BD BD BD BD BD BD BD SE E ~R Y E 2 D O 5 4 3 2 1 0 W A CE BAR ~B ~B R/~ BD1 BD1 BD1 BD1 BD1 BD1 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 32 30 44 42 40 38 35 33 31 29 11 28 26 27 46 12 45 13 43 41 39 36 34 15 1 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 P B - 1 1 1 1 1 ~E ~ ~G NC ~W ~R VSS VSS DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ T 5A R/ DQ DQ DQ DQ DQ 1 D 0 2 E DQ 3 T P C Y W A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VC ~B ~W E U2 M29 G A P 9 1 2 3 4 5 6 7 8 _ 10 16 17 48 18 19 20 21 22 23 24 25 37 47 14 0 9 8 7 6 5 4 3 2 1 0 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 PROG F BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA 2 u C9 .1 D D DV
Figure B.10. External non-volatile memory and FPGA connection.
69 BIBLIOGRAPHY
70 BIBLIOGRAPHY
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