Zero-Static-Power Nonvolatile Logic-In-Memory Circuits for Flexible

Republic of Korea gene therapy in vitro and in vivo.

Nano Research 1 DOI 10.1007/s12274-017-1449-y Nano Res

Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics Byung Chul Jang1, Sang Yoon Yang1, Hyejeong Seong2, Sung Kyu Kim3, Junhwan Choi2, Sung Gap

Im2, and Sung-Yool Choi1 ()

Nano Res., Just Accepted Manuscript • DOI: 10.1007/s12274-017-1449-y http://www.thenanoresearch.com on Jan. 03, 2017

Just Accepted

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TABLE OF CONTENTS (TOC)

Zero-Static-Power Nonvolatile Logic-in-Memory Circuits for Flexible Electronics

Byung Chul Jang1, Sang Yoon Yang1, Hyejeong Seong2, Sung Kyu Kim3, Junhwan Choi2, Sung Gap Im2, and Sung-Yool Choi1,*

1School of Electrical Engineering, Graphene/2D Materials Research Center, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea 2Department of Chemical and Biomolecular

Engineering, Graphene/2D Materials Research Center, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea Flexible nonvolatile logic-in-memory circuit enabling normally-off-computing can be implemented using pV3D3-memristor 3Department of Materials Science and Engineering, Korea array. For the first time, we experimentally demonstrate our Advanced Institute of Science and Technology (KAIST), implementation of MAGIC-NOT and -NOR gates during multiple Daejeon 34141, Korea cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized within crossbar array.

Author 1, http://mndl.kaist.ac.kr Author 2, http://ftfl.kaist.ac.kr Author 3, http://hrtem.kaist.ac.kr

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Nano Res DOI (automatically inserted by the publisher) Research Article

Zero-Static-Power Nonvolatile Logic-in-Memory Circuits for Flexible Electronics

Byung Chul Jang1, Sang Yoon Yang1, Hyejeong Seong2, Sung Kyu Kim3, Junhwan Choi2, Sung Gap Im2, and 1 Sung-Yool Choi ()

1School of Electrical Engineering, Graphene/2D Materials Research Center, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea 2Department of Chemical and Biomolecular Engineering, Graphene/2D Materials Research Center, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea 3Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea

Received: day month year / Revised: day month year / Accepted: day month year (automatically inserted by the publisher)

ABSTRACT

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we demonstrate that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-memristor array. Albeit memristive logic-in-memory circuits have been previously reported, the requirements of additional components and large variation of memristors have limited demonstrations to simple gates within a few operation cycles on only rigid substrate. Using memristor-aided logic (MAGIC) architecture requiring only memristors and pV3D3-memristor with good uniformity on flexible substrate, for the first time, we experimentally demonstrate our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within crossbar array. This research advances the development of novel

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computing architecture with zero static power consumption for battery-power flexible electronic systems.

KEYWORDS memristor, memristive logic circuit, flexible nonvolatile logic-in-memory circuit, normally-off-computing, memristor-aided logic (MAGIC) architecture

———————————— Address correspondence to Sung-Yool Choi, [email protected]

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networks, and analog circuits [17-19]. In particular, 1. Introduction the memristive logic gates can perform a nonvolatile logic-in-memory circuit, enabling normally-off Flexible electronics with a stylish form factor, such computing with the static power dissipation of 0 W as smart bands, curved TV, and so on, are now [20-22]. They furthermore enable development of an integrated in our daily lives. For realization of advanced computer architecture that is different multifunctional flexible electronic systems, various from the conventional von Neumann architecture electronic devices, such as logic gates, circuits, with its physically separate memory and logic memory, sensors, radio frequency identification circuits that suffer from the data transfer rate (RFID), and actuators have been developed onto a between the central processing unit and memory flexible platform [1-5]. In particular, developments [23]. for flexible logic and memory devices are essential A representative approach of the memristive on account of their roles of information processing, nonvolatile logic-in-memory circuit is the storage, and communication with external devices. memristor-based material implication (IMP) logic Furthermore, it is necessary to develop gate, in which resistance is used as the logical state battery-powered flexible devices with ultra-low [17,24,25]. The input and output of the logic gates are stored on memristors within the crossbar array, and static power dissipation of approximately 5 nW (Pstatic the IMP and FALSE operations (where the FALSE = VLowest,DD IDeep suspend) based on the 2015 operation always yields the logical ‘0’) form basic International Technology Roadmap for Boolean functions. This architecture, however, Semiconductors (ITRS) [6] because they have limited requires two voltage pulses to perform logic batteries and long standby periods. operations. It furthermore requires an additional Several research groups have developed a variety of resistor within each row of the crossbar, which flexible memories and logic gates based on the necessitates a complicated control circuit design and organic thin-film transistor (OTFT). However, these dissipates high power. Moreover, the output result is OTFT-based devices still face significant challenges stored not by a dedicated output memristor, but by in the development of high-density devices with one of the inputs. high performance and low power consumption. Another memristive nonvolatile logic-in-memory These challenges result from the inherent material circuit, memristor-aided logic (MAGIC) architecture, properties, incompatible lithography processes, and was theoretically proposed [26]. Unlike IMP logic, volatile complementary logic circuits [7-9]. memristors for the input and output are separated, Compared to devices based on OTFT, the and output is written to a dedicated memristor. polymer-based memristor or memristive device, Without an additional resistor, a single voltage pulse which is a nanoscale two-terminal passive device, is only required to operate logic gates. The MAGIC has been well known as a promising flexible architecture is thereby advantageous over IMP logic nonvolatile memory device owing to its simple in terms of latency and energy consumption. structure, fast switching speed, high packing density, excellent flexibility, and low operating voltage Specifically, it is 2.4 times faster than IMP logic and [10-13]. Memristors [14] and memristive devices [15] consumes 33.7% of the total energy consumed in IMP were predicted by Chua in 1971 as the fourth basic logic [27]. Furthermore, the simple architecture of circuit element, which was later demonstrated by a MAGIC can enable a memristive nonvolatile Hewlett-Packard (HP) laboratory team in 2008 [16]. logic-in-memory circuit to be reliably implemented The unique property of the memristor is the on flexible substrate over IMP logic. However, the variation of its nonvolatile resistance state depending large device-to-device variation within the crossbar on the current or voltage history across it. While array may result in the implementation of simple numerous research groups and semiconductor gates with few cycles of operation [17,22,28]. This industries have developed memristors primarily for leads to applications of IMP logic gate on only rigid memory applications, memristors can also be used as substrate and hinders MAGIC architecture from functional blocks for logic gates, artificial neuron being experimentally implemented. It is therefore

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necessary to develop a polymer-based memristor NAND logic gates within the crossbar array that array with good uniformity and reliable switching contains input memristors without external characteristics that are robust to electrical and components. This enables efficient computing within mechanical stresses on flexible substrate in order to the memory array. Moreover, we experimentally realize a flexible electronic system with ultra-low demonstrated that only five memristors can perform static power consumption via MAGIC architecture. a half adder, thus demonstrating the feasibility of the Recently, we developed a memristive nonvolatile logic-in-memory circuit for poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) complex integrated circuits on flexible substrate. (pV3D3)-based unipolar memristor array fabricated via initiated chemical vapor deposition (iCVD) with 2. Results and discussion a solvent-free process on a flexible substrate [29]. The pV3D3-memristor appears very attractive compared Figure 1a schematically illustrates the to other polymer-based flexible memristors on pV3D3-memristor with an 8 8 array on a PES account of its reliable switching characteristics substrate. The pV3D3-memristor consists of a Cu top without a passivation layer, as well as its superior electrode (TE), pV3D3 films as material for the mechanical stability, good uniformity in terms of memristor (its chemical structure is shown in the device-to-device distribution, and compatibility with Figure 1a inset with the green dotted line), and an Al photolithography technology on flexible substrate. bottom electrode (BE). As depicted with the orange These characteristics result from the mechanically dotted line in the Figure 1a inset, the and electrically robust, highly uniform, and pV3D3-memristor operates with a Cu filament, outstanding chemically stable pV3D3 thin film whose formation and rupture inside the pV3D3 deposited via a solvent-free iCVD process. In material induces the low resistance state (LRS) and particular, because these outstanding characteristics high resistance state (HRS), thereby indicating of pV3D3-memristor on flexible substrate are logical ‘1’ and ‘0,’ respectively [29]. The inset with the essential factors for enabling compact and reliable black dotted line of Figure 1a shows that the nonvolatile logic-in-memory circuits, the pV3D3-memristor array can realize basic Boolean pV3D3-memristor array shows considerable functions, such as NOT, NOR, OR, AND, and NAND potential for nonvolatile logic-in-memory circuits on operations, as will be discussed below in more detail. flexible substrate. Figure 1b presents a photograph of the fabricated In this study, we experimentally realized the flexible pV3D3-memristor array on PES substrate. pV3D3-memristive nonvolatile logic-in-memory The inset displays a magnified optical image of the circuits, thereby enabling static power consumption pV3D3-memristor array with a unit memristor cell of 0 W on flexible polyethersulfone (PES) substrate area of approximately 5㎛ 5㎛. This area of the using only the theoretically proposed MAGIC pV3D3-memristor fabricated via a photolithography architecture. Unlike existing reports on memristive technique is relatively smaller than that of nonvolatile logic-in-memory circuits with few polymer-based devices fabricated through a shadow operation cycles on rigid substrate, we demonstrated mask. It thus indicates the feasibility for realization that the basic Boolean functions were reliably of flexible devices with high density. As shown in implemented on flexible substrate during multiple Figure 1c, the uniform and thin (~20 nm) pV3D3 film cycles, and even under bent conditions, at the between Cu TE and Al BE was confirmed via a bending radius of 3.8 mm. This achievement resulted cross-sectional high-resolution transmission electron from the reliable switching performance microcopy (HRTEM). It demonstrates good characteristics that are robust to electrical and uniformity of the pV3D3 film characteristic arising mechanical stresses, the good uniformity of the from gas-phase polymerization of the iCVD process. memristor array, and the simple MAGIC architecture. Figure 1d shows a current–voltage (I-V) curve of a To the best of our knowledge, this demonstration is typical pV3D3-memristor measured with a voltage the first successful one of its kind. Consequently, we sweeping mode under air environment. After a succeeded in realizing NOR, NOT, OR, AND, and

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forming process with high voltage and a compliance When the voltage sweep was applied to the Cu TE current of 10 A, the resistance of the from 0 to 3 V with compliance current, the current pV3D3-memristor could be reproducibly switched abruptly increased at approximately 3.0 V, which from LRS to HRS, or vice versa. The was designated as the set voltage. This SET process pV3D3-memristor showed a typical unipolar occurs by the electrochemical reaction, enabling resistive switching behavior, where both SET and formation of Cu filaments into pV3D3 film [29]. RESET processes were independent of the voltage Afterward, by re-sweeping the applied voltage polarity. without compliance current, the current rapidly

Figure 1. (a) A schematic illustration of pV3D3-memristor with an 8 8 crossbar array on a plastic substrate. The inset with the orange dotted line shows the logical states of the pV3D3-memristor; the inset with the green dotted line displays the molecular structure of pV3D3, and the inset with the black dotted line depicts the feasible logic gates using the pV3D3-memristor. (b) A photograph of a flexible pV3D3-memristor on a PES substrate. The inset shows a magnified optical image of the flexible pV3D3-memristor array (scale bar: 20㎛). (c) Cross-sectional HRTEM image of the flexible pV3D3-memristor. (d) I-V characteristics of the pV3D3-memristor. (e) Cycling endurance and retention characteristics of the pV3D3-memristor.

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decreased at approximately 0.5 V, which was defined filaments. The pV3D3-memristor had a wide as the reset voltage. This RESET process results from memory window above the 107 at 0.2 V reading the rupture of Cu filaments by Joule heating arising voltage, which corresponded to the ratio of HRS to from the high currents flowing through the Cu LRS.

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As shown in Figure 1e, pV3D3-memristor exhibited

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stable retention times for 105 s under air and a wide

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memory window above 107 without noticeable

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degradation during cycling endurance tests via the

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DC sweep mode and the repeated pulse voltages

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(Figure S1). Furthermore, the pV3D3-memristor

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array showed good uniformity in terms of

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device-to-device distributions of forming voltage and

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resistance of virgin devices (not electroformed)

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(Figure S2). This good uniformity of the

Figure 2. (a) Schematic of logic-in-memory operations within the crossbar array via the MAGIC method. (b) The MAGIC-NOT gate within the crossbar array and its equivalent circuit. The logic gate consists of an input memristor and an output memristor. (c) Experimental results of the MAGIC-NOT gate during 50 cycles. (d) MAGIC-NOR gate within the crossbar array and its equivalent circuit. The logic gate consists of two input memristors and an output memristor. (e) Experimental results of the MAGIC-NOR gate for all input memristor combinations during 50 cycles.

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pV3D3-memristor array resulted from the highly specific combination of input memristors, the logical uniform pV3D3 films, as shown in Figure 1c. state of the initialized output memristor can be However, in the solution-processed polymer-based changed during application of V0. memristors, it was challenging to achieve good Because voltage drop across the output memristor uniformity on account of the residual solvent or during application of V0 should be sufficiently high pinhole formation in thicknesses below several to switch its logical state, it is necessary to choose hundred nanometers of polymer film. Therefore, the voltage V0 with a sufficient margin, which includes a reliable switching performance and good uniformity reset voltage cycle-to-cycle variation and of the pV3D3-memristor array fabricated via the device-to-device variation (Figure S3). Thus, for solvent-free iCVD process made the convenience of measurement, we selected 2 V as the pV3D3-memristor array desirable for reliable pulse voltage V0 with a pulse width of 5 ms. The memristive nonvolatile logic-in-memory circuits on following logic operation employed this value of flexible substrate. voltage as V0. Figure 2 illustrates the operation of NOT and NOR We previously reported that the switching speed for gates via the MAGIC architecture. As schematically the reset process is 500 ns in the pV3D3-memristor illustrated in Figure 2a, the logic gates are realized without device process optimization [29]. Note that using the information stored in memristors on the the feasible switching speed of the memristor is 85 ps crossbar array, thereby enabling the logic-in-memory [30]. Therefore, the switching speed of the operation. The logic operation of MAGIC works via pV3D3-memristor can possibly be improved by two sequential steps. The first step initializes the scaling the pV3D3thickness or by a specifically output memristor to logical ‘1.’ In the second step, designed structure with the transmission line [30]. voltage V0 is applied across the memristors for logic Accordingly, low energy consumption per logic operation, as shown in Figures 2b and d. For a operation and fast logic-in-memory operations with

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the pV3D3-memristor would be enabled. applying voltage V0. In the condition in which both Figure 2b presents a schematic of the MAGIC-NOT input memristors are logical ‘0,’ the voltage drop gate within a crossbar array and its equivalent circuit. across the output memristor is lower than its reset The MAGIC-NOT gate consists of an input voltage by the voltage divider, resulting in the memristor and an output memristor, which are output memristor initial logical ‘1.’ However, for all connected in series with an opposite polarity. The other input combinations (input 1, input 2: 01, 10, 11), NOT gate was realized in two steps. The output the output memristor voltage is higher than its reset memristor was initialized into a logical ‘1,’ followed voltage, thus switching output memristor to logical by application of voltage V0 at the input memristor. ‘0’. The applied voltage formed the voltage divider Figure 2e shows that the reliable MAGIC-NOR between the input and output memristors, leading to operation using the pV3D3-memristor during the 50 a change in the state of the output memristor cycles is guaranteed. Most reported memristive logic depending on the input memristor state. For the case operations via IMP logic have shown limited in which the input memristor was logical ‘1,’ the experimental results for a few cycles of operations, voltage drop across the output memristor was higher which may have been on account of the memristor than its reset voltage. Hence, the output memristor device-to-device variation [17,22,28]. Therefore, state was changed to the logical ‘0.’ reliable multi-cycle operations of MAGIC-NOT and On the other hand, in the case of the input -NOR gates benefit from the reliable memristor logical ‘0,’ the applied voltage V0 dropped pV3D3-memristor array with highly uniform and mainly across the input memristor. This did not electrically robust pV3D3 film. change the output memristor state. Thus, the output It should be noted that, the states of the output memristor maintained the logical ‘1.’ We memristors in our study exhibited broad implemented the MAGIC-NOT operation using the distributions during the operation of NOR and NOT pV3D3-memristor during 50 cycles, as shown in gates via the MAGIC architecture. These Figure 2c. distributions may have been related to the state drift The MAGIC-NOR gate can additionally be phenomenon [23] and the variations of the ruptured implemented within a crossbar array, as shown in filament path length [31] during the MAGIC Figure 2d. The two input memristors are connected operation. However, the output memristors after in parallel and linked in series with an output MAGIC operations showed a wide memory window memristor. As in the NOT operation, two execution above 106 between states of logical ‘1’ and ‘0.’ This steps are required in the NOR operation. In the first result was on account of the pV3D3-memristor execution, the logical ‘1’ is written at the output inherent high on/off ratio, which enabled the reliable memristor. The second execution induces the sensing operation of the output memristor logical conditional logic operation of output memristor by state.

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After NOT and NOR operations, the output

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memristor state showed stable retention times for 104

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s (Figure S4). Such a nonvolatile characteristic of the

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pV3D3-memristive logic gates can effectively

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suppress the static power dissipation compared with

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complementary logic circuits, which suffer from the

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sub-threshold leakage current of transistors, because

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no need exists for supplying voltage to maintain the

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output logical state [21,22,32]. Therefore, the

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pV3D3-memristive logic gates performed the

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normally-off computing with the static power

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consumption of 0 W, thereby achieving the static

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power consumption target of battery-powered

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devices reported in the 2015 ITRS [6]. In addition, the

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output memristor nonvolatile characteristic enabled

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its state to be used as an input for the other logic gate,

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which indicates its feasibility for the cascade logic

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Figure 3. (a) Schematic of the MAGIC-OR gate within the crossbar array. The logic gate is linked in series with a MAGIC-NOR gate and a MAGIC-NOT gate. (b) OR gate symbol and its truth table. (c) Experimental results of the MAGIC-NOR gate. (d) Schematic of the MAGIC-AND gate within a crossbar array. The logic gate is linked in series with two MAGIC-NOT gates and an MAGIC-NOR gate. (e) AND gate symbol and its truth table. (f) Experimental results of the MAGIC-AND gate. (g) Schematic of the MAGIC-NAND gate within a crossbar array. The logic gate is sequentially linked in series with two MAGIC-NOT gates, a MAGIC-NOR gate, and a MAGIC-NOT gate. (h) NAND gate symbol and its truth table. (i) Experimental results of the MAGIC-NAND gate. operation required in functionally complete logic

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circuits. memristor of MAGIC-NOR. Figure 3c shows that the Using the theoretically proposed MAGIC MAGIC-OR gate was successfully implemented with architecture, additional logic gates were designed the sequential operations. with the aid of the external memristors located The MAGIC-AND operation was additionally outside the active input memristors array [26]. In performed in three sequential steps, as shown in contrast, we designed the basic Boolean functions, Figures 3d-f. First, the memristors were initialized in such as OR, AND, and NAND gates, via the preparation for the MAGIC operation. Second, the appropriate network of NOT and NOR gates MAGIC-NOT operations were implemented for renowned as the universal logic gate, inside the input memristors A and B. To complete the active crossbar array that included input memristors. MAGIC-AND operation, the two output memristors This approach enabled more efficient data of the MAGIC-NOT operation were used as the processing than the architecture that employs input memristors of the MAGIC-NOR operation. external components. After the MAGIC-NOR operation, the MAGIC-AND

Figure 4. (a) Schematic of the MAGIC-NOT gate within the crossbar array under a bent condition. The inset shows a photograph of an I-V measurement being performed under a fixed condition. (b) Experimental results of the MAGIC-NOT gate under the bent condition. (c) Schematic of MAGIC-NOR gate within the crossbar array under the bent condition. (d) Experimental results of the MAGIC-NOR gate for all input memristor combinations under the bent condition.

Using the same operation scheme depicted in gate was completely achieved, as shown in the Figure 2, the additional MAGIC logic gates were measurement results of Figure 3f. realized (Figure 3). The MAGIC-OR gate was The schematic and illustration of the realized in three steps (Figures 3a-c). First, the MAGIC-NAND operation are shown in Figures 3g-i. initialization of memristors (logical ‘1’ for the output The first execution step was the initialization of the memristor and the input values for the input memristors. Next, input memristors A and B were memristors) was necessary for the MAGIC operation. used for the MAGIC-NOT operation. The Second, the MAGIC-NOR operation with input MAGIC-NOR operation was performed with the memristors A and B was implemented and served as output memristors of the MAGIC-NOT operation. the input for the next step. Third, we implemented For finalization of the MAGIC-NAND operations, the MAGIC-NOT operation with the output the output memristor of the MAGIC-NOR operation

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was used as the input memristor of the MAGIC-NOT consumption of 0 W in the flexible electronic system. operation. The measurement results of Figure 3i To confirm the operation of flexible memristive show the perfect operation of the MAGIC-NAND logic circuits under mechanical deformation, a gate. bending test was carried out for the implementation We therefore demonstrated that the of MACIC-NOT and -NOR gates. We previously pV3D3-memristor array on flexible substrate can reported that our pV3D3-memristor showed reliable perform the logic-in-memory operation by switching characteristics at the bending radius of 3.8 implementing basic Boolean functions, such as NOT, mm [29]. Hence, the MAGIC-NOT and -NOR NOR, OR, AND, and NAND gates, within the operations were performed at the bending radius of crossbar array. Although the initialization process of 3.8 mm. MAGIC-NOT (Figure 4a and b) and -NOR output memristor can cause the long latency in gates (Figure 4c and d) were implemented under a pV3D3-memristive nonvolatile logic-in-memory bent circumstance without significant degradation. circuit, more memristors including output and Furthermore, after the repeated bending over 1000 intermediate memristors can be initialized cycles at the bending radius of 3.8 mm, MAGIC-NOT simultaneously to lower the latency [27]. This and -NOR gates were successfully realized (Figure strategy can eliminate the requirement for multiple S5). The outstanding mechanical robustness of the intermediate initializations, but increasing the pV3D3-memristive logic gates benefitted from both utilized area. Therefore, any memristive logic circuits the elastic nature of the hexagonal siloxane network can be optimized for the latency and area constraints of the pV3D3 film [33] and the memristor device of the application. We believe that the characteristics with a nanometer-scale vertical pV3D3-memristive nonvolatile logic-in-circuits are channel. very promising not only for implementing the When an external strain is applied to a device, advanced computing architecture to solve the von tensile or compressive strain primarily occurs in a Neumann bottleneck, but also for achieving lateral direction. In conventional FETs based on normally-off computing with static power lateral active channels, the external strain applied to

Figure 5. (a) Schematic for realization of a half adder within the crossbar array. (b) Circuit schematic of the half adder using a combination of NOT and NOR gates, and its truth table. (c) Experimental results of the half adder using five memristors within a crossbar array. (d) Comparison table for a MOSFET and the memristor device count required for the logic gates and half adder. 40

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the channel induces band structure modifications, Figure 5d shows the number of metal-oxide resulting in the change of mobility of FETs [34]. semiconductor field-effect transistors (MOSFETs) However, in the case of a memristor device operated and memristors required for implementing the logic with a metal filament, the metal filament with a gates and adder circuit. Considering that the nanometer-scale vertical channel is minimally memristor size was smaller than that of the transistor, vulnerable to the magnitude and direction of the memristive functional blocks could be fabricated external strain [35]. Owing to this robust logic on a relatively smaller area, i.e., more logic functions operation of the pV3D3-memristor against on a single chip, which can accomplish more than mechanical stress, we therefore experimentally Moore’s law without tremendous device scaling. showed, for the first time, that the memristive logic Therefore, the pV3D3-memristor shows the potential gate can work reliably under a bent circumstance, of practical applications to complex circuit designs thereby enabling the pV3D3-mermistive nonvolatile on flexible substrate for building flexible electronic logic-in-memory circuit to be suitable for building a systems with ultra-low static power consumption. flexible electronic system with ultra-low static power The memristive logic circuits via MAGIC dissipation. architecture have two advantages compared with Using the logic gates designed via MAGIC conventional complementary logic circuits. The first architecture, the basic building block of computation, is the nonvolatile logic-in-memory circuit in which such as adder logic, can be realized for the same device can work for computing and demonstration of practical application. Here, we memory functionalities. This originates from the report a half adder that consists of 1 XOR and 1 OR memristor nonvolatile characteristics. It can realize gates (Figure 5a). The half adder usually adds the the standardized logic circuits with both ultra-low two single binary digits, A and B, to calculate Sum power consumption and a short interconnection and carry out Carry (Figure 5b). The half adder can delay. This differs from the conventional be realized using 3 NOR and 2 NOT gates via five complementary logic circuits in which the length of memristors in a 1 5 crossbar array, as schematically the global interconnection in the advanced illustrated in Figures 5a and b. very-large-scale integrated circuit (VLSI) results in During operation of the half adder, the memristors an increase of both dynamic power consumption and in other rows either did not undergo the forming interconnection delay [20]. In addition, the process, or they were programmed into HRS, which nonvolatile logic-in-memory circuit can achieve the mitigated unintentional leakage currents in the static power consumption of 0 W during standby crossbar array structure. To implement the half mode because the electronic system with nonvolatile adder shown in Figure 5b, a sequence of steps was logic gates cannot suffer from the sub-threshold necessary (Figure S6). First, M1 and M2 of the leakage current. memristors were written to the input values of A and The second advantage is the sequential cascading B, and the other memristors were initialized. The operation of the memristive logic circuits. The second and third steps were involved in operating cascading operation is required for implementing a the NOT logic gates of A and B, where the output functionally complete logic, which enables all was stored into M3 and M4, respectively. Fourth, the essential functions in the arithmetic logic unit (ALU) Carry bit was acquired from M5, which was the and central processing unit (CPU). The sequential output of the NOR logic gates of M3 and M4. Fifth, cascading operation additionally enables the M3 was initialized and then processed by the NOR memristive logic circuit to occupy a much smaller logic operation with input M1 and M2. Lastly, the area for implementing the equivalent circuits Sum bit was extracted from M4, which resulted from compared with the complementary logic circuit: five the NOR logic operation with input M3 and M5. memristors compared to fourteen transistors in the The implementation stream of the half adder is case of the half adder circuit. Furthermore, while the shown in Figure S6, and the experimental results are complementary logic circuits depend on the specific given in Figure 5c. In the latter figure, the half adder gate topology to achieve a specific function, the using only five memristors is successfully achieved. memristive logic circuits enable implementation of

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the reconfigurable circuits, which can achieve any computing architecture that solves the von logic functions relying on their configuration inside Neumann bottleneck. the crossbar array. Therefore, memristors within the limited area can realize many logic functions, which 4. Methods enables their effective implementation of the complex functions, such as the adder. 4.1 Device fabrication 3. Conclusions Flexible pV3D3-memristor, illustrated in the inset of Figure 1(a), were fabricated with crossbar In summary, for the first time, we experimentally structures. First, 60 nm-thick Al electrodes were demonstrated that mechanically deformable, patterned on PES substrate by photolithography nonvolatile logic-in-memory circuits enabling and subsequent thermal evaporation. A 20 nm-thick normally-off computing can be realized using a pV3D3 film was then deposited on the Al electrodes pV3D3-memristor array built on flexible substrate. via the iCVD reactor, as described elsewhere [36]. The working principle is based on the theoretically Device fabrication was completed by depositing the proposed MAGIC architecture. Previous reports on 60 nm-thick Cu electrode lines via memristive nonvolatile logic-in-memory circuits photolithography and subsequent thermal have shown the limitation of implementation for evaporation, perpendicular to the bottom electrodes, simple gates within a few operation cycles on only for the 8 8 cross bar array. Line widths of both top rigid substrate. On the other hand, we achieved a successful implementation of the basic elements for Cu and bottom Al electrodes were identical at about the universal logic gate, i.e., MAGIC-NOT and 5 ㎛ (the active area of memory: 5 ㎛ 5 ㎛). -NOR gates with pV3D3-memristors during multiple cycles, and even under bent conditions at a Electrochemically active copper was selected as the bending radius of 3.8 mm, resulting from high top electrode for supplying the source of the uniformity, outstanding mechanical stability, and conducting filaments, and aluminum was chosen an electrical robustness of the pV3D3 film. Other basic inert bottom electrode. Boolean functions, such as OR, AND, and NAND gates, were successfully implemented by various 4.2 Electrical characterization combinations of basic NOT and NOR gates. In order to investigate the electrical characteristics For the practical application, we demonstrated that of the fabricated devices, a bias was applied to the these combinations of MAGIC-based logic gates Cu electrode with the Al electrode grounded, via a could also be extended to an implementation of a Keithley 4200 semiconductor parameter analyzer half adder, which utilized only five memristors without any device encapsulation in air atmosphere. through the appropriate network of NOT and NOR During the SET process, the compliance current was gates. This indicated the feasibility of the set to protect the device. pV3D3-memristor array for a much more complex integrated circuit design. We believe that our research presents an importance milestone for Acknowledgements development of a battery-powered flexible This research was supported by the Global Frontier electronic system with not only static power Center for Advanced Soft Electronics (2011-0031640), consumption of 0 W, but also the advanced the Creative Research Program of the ETRI

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(15ZE1110), Wearable Platform Materials Technology transparent silicon-on-polymer based sub-20 nm non-planar 3D FinFET for brain-architecture inspired Center (WMC) funded by the National Research computation. Adv. Mater. 2014, 26 (18), 2794-2899. Foundation of Korea (NRF) Grant of the Korean [10] Hosseini, N. R.; Lee, J.-S. Resistive switching memory Government (MSIP) (2016R1A5A1009926), and based on bioinspired natural solid polymer electrolyte. ACS Samsung Research Funding Center of Samsung Nano 2015, 9, 419-426. Electronics (SRFC-MA1402-04). [11] Son, D. I.; Kim, T. W.; Shim, J. H.; Jung, J. H.; Lee, D. U.; Lee, J. M.; Park, W. I.; Choi, W. K. Flexible organic bistable devices based on graphene embedded in an Electronic Supplementary Material: Supplementary insulating poly(methyl methacrylate) polymer layer. Nano material (The cycling endurance result of Lett. 2010, 10, 2441-2447. pV3D3-memristor via the repeated pulse voltages, [12] Jeong, H. Y.; Kim, J. Y.; Kim, J. W.; Hwang, J. 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