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Mathematical Analysis of Logical Masking Capability of Logic Gates

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Mathematical Analysis of Logical Masking Capability of Logic Gates Recent Advances in Electrical Engineering and Electronic Devices Mathematical Analysis of Logical Masking Capability of Logic Gates P. BALASUBRAMANIAN*, and N. E. MASTORAKIS¶ * Department of Computer Science and Engineering S. A. Engineering College (Affiliated to Anna University) Poonamallee-Avadi Road, Veeraraghavapuram, Chennai 600 077 INDIA [email protected] ¶ Sector of Electrical Engineering and Computer Science Military Institutes of University Education, Hellenic Naval Academy Piraeus 18539 GREECE [email protected] Abstract: - In this paper, logical masking capability of commonly used logic gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR, when subject to single/multiple input faults, are analyzed from a mathematical perspective. A new metric, called Gate Error Metric (GEM) is proposed to study the extent of output error in these gates when subject to potential input fault occurrences, where less value of GEM implies good logical masking. Generic GEM equations are deduced for n-input AND/NAND/OR/NOR, and XOR/XNOR gate types. The equations reveal that with an increase in fan-in output errors tend to reduce for all types of logic gates in general. In specific, AND/NAND/OR/NOR gates have similar GEM values and these are superior compared to the GEM values of XOR/XNOR gates. Key-Words: - Logic gates; Logical masking; Modeling; Circuit analysis; Reliability; Fault tolerance 1 Introduction At the heart of any digital circuit/system lies the Nanoelectronic digital circuits and systems continue combinational or non-regenerative logic, which can to face unprecedented reliability issues [1] [2], such be implemented using logic gates, such as NOT, as atomistic fluctuations, electro-migration, hot- AND, NAND, OR, NOR, XOR, and XNOR. This carrier effects, negative bias temperature instability, work critically analyzes the logical masking ability and a plethora of technological, process-related, of diverse logic gates mentioned hitherto, given the metrology and other manufacturing defects, which possibility of potential input fault occurrences. were witnessed only remotely in the age of Logical masking refers to the ability of a logic gate microelectronics. Emerging device technologies [3] to tolerate faults occurring on its inputs on account such as carbon nanotube, resonant tunneling device, of its inherent nature/functionality. In effect, this nano-array, magnetic logic circuits, spin-transistors, work builds upon research published earlier [5] – quantum dot cellular automata, bio- and molecular [7], which analyzed the error resiliency of standard electronics are currently under active investigation and complex logic gates by assuming their non- to analyze whether some of them could indeed deterministic behavior in the presence of become alternatives to bulk CMOS, which remains probabilistic input errors. However, this work is as the undisputed technology of choice and has distinguished in that real binary inputs are dealt indeed been the lifeblood of semiconductor industry with, and the likelihood of all potential input faults for well over 50 years. In this backdrop, the ITRS (single/multiple) is duly taken into account. [4] has projected design-for-reliability (including, The rest of this paper is organized as follows. fault-tolerant design) as a grand challenge for the Section 2 briefly discusses the functionality of nanoelectronics era, and has pointed out that the AND/NAND, and OR/NOR logic gates, followed issue of reliability should be addressed at all aspects by a derivation of their generalized gate error metric of the design technology in order to cope with (GEM) expression. A similar task is performed in parametric variations that have become the order of the context of XOR/XNOR gate types in Section 3, the day in modern semiconductor electronics. where XOR and XNOR gates functionality is succinctly described and the generalized GEM ISBN: 978-1-61804-266-8 144 Recent Advances in Electrical Engineering and Electronic Devices equation is derived. Section 4 provides comparison resulting in an erroneous output of 1, and thus the of GEM values corresponding to various logic gates fault is said to be revealed. This is because the ON- for fan-in ranging from 2 to 4 inputs. Finally, the set of AND3 is 1, while its OFF-set is equal to 7. conclusions are given in Section 5. Thus, in general, as long as single or multiple faults do not force the inputs of a gate to move from its ON-set to OFF-set or vice-versa, no output error 2 Derivation of GEM Expression for will occur, and the faults would be logically AND/NAND/OR/NOR Gate Types masked. On the contrary, any fault that causes a movement of gate inputs from its ON-set to OFF-set Functionality of standard logic gates is common or vice-versa will tend to corrupt the output, and knowledge. However, it is briefly reiterated here for therefore it becomes exposed. Therefore, the reference. The AND gate produces a binary output number of potential output errors likely due to a of 1, if all its inputs are 1 ; otherwise it outputs a ’s movement of inputs from OFF-set to ON-set of the binary 0 for any other input combination. The AND3 gate equals 7. This number would be the NAND gate produces a binary output of 1, if at least same for the reverse case as well. Hence, the one of its inputs is 0; it produces a binary output of number of potential output errors likely to manifest 0 only when all its inputs are 1. The OR gate in case of an n-input AND gate due to ON-set to produces a binary output of 1 even if one of its OFF-set and OFF-set to ON-set migrations can be inputs is 1; only when all its inputs are 0’s, it n produces an output of 0. The NOR gate outputs a given by )12(2 , based on the concept of binary 0, even if one of its inputs is 1; when all its mathematical induction. inputs are 0, the output of the NOR gate becomes 1. With respect to the primary input 000, number of From the above description, it may be construed inputs that are at a Hamming distance of 1 equals 3 that AND and NOR gates have similar ON-set 3 cardinalities of 1, while NAND and OR gates have viz. 001, 010 and 100 – given as ; this similar OFF-set cardinalities of 1. Hence, cardinality 1 of ON-set/OFF-set of all these logic gates equals 1. represents the inputs that could arise due to a single In other words, AND, NAND, OR, and NOR are fault, and there is only a single input change/fault. identical in the sense that they have a singleton ON Count of inputs that are at a Hamming distance of 2 or OFF-set [8]. In fact, this commonality resulted in the derivation of a similar GEM equation for all 3 also equals 3 viz. 011, 101 and 110 – given as ; these gates. Therefore, deduction of GEM equation 2 for just the AND gate (as a representative among this represents the inputs that could arise due to NAND, OR, and NOR gates) would be presented in double (multiple) faults, i.e. two input changes/fault. this paper, and the derivation of (similar) GEM The only input that is at a Hamming distance of 3 is equations for the remaining gates are left as an exercise to the reader. 3 111 – given as ; this represents the input that Before proceeding further, the proposed gate 3 error metric, GEM is defined. GEM is specified as the ratio of number of potential output errors arises due to a triple (multiple) fault, i.e. three input divided by the total number of potential input fault changes for this fault. As a generalization, with occurrences (i.e. fault occurring on each individual respect to an n-input binary pattern, the total number input), corresponding to distinct primary inputs. of potential input faults is calculated using the Consider a 3-input AND gate (given by AND3). principle of mathematical induction as follows, When the AND3 input is 000, its output is 0. Owing where k signifies the Hamming distance. to single or multiple fault occurrences due to transient/permanent errors [9] – [11], if the AND3 n n n input changes to 001 or 010 or 011 or 100 or 101 or 2 k 110, its output would still be retained as 0, i.e. no k1 k error occurs in the output, in spite of certain single or multiple faults occurring on the inputs, and the Given these, the generalized GEM equation for an input faults are said to be successfully concealed n-input AND/NAND/OR/NOR gate is deduced as, (logically masked) from being observed by the external environment. Only when the AND3 input becomes faulty as 111, its output gets corrupted ISBN: 978-1-61804-266-8 145 Recent Advances in Electrical Engineering and Electronic Devices n )12(2 for fan-in ranging from 2 to 4 inputs, which are GEMAND/NAND/OR/NOR = (1) shown in Figure 1. Note that modern ASIC standard n n n cell libraries do not feature AND/NAND/OR/NOR 2 k gates with more than 4 inputs and XOR/XNOR k1 k gates with more than 3 inputs. It can be seen in Figure 1 that GEM values tend to decrease with Since the NOT gate is just a simple inverter, increase in fan-in for all types of gates, which is producing complemented values of inputs at its desirable. In previous works [5] [6], output error outputs, its GEM equation reduces to a constant of probabilities of XOR/XNOR gates were found to 1. But this GEM value is very high of all the logic increase with increase in fan-in – however this is gates considered.
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