AC701 Evaluation Board for the Artix-7 FPGA User Guide (UG952)
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AC701 Evaluation Board for the Artix-7 FPGA User Guide UG952 (v1.4) August 6, 2019 DISCLAIMER The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. © Copyright 2012–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG and used under license. HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks of HDMI Licensing LLC. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 10/23/2012 1.0 Initial Xilinx release. 01/30/2013 1.1 Updated photograph in Figure 1-2, page 11 to revision 1.0 of the AC701 board. Revised Figure 1-3. Revised last paragraph under DDR3 Memory Module, page 15, fourth paragraph under USB JTAG Module, page 23, third paragraph under GTP Transceivers, page 35, first paragraph under U3 IN0: 125 MHz Clock Generator, page 33, first, second and third paragraphs under U3/U4 IN2: FMC HPC GBT Clocks, page 35, fourth paragraph under PCI Express Edge Connector, page 38, and the first paragraph under SFP/SFP+ Connector, page 39. Revised third and fourth rows in Table 1-13, page 40 and the fifth row in Table 1-14, page 40. Revised second paragraph and added fourth paragraph under LCD Character Display, page 47. Revised first paragraph under I2C Bus Switch, page 49. Added Figure 1-32, page 53, Figure 1-34, page 53 and Figure 1-35, page 54. Revised Figure 1-41, page 57. Added section AC701 Board Power System, page 67 and section XADC Power System Measurement, page 72. Added third paragraph under Power Management, page 62. Revised Figure 1-49, page 78. Revised Figure A-2, page 82. Updated the Xilinx Design Constraints in Appendix C. Added Appendix F, Regulatory and Compliance Information. 08/28/2013 1.2 Added Figure 1-10. Revised Figure 1-2, Figure 1-49, and Figure 1-50. AC701 Evaluation Board www.xilinx.com UG952 (v1.4) August 6, 2019 Date Version Revision 04/07/2015 1.3 Replaced the board photo in Figure 1-2 with the Rev 2.0 board. Added callout row to GTP transceiver clock multiplexers in Table 1-1. Replaced Table 1-4, Table 1-5, Table 1-7, and Table 1-8. Replaced I/O banks 32, 33, and 34 with banks 33, 34, and 35 in DDR3 Memory Module, page 15. Updated Figure 1-10. Major revision of GTP Transceiver Clock Multiplexer section, starting on page 28. Added note to Table 1-13. Replaced Table 1-16, Table 1-19, Table 1-21, Table 1-23, and Table 1-26. Updated Figure 1-42. Voltage regulators changed in section AC701 Board Power System, page 67. Updated device types and footnotes in Table 1-27 to reflect device changes. Updated Figure 1-44 and Figure 1-45. Changed Texas Instruments parts numbers to LMZ31710 and LMZ31704 in [Ref 22]. Changed XADC_GPIO_3, 2, 1, 0 description in Table 1-35. Added Figure A-3 to show board components called out in Table A-3. Updated the Artix-7 FPGA AC701 Declaration of Conformity link in Appendix F, Regulatory and Compliance Information. 08/06/2019 1.4 Updated DDR3 Memory Module section. Changed Appendix C, Xilinx Design Constraints. Updated the Appendix F, Regulatory and Compliance Information. UG952 (v1.4) August 6, 2019 www.xilinx.com AC701 Evaluation Board AC701 Evaluation Board www.xilinx.com UG952 (v1.4) August 6, 2019 Table of Contents Revision History . 2 Chapter 1: AC701 Evaluation Board Features Overview . 7 Additional Information . 7 AC701 Board Features . 7 Electrostatic Discharge Caution . 9 Feature Descriptions . 11 Artix-7 FPGA . 13 DDR3 Memory Module . 15 Quad SPI Flash Memory . 20 SPI Flash Memory External Programming Header . 21 SD Card Interface . 22 USB JTAG Module . 23 Clock Generation . 24 GTP Transceivers . 35 PCI Express Edge Connector . 38 SFP/SFP+ Connector . 39 10/100/1000 Mb/s Tri-Speed Ethernet PHY . 41 Ethernet PHY User LEDs . 43 USB-to-UART Bridge . 43 HDMI Video Output . 44 LCD Character Display . 47 I2C Bus Switch . 49 AC701 Board LEDs . 50 User I/O . 51 Switches . 56 FPGA Mezzanine Card Interface . 58 Power Management . 62 AC701 Board Power System . 67 XADC Power System Measurement . 72 XADC Header . 76 Configuration Options . 78 Appendix A: Default Switch and Jumper Settings User GPIO DIP Switch SW2 . 81 Configuration DIP Switch SW1 . 82 Default Jumper Settings . 83 AC701 Evaluation Board www.xilinx.com Send Feedback 5 UG952 (v1.4) August 5, 2019 Appendix B: VITA 57.1 FMC Connector Pinouts Appendix C: Xilinx Design Constraints Appendix D: Board Setup Installing the AC701 Board in a PC Chassis . 89 Appendix E: Board Specifications Dimensions . 91 Environmental . 91 Temperature . 91 Humidity . 91 Operating Voltage . 91 Appendix F: Regulatory and Compliance Information Overview . 93 CE Directives . 93 CE Standards . 93 Electromagnetic Compatibility . 93 Safety . ..